qcs405.c 232 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/input.h>
  22. #include <linux/of_device.h>
  23. #include <linux/pm_qos.h>
  24. #include <sound/core.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/info.h>
  30. #include <dsp/audio_notifier.h>
  31. #include <dsp/q6afe-v2.h>
  32. #include <dsp/q6core.h>
  33. #include "device_event.h"
  34. #include "msm-pcm-routing-v2.h"
  35. #include "codecs/msm-cdc-pinctrl.h"
  36. #include "codecs/wcd9335.h"
  37. #include "codecs/wsa881x.h"
  38. #include "codecs/csra66x0/csra66x0.h"
  39. #include <dt-bindings/sound/audio-codec-port-types.h>
  40. #include "codecs/bolero/bolero-cdc.h"
  41. #include "codecs/bolero/wsa-macro.h"
  42. #define DRV_NAME "qcs405-asoc-snd"
  43. #define __CHIPSET__ "QCS405 "
  44. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  45. #define DEV_NAME_STR_LEN 32
  46. #define SAMPLING_RATE_8KHZ 8000
  47. #define SAMPLING_RATE_11P025KHZ 11025
  48. #define SAMPLING_RATE_16KHZ 16000
  49. #define SAMPLING_RATE_22P05KHZ 22050
  50. #define SAMPLING_RATE_32KHZ 32000
  51. #define SAMPLING_RATE_44P1KHZ 44100
  52. #define SAMPLING_RATE_48KHZ 48000
  53. #define SAMPLING_RATE_88P2KHZ 88200
  54. #define SAMPLING_RATE_96KHZ 96000
  55. #define SAMPLING_RATE_176P4KHZ 176400
  56. #define SAMPLING_RATE_192KHZ 192000
  57. #define SAMPLING_RATE_352P8KHZ 352800
  58. #define SAMPLING_RATE_384KHZ 384000
  59. #define SPDIF_TX_CORE_CLK_204_P8_MHZ 204800000
  60. #define TLMM_EAST_SPARE 0x07BA0000
  61. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  62. #define WSA8810_NAME_1 "wsa881x.20170211"
  63. #define WSA8810_NAME_2 "wsa881x.20170212"
  64. #define WCN_CDC_SLIM_RX_CH_MAX 2
  65. #define WCN_CDC_SLIM_TX_CH_MAX 3
  66. #define TDM_CHANNEL_MAX 8
  67. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  68. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  69. enum {
  70. SLIM_RX_0 = 0,
  71. SLIM_RX_1,
  72. SLIM_RX_2,
  73. SLIM_RX_3,
  74. SLIM_RX_4,
  75. SLIM_RX_5,
  76. SLIM_RX_6,
  77. SLIM_RX_7,
  78. SLIM_RX_MAX,
  79. };
  80. enum {
  81. SLIM_TX_0 = 0,
  82. SLIM_TX_1,
  83. SLIM_TX_2,
  84. SLIM_TX_3,
  85. SLIM_TX_4,
  86. SLIM_TX_5,
  87. SLIM_TX_6,
  88. SLIM_TX_7,
  89. SLIM_TX_8,
  90. SLIM_TX_MAX,
  91. };
  92. enum {
  93. PRIM_MI2S = 0,
  94. SEC_MI2S,
  95. TERT_MI2S,
  96. QUAT_MI2S,
  97. QUIN_MI2S,
  98. MI2S_MAX,
  99. };
  100. enum {
  101. PRIM_AUX_PCM = 0,
  102. SEC_AUX_PCM,
  103. TERT_AUX_PCM,
  104. QUAT_AUX_PCM,
  105. QUIN_AUX_PCM,
  106. AUX_PCM_MAX,
  107. };
  108. enum {
  109. WSA_CDC_DMA_RX_0 = 0,
  110. WSA_CDC_DMA_RX_1,
  111. CDC_DMA_RX_MAX,
  112. };
  113. enum {
  114. WSA_CDC_DMA_TX_0 = 0,
  115. WSA_CDC_DMA_TX_1,
  116. WSA_CDC_DMA_TX_2,
  117. VA_CDC_DMA_TX_0,
  118. VA_CDC_DMA_TX_1,
  119. CDC_DMA_TX_MAX,
  120. };
  121. enum {
  122. PRIM_SPDIF_RX = 0,
  123. SEC_SPDIF_RX,
  124. SPDIF_RX_MAX,
  125. };
  126. enum {
  127. PRIM_SPDIF_TX = 0,
  128. SEC_SPDIF_TX,
  129. SPDIF_TX_MAX,
  130. };
  131. struct mi2s_conf {
  132. struct mutex lock;
  133. u32 ref_cnt;
  134. u32 msm_is_mi2s_master;
  135. };
  136. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  137. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  141. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  142. };
  143. struct dev_config {
  144. u32 sample_rate;
  145. u32 bit_format;
  146. u32 channels;
  147. };
  148. struct msm_wsa881x_dev_info {
  149. struct device_node *of_node;
  150. u32 index;
  151. };
  152. struct msm_csra66x0_dev_info {
  153. struct device_node *of_node;
  154. u32 index;
  155. };
  156. enum pinctrl_pin_state {
  157. STATE_DISABLE = 0, /* All pins are in sleep state */
  158. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  159. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  160. };
  161. struct msm_pinctrl_info {
  162. struct pinctrl *pinctrl;
  163. struct pinctrl_state *mi2s_disable;
  164. struct pinctrl_state *tdm_disable;
  165. struct pinctrl_state *mi2s_active;
  166. struct pinctrl_state *tdm_active;
  167. enum pinctrl_pin_state curr_state;
  168. };
  169. struct msm_asoc_mach_data {
  170. struct snd_info_entry *codec_root;
  171. struct msm_pinctrl_info pinctrl_info;
  172. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  173. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  174. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  175. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  176. int dmic_01_gpio_cnt;
  177. int dmic_23_gpio_cnt;
  178. int dmic_45_gpio_cnt;
  179. int dmic_67_gpio_cnt;
  180. };
  181. struct msm_asoc_wcd93xx_codec {
  182. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  183. enum afe_config_type config_type);
  184. };
  185. static const char *const pin_states[] = {"sleep", "i2s-active",
  186. "tdm-active"};
  187. enum {
  188. TDM_0 = 0,
  189. TDM_1,
  190. TDM_2,
  191. TDM_3,
  192. TDM_4,
  193. TDM_5,
  194. TDM_6,
  195. TDM_7,
  196. TDM_PORT_MAX,
  197. };
  198. enum {
  199. TDM_PRI = 0,
  200. TDM_SEC,
  201. TDM_TERT,
  202. TDM_QUAT,
  203. TDM_QUIN,
  204. TDM_INTERFACE_MAX,
  205. };
  206. struct tdm_port {
  207. u32 mode;
  208. u32 channel;
  209. };
  210. /* TDM default config */
  211. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  212. { /* PRI TDM */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  221. },
  222. { /* SEC TDM */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  231. },
  232. { /* TERT TDM */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  241. },
  242. { /* QUAT TDM */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  251. },
  252. { /* QUIN TDM */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  261. }
  262. };
  263. /* TDM default config */
  264. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  265. { /* PRI TDM */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  274. },
  275. { /* SEC TDM */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  284. },
  285. { /* TERT TDM */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  294. },
  295. { /* QUAT TDM */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  304. },
  305. { /* QUIN TDM */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  314. }
  315. };
  316. /* Default configuration of slimbus channels */
  317. static struct dev_config slim_rx_cfg[] = {
  318. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. };
  327. static struct dev_config slim_tx_cfg[] = {
  328. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  337. };
  338. /* Default configuration of Codec DMA Interface Tx */
  339. static struct dev_config cdc_dma_rx_cfg[] = {
  340. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  341. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  342. };
  343. /* Default configuration of Codec DMA Interface Rx */
  344. static struct dev_config cdc_dma_tx_cfg[] = {
  345. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  346. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  349. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  350. };
  351. static struct dev_config usb_rx_cfg = {
  352. .sample_rate = SAMPLING_RATE_48KHZ,
  353. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  354. .channels = 2,
  355. };
  356. static struct dev_config usb_tx_cfg = {
  357. .sample_rate = SAMPLING_RATE_48KHZ,
  358. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  359. .channels = 1,
  360. };
  361. static struct dev_config proxy_rx_cfg = {
  362. .sample_rate = SAMPLING_RATE_48KHZ,
  363. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  364. .channels = 2,
  365. };
  366. /* Default configuration of MI2S channels */
  367. static struct dev_config mi2s_rx_cfg[] = {
  368. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  369. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  372. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. };
  374. /* Default configuration of SPDIF channels */
  375. static struct dev_config spdif_rx_cfg[] = {
  376. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  377. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  378. };
  379. static struct dev_config spdif_tx_cfg[] = {
  380. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  381. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  382. };
  383. static struct dev_config mi2s_tx_cfg[] = {
  384. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  385. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. };
  390. static struct dev_config aux_pcm_rx_cfg[] = {
  391. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  392. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. };
  397. static struct dev_config aux_pcm_tx_cfg[] = {
  398. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. };
  404. static int msm_vi_feed_tx_ch = 2;
  405. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  406. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  407. "Five", "Six", "Seven",
  408. "Eight"};
  409. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  410. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  411. "S32_LE"};
  412. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  413. "KHZ_32", "KHZ_44P1", "KHZ_48",
  414. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  415. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  416. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  417. "KHZ_44P1", "KHZ_48",
  418. "KHZ_88P2", "KHZ_96"};
  419. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  420. "Five", "Six", "Seven",
  421. "Eight"};
  422. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  423. "Six", "Seven", "Eight"};
  424. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  425. "KHZ_16", "KHZ_22P05",
  426. "KHZ_32", "KHZ_44P1", "KHZ_48",
  427. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  428. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  429. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  430. "Five", "Six", "Seven", "Eight"};
  431. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  432. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  433. "KHZ_48", "KHZ_176P4",
  434. "KHZ_352P8"};
  435. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  436. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  437. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  438. "KHZ_48", "KHZ_96", "KHZ_192"};
  439. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  440. "Five", "Six", "Seven",
  441. "Eight"};
  442. static const char *const qos_text[] = {"Disable", "Enable"};
  443. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  444. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  445. "Five", "Six", "Seven",
  446. "Eight"};
  447. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  448. "KHZ_16", "KHZ_22P05",
  449. "KHZ_32", "KHZ_44P1", "KHZ_48",
  450. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  451. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  452. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  453. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  454. "KHZ_192"};
  455. static const char *spdif_ch_text[] = {"One", "Two"};
  456. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  457. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  535. cdc_dma_sample_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  537. cdc_dma_sample_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  539. cdc_dma_sample_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  541. cdc_dma_sample_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  543. cdc_dma_sample_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  545. cdc_dma_sample_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  547. cdc_dma_sample_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  554. static struct platform_device *spdev;
  555. static bool is_initial_boot;
  556. static bool codec_reg_done;
  557. static struct snd_soc_aux_dev *msm_aux_dev;
  558. static struct snd_soc_codec_conf *msm_codec_conf;
  559. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  560. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  561. int enable, bool dapm);
  562. static int msm_wsa881x_init(struct snd_soc_component *component);
  563. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  564. struct snd_ctl_elem_value *ucontrol);
  565. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  566. {"MIC BIAS1", NULL, "MCLK TX"},
  567. {"MIC BIAS2", NULL, "MCLK TX"},
  568. {"MIC BIAS3", NULL, "MCLK TX"},
  569. {"MIC BIAS4", NULL, "MCLK TX"},
  570. };
  571. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  572. {
  573. AFE_API_VERSION_I2S_CONFIG,
  574. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  575. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  576. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  577. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  578. 0,
  579. },
  580. {
  581. AFE_API_VERSION_I2S_CONFIG,
  582. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  583. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  584. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  585. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  586. 0,
  587. },
  588. {
  589. AFE_API_VERSION_I2S_CONFIG,
  590. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  591. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  592. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  593. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  594. 0,
  595. },
  596. {
  597. AFE_API_VERSION_I2S_CONFIG,
  598. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  599. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  600. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  601. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  602. 0,
  603. },
  604. {
  605. AFE_API_VERSION_I2S_CONFIG,
  606. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  607. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  608. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  609. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  610. 0,
  611. }
  612. };
  613. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  614. static int slim_get_sample_rate_val(int sample_rate)
  615. {
  616. int sample_rate_val = 0;
  617. switch (sample_rate) {
  618. case SAMPLING_RATE_8KHZ:
  619. sample_rate_val = 0;
  620. break;
  621. case SAMPLING_RATE_16KHZ:
  622. sample_rate_val = 1;
  623. break;
  624. case SAMPLING_RATE_32KHZ:
  625. sample_rate_val = 2;
  626. break;
  627. case SAMPLING_RATE_44P1KHZ:
  628. sample_rate_val = 3;
  629. break;
  630. case SAMPLING_RATE_48KHZ:
  631. sample_rate_val = 4;
  632. break;
  633. case SAMPLING_RATE_88P2KHZ:
  634. sample_rate_val = 5;
  635. break;
  636. case SAMPLING_RATE_96KHZ:
  637. sample_rate_val = 6;
  638. break;
  639. case SAMPLING_RATE_176P4KHZ:
  640. sample_rate_val = 7;
  641. break;
  642. case SAMPLING_RATE_192KHZ:
  643. sample_rate_val = 8;
  644. break;
  645. case SAMPLING_RATE_352P8KHZ:
  646. sample_rate_val = 9;
  647. break;
  648. case SAMPLING_RATE_384KHZ:
  649. sample_rate_val = 10;
  650. break;
  651. default:
  652. sample_rate_val = 4;
  653. break;
  654. }
  655. return sample_rate_val;
  656. }
  657. static int slim_get_sample_rate(int value)
  658. {
  659. int sample_rate = 0;
  660. switch (value) {
  661. case 0:
  662. sample_rate = SAMPLING_RATE_8KHZ;
  663. break;
  664. case 1:
  665. sample_rate = SAMPLING_RATE_16KHZ;
  666. break;
  667. case 2:
  668. sample_rate = SAMPLING_RATE_32KHZ;
  669. break;
  670. case 3:
  671. sample_rate = SAMPLING_RATE_44P1KHZ;
  672. break;
  673. case 4:
  674. sample_rate = SAMPLING_RATE_48KHZ;
  675. break;
  676. case 5:
  677. sample_rate = SAMPLING_RATE_88P2KHZ;
  678. break;
  679. case 6:
  680. sample_rate = SAMPLING_RATE_96KHZ;
  681. break;
  682. case 7:
  683. sample_rate = SAMPLING_RATE_176P4KHZ;
  684. break;
  685. case 8:
  686. sample_rate = SAMPLING_RATE_192KHZ;
  687. break;
  688. case 9:
  689. sample_rate = SAMPLING_RATE_352P8KHZ;
  690. break;
  691. case 10:
  692. sample_rate = SAMPLING_RATE_384KHZ;
  693. break;
  694. default:
  695. sample_rate = SAMPLING_RATE_48KHZ;
  696. break;
  697. }
  698. return sample_rate;
  699. }
  700. static int slim_get_bit_format_val(int bit_format)
  701. {
  702. int val = 0;
  703. switch (bit_format) {
  704. case SNDRV_PCM_FORMAT_S32_LE:
  705. val = 3;
  706. break;
  707. case SNDRV_PCM_FORMAT_S24_3LE:
  708. val = 2;
  709. break;
  710. case SNDRV_PCM_FORMAT_S24_LE:
  711. val = 1;
  712. break;
  713. case SNDRV_PCM_FORMAT_S16_LE:
  714. default:
  715. val = 0;
  716. break;
  717. }
  718. return val;
  719. }
  720. static int slim_get_bit_format(int val)
  721. {
  722. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  723. switch (val) {
  724. case 0:
  725. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  726. break;
  727. case 1:
  728. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  729. break;
  730. case 2:
  731. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  732. break;
  733. case 3:
  734. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  735. break;
  736. default:
  737. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  738. break;
  739. }
  740. return bit_fmt;
  741. }
  742. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  743. {
  744. int port_id = 0;
  745. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  746. port_id = SLIM_RX_0;
  747. } else if (strnstr(kcontrol->id.name,
  748. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  749. port_id = SLIM_RX_2;
  750. } else if (strnstr(kcontrol->id.name,
  751. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  752. port_id = SLIM_RX_5;
  753. } else if (strnstr(kcontrol->id.name,
  754. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  755. port_id = SLIM_RX_6;
  756. } else if (strnstr(kcontrol->id.name,
  757. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  758. port_id = SLIM_TX_0;
  759. } else if (strnstr(kcontrol->id.name,
  760. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  761. port_id = SLIM_TX_1;
  762. } else {
  763. pr_err("%s: unsupported channel: %s",
  764. __func__, kcontrol->id.name);
  765. return -EINVAL;
  766. }
  767. return port_id;
  768. }
  769. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  770. struct snd_ctl_elem_value *ucontrol)
  771. {
  772. int ch_num = slim_get_port_idx(kcontrol);
  773. if (ch_num < 0)
  774. return ch_num;
  775. ucontrol->value.enumerated.item[0] =
  776. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  777. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  778. ch_num, slim_rx_cfg[ch_num].sample_rate,
  779. ucontrol->value.enumerated.item[0]);
  780. return 0;
  781. }
  782. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  783. struct snd_ctl_elem_value *ucontrol)
  784. {
  785. int ch_num = slim_get_port_idx(kcontrol);
  786. if (ch_num < 0)
  787. return ch_num;
  788. slim_rx_cfg[ch_num].sample_rate =
  789. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  790. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  791. ch_num, slim_rx_cfg[ch_num].sample_rate,
  792. ucontrol->value.enumerated.item[0]);
  793. return 0;
  794. }
  795. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  796. struct snd_ctl_elem_value *ucontrol)
  797. {
  798. int ch_num = slim_get_port_idx(kcontrol);
  799. if (ch_num < 0)
  800. return ch_num;
  801. ucontrol->value.enumerated.item[0] =
  802. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  803. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  804. ch_num, slim_tx_cfg[ch_num].sample_rate,
  805. ucontrol->value.enumerated.item[0]);
  806. return 0;
  807. }
  808. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  809. struct snd_ctl_elem_value *ucontrol)
  810. {
  811. int sample_rate = 0;
  812. int ch_num = slim_get_port_idx(kcontrol);
  813. if (ch_num < 0)
  814. return ch_num;
  815. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  816. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  817. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  818. __func__, sample_rate);
  819. return -EINVAL;
  820. }
  821. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  822. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  823. ch_num, slim_tx_cfg[ch_num].sample_rate,
  824. ucontrol->value.enumerated.item[0]);
  825. return 0;
  826. }
  827. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  828. struct snd_ctl_elem_value *ucontrol)
  829. {
  830. int ch_num = slim_get_port_idx(kcontrol);
  831. if (ch_num < 0)
  832. return ch_num;
  833. ucontrol->value.enumerated.item[0] =
  834. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  835. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  836. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  837. ucontrol->value.enumerated.item[0]);
  838. return 0;
  839. }
  840. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  841. struct snd_ctl_elem_value *ucontrol)
  842. {
  843. int ch_num = slim_get_port_idx(kcontrol);
  844. if (ch_num < 0)
  845. return ch_num;
  846. slim_rx_cfg[ch_num].bit_format =
  847. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  848. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  849. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  850. ucontrol->value.enumerated.item[0]);
  851. return 0;
  852. }
  853. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  854. struct snd_ctl_elem_value *ucontrol)
  855. {
  856. int ch_num = slim_get_port_idx(kcontrol);
  857. if (ch_num < 0)
  858. return ch_num;
  859. ucontrol->value.enumerated.item[0] =
  860. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  861. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  862. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  863. ucontrol->value.enumerated.item[0]);
  864. return 0;
  865. }
  866. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  867. struct snd_ctl_elem_value *ucontrol)
  868. {
  869. int ch_num = slim_get_port_idx(kcontrol);
  870. if (ch_num < 0)
  871. return ch_num;
  872. slim_tx_cfg[ch_num].bit_format =
  873. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  874. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  875. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  876. ucontrol->value.enumerated.item[0]);
  877. return 0;
  878. }
  879. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  880. struct snd_ctl_elem_value *ucontrol)
  881. {
  882. int ch_num = slim_get_port_idx(kcontrol);
  883. if (ch_num < 0)
  884. return ch_num;
  885. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  886. ch_num, slim_rx_cfg[ch_num].channels);
  887. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  888. return 0;
  889. }
  890. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  891. struct snd_ctl_elem_value *ucontrol)
  892. {
  893. int ch_num = slim_get_port_idx(kcontrol);
  894. if (ch_num < 0)
  895. return ch_num;
  896. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  897. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  898. ch_num, slim_rx_cfg[ch_num].channels);
  899. return 1;
  900. }
  901. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  902. struct snd_ctl_elem_value *ucontrol)
  903. {
  904. int ch_num = slim_get_port_idx(kcontrol);
  905. if (ch_num < 0)
  906. return ch_num;
  907. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  908. ch_num, slim_tx_cfg[ch_num].channels);
  909. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  910. return 0;
  911. }
  912. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  913. struct snd_ctl_elem_value *ucontrol)
  914. {
  915. int ch_num = slim_get_port_idx(kcontrol);
  916. if (ch_num < 0)
  917. return ch_num;
  918. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  919. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  920. ch_num, slim_tx_cfg[ch_num].channels);
  921. return 1;
  922. }
  923. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  924. struct snd_ctl_elem_value *ucontrol)
  925. {
  926. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  927. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  928. ucontrol->value.integer.value[0]);
  929. return 0;
  930. }
  931. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  932. struct snd_ctl_elem_value *ucontrol)
  933. {
  934. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  935. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  936. return 1;
  937. }
  938. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  939. struct snd_ctl_elem_value *ucontrol)
  940. {
  941. /*
  942. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  943. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  944. * value.
  945. */
  946. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  947. case SAMPLING_RATE_96KHZ:
  948. ucontrol->value.integer.value[0] = 5;
  949. break;
  950. case SAMPLING_RATE_88P2KHZ:
  951. ucontrol->value.integer.value[0] = 4;
  952. break;
  953. case SAMPLING_RATE_48KHZ:
  954. ucontrol->value.integer.value[0] = 3;
  955. break;
  956. case SAMPLING_RATE_44P1KHZ:
  957. ucontrol->value.integer.value[0] = 2;
  958. break;
  959. case SAMPLING_RATE_16KHZ:
  960. ucontrol->value.integer.value[0] = 1;
  961. break;
  962. case SAMPLING_RATE_8KHZ:
  963. default:
  964. ucontrol->value.integer.value[0] = 0;
  965. break;
  966. }
  967. pr_debug("%s: sample rate = %d", __func__,
  968. slim_rx_cfg[SLIM_RX_7].sample_rate);
  969. return 0;
  970. }
  971. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  972. struct snd_ctl_elem_value *ucontrol)
  973. {
  974. switch (ucontrol->value.integer.value[0]) {
  975. case 1:
  976. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  977. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  978. break;
  979. case 2:
  980. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  981. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  982. break;
  983. case 3:
  984. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  985. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  986. break;
  987. case 4:
  988. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  989. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  990. break;
  991. case 5:
  992. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  993. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  994. break;
  995. case 0:
  996. default:
  997. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  998. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  999. break;
  1000. }
  1001. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1002. __func__,
  1003. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1004. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1005. ucontrol->value.enumerated.item[0]);
  1006. return 0;
  1007. }
  1008. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1009. {
  1010. int idx = 0;
  1011. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1012. sizeof("WSA_CDC_DMA_RX_0")))
  1013. idx = WSA_CDC_DMA_RX_0;
  1014. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1015. sizeof("WSA_CDC_DMA_RX_0")))
  1016. idx = WSA_CDC_DMA_RX_1;
  1017. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1018. sizeof("WSA_CDC_DMA_TX_0")))
  1019. idx = WSA_CDC_DMA_TX_0;
  1020. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1021. sizeof("WSA_CDC_DMA_TX_1")))
  1022. idx = WSA_CDC_DMA_TX_1;
  1023. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1024. sizeof("WSA_CDC_DMA_TX_2")))
  1025. idx = WSA_CDC_DMA_TX_2;
  1026. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1027. sizeof("VA_CDC_DMA_TX_0")))
  1028. idx = VA_CDC_DMA_TX_0;
  1029. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1030. sizeof("VA_CDC_DMA_TX_1")))
  1031. idx = VA_CDC_DMA_TX_1;
  1032. else {
  1033. pr_err("%s: unsupported port: %s\n",
  1034. __func__, kcontrol->id.name);
  1035. return -EINVAL;
  1036. }
  1037. return idx;
  1038. }
  1039. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1040. struct snd_ctl_elem_value *ucontrol)
  1041. {
  1042. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1043. if (ch_num < 0)
  1044. return ch_num;
  1045. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1046. cdc_dma_rx_cfg[ch_num].channels - 1);
  1047. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1048. return 0;
  1049. }
  1050. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1051. struct snd_ctl_elem_value *ucontrol)
  1052. {
  1053. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1054. if (ch_num < 0)
  1055. return ch_num;
  1056. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1057. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1058. cdc_dma_rx_cfg[ch_num].channels);
  1059. return 1;
  1060. }
  1061. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1062. struct snd_ctl_elem_value *ucontrol)
  1063. {
  1064. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1065. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1066. case SNDRV_PCM_FORMAT_S32_LE:
  1067. ucontrol->value.integer.value[0] = 3;
  1068. break;
  1069. case SNDRV_PCM_FORMAT_S24_3LE:
  1070. ucontrol->value.integer.value[0] = 2;
  1071. break;
  1072. case SNDRV_PCM_FORMAT_S24_LE:
  1073. ucontrol->value.integer.value[0] = 1;
  1074. break;
  1075. case SNDRV_PCM_FORMAT_S16_LE:
  1076. default:
  1077. ucontrol->value.integer.value[0] = 0;
  1078. break;
  1079. }
  1080. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1081. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1082. ucontrol->value.integer.value[0]);
  1083. return 0;
  1084. }
  1085. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1086. struct snd_ctl_elem_value *ucontrol)
  1087. {
  1088. int rc = 0;
  1089. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1090. switch (ucontrol->value.integer.value[0]) {
  1091. case 3:
  1092. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1093. break;
  1094. case 2:
  1095. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1096. break;
  1097. case 1:
  1098. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1099. break;
  1100. case 0:
  1101. default:
  1102. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1103. break;
  1104. }
  1105. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1106. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1107. ucontrol->value.integer.value[0]);
  1108. return rc;
  1109. }
  1110. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1111. {
  1112. int sample_rate_val = 0;
  1113. switch (sample_rate) {
  1114. case SAMPLING_RATE_8KHZ:
  1115. sample_rate_val = 0;
  1116. break;
  1117. case SAMPLING_RATE_16KHZ:
  1118. sample_rate_val = 1;
  1119. break;
  1120. case SAMPLING_RATE_32KHZ:
  1121. sample_rate_val = 2;
  1122. break;
  1123. case SAMPLING_RATE_44P1KHZ:
  1124. sample_rate_val = 3;
  1125. break;
  1126. case SAMPLING_RATE_48KHZ:
  1127. sample_rate_val = 4;
  1128. break;
  1129. case SAMPLING_RATE_88P2KHZ:
  1130. sample_rate_val = 5;
  1131. break;
  1132. case SAMPLING_RATE_96KHZ:
  1133. sample_rate_val = 6;
  1134. break;
  1135. case SAMPLING_RATE_176P4KHZ:
  1136. sample_rate_val = 7;
  1137. break;
  1138. case SAMPLING_RATE_192KHZ:
  1139. sample_rate_val = 8;
  1140. break;
  1141. case SAMPLING_RATE_352P8KHZ:
  1142. sample_rate_val = 9;
  1143. break;
  1144. case SAMPLING_RATE_384KHZ:
  1145. sample_rate_val = 10;
  1146. break;
  1147. default:
  1148. sample_rate_val = 4;
  1149. break;
  1150. }
  1151. return sample_rate_val;
  1152. }
  1153. static int cdc_dma_get_sample_rate(int value)
  1154. {
  1155. int sample_rate = 0;
  1156. switch (value) {
  1157. case 0:
  1158. sample_rate = SAMPLING_RATE_8KHZ;
  1159. break;
  1160. case 1:
  1161. sample_rate = SAMPLING_RATE_16KHZ;
  1162. break;
  1163. case 2:
  1164. sample_rate = SAMPLING_RATE_32KHZ;
  1165. break;
  1166. case 3:
  1167. sample_rate = SAMPLING_RATE_44P1KHZ;
  1168. break;
  1169. case 4:
  1170. sample_rate = SAMPLING_RATE_48KHZ;
  1171. break;
  1172. case 5:
  1173. sample_rate = SAMPLING_RATE_88P2KHZ;
  1174. break;
  1175. case 6:
  1176. sample_rate = SAMPLING_RATE_96KHZ;
  1177. break;
  1178. case 7:
  1179. sample_rate = SAMPLING_RATE_176P4KHZ;
  1180. break;
  1181. case 8:
  1182. sample_rate = SAMPLING_RATE_192KHZ;
  1183. break;
  1184. case 9:
  1185. sample_rate = SAMPLING_RATE_352P8KHZ;
  1186. break;
  1187. case 10:
  1188. sample_rate = SAMPLING_RATE_384KHZ;
  1189. break;
  1190. default:
  1191. sample_rate = SAMPLING_RATE_48KHZ;
  1192. break;
  1193. }
  1194. return sample_rate;
  1195. }
  1196. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1197. struct snd_ctl_elem_value *ucontrol)
  1198. {
  1199. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1200. if (ch_num < 0)
  1201. return ch_num;
  1202. ucontrol->value.enumerated.item[0] =
  1203. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1204. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1205. cdc_dma_rx_cfg[ch_num].sample_rate);
  1206. return 0;
  1207. }
  1208. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1209. struct snd_ctl_elem_value *ucontrol)
  1210. {
  1211. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1212. if (ch_num < 0)
  1213. return ch_num;
  1214. cdc_dma_rx_cfg[ch_num].sample_rate =
  1215. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1216. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1217. __func__, ucontrol->value.enumerated.item[0],
  1218. cdc_dma_rx_cfg[ch_num].sample_rate);
  1219. return 0;
  1220. }
  1221. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1222. struct snd_ctl_elem_value *ucontrol)
  1223. {
  1224. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1225. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1226. cdc_dma_tx_cfg[ch_num].channels);
  1227. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1228. return 0;
  1229. }
  1230. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1231. struct snd_ctl_elem_value *ucontrol)
  1232. {
  1233. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1234. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1235. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1236. cdc_dma_tx_cfg[ch_num].channels);
  1237. return 1;
  1238. }
  1239. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1240. struct snd_ctl_elem_value *ucontrol)
  1241. {
  1242. int sample_rate_val;
  1243. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1244. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1245. case SAMPLING_RATE_384KHZ:
  1246. sample_rate_val = 12;
  1247. break;
  1248. case SAMPLING_RATE_352P8KHZ:
  1249. sample_rate_val = 11;
  1250. break;
  1251. case SAMPLING_RATE_192KHZ:
  1252. sample_rate_val = 10;
  1253. break;
  1254. case SAMPLING_RATE_176P4KHZ:
  1255. sample_rate_val = 9;
  1256. break;
  1257. case SAMPLING_RATE_96KHZ:
  1258. sample_rate_val = 8;
  1259. break;
  1260. case SAMPLING_RATE_88P2KHZ:
  1261. sample_rate_val = 7;
  1262. break;
  1263. case SAMPLING_RATE_48KHZ:
  1264. sample_rate_val = 6;
  1265. break;
  1266. case SAMPLING_RATE_44P1KHZ:
  1267. sample_rate_val = 5;
  1268. break;
  1269. case SAMPLING_RATE_32KHZ:
  1270. sample_rate_val = 4;
  1271. break;
  1272. case SAMPLING_RATE_22P05KHZ:
  1273. sample_rate_val = 3;
  1274. break;
  1275. case SAMPLING_RATE_16KHZ:
  1276. sample_rate_val = 2;
  1277. break;
  1278. case SAMPLING_RATE_11P025KHZ:
  1279. sample_rate_val = 1;
  1280. break;
  1281. case SAMPLING_RATE_8KHZ:
  1282. sample_rate_val = 0;
  1283. break;
  1284. default:
  1285. sample_rate_val = 6;
  1286. break;
  1287. }
  1288. ucontrol->value.integer.value[0] = sample_rate_val;
  1289. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1290. cdc_dma_tx_cfg[ch_num].sample_rate);
  1291. return 0;
  1292. }
  1293. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1294. struct snd_ctl_elem_value *ucontrol)
  1295. {
  1296. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1297. switch (ucontrol->value.integer.value[0]) {
  1298. case 12:
  1299. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1300. break;
  1301. case 11:
  1302. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1303. break;
  1304. case 10:
  1305. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1306. break;
  1307. case 9:
  1308. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1309. break;
  1310. case 8:
  1311. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1312. break;
  1313. case 7:
  1314. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1315. break;
  1316. case 6:
  1317. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1318. break;
  1319. case 5:
  1320. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1321. break;
  1322. case 4:
  1323. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1324. break;
  1325. case 3:
  1326. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1327. break;
  1328. case 2:
  1329. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1330. break;
  1331. case 1:
  1332. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1333. break;
  1334. case 0:
  1335. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1336. break;
  1337. default:
  1338. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1339. break;
  1340. }
  1341. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1342. __func__, ucontrol->value.integer.value[0],
  1343. cdc_dma_tx_cfg[ch_num].sample_rate);
  1344. return 0;
  1345. }
  1346. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1347. struct snd_ctl_elem_value *ucontrol)
  1348. {
  1349. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1350. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1351. case SNDRV_PCM_FORMAT_S32_LE:
  1352. ucontrol->value.integer.value[0] = 3;
  1353. break;
  1354. case SNDRV_PCM_FORMAT_S24_3LE:
  1355. ucontrol->value.integer.value[0] = 2;
  1356. break;
  1357. case SNDRV_PCM_FORMAT_S24_LE:
  1358. ucontrol->value.integer.value[0] = 1;
  1359. break;
  1360. case SNDRV_PCM_FORMAT_S16_LE:
  1361. default:
  1362. ucontrol->value.integer.value[0] = 0;
  1363. break;
  1364. }
  1365. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1366. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1367. ucontrol->value.integer.value[0]);
  1368. return 0;
  1369. }
  1370. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1371. struct snd_ctl_elem_value *ucontrol)
  1372. {
  1373. int rc = 0;
  1374. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1375. switch (ucontrol->value.integer.value[0]) {
  1376. case 3:
  1377. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1378. break;
  1379. case 2:
  1380. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1381. break;
  1382. case 1:
  1383. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1384. break;
  1385. case 0:
  1386. default:
  1387. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1388. break;
  1389. }
  1390. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1391. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1392. ucontrol->value.integer.value[0]);
  1393. return rc;
  1394. }
  1395. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1396. struct snd_ctl_elem_value *ucontrol)
  1397. {
  1398. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1399. usb_rx_cfg.channels);
  1400. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1401. return 0;
  1402. }
  1403. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1404. struct snd_ctl_elem_value *ucontrol)
  1405. {
  1406. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1407. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1408. return 1;
  1409. }
  1410. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1411. struct snd_ctl_elem_value *ucontrol)
  1412. {
  1413. int sample_rate_val;
  1414. switch (usb_rx_cfg.sample_rate) {
  1415. case SAMPLING_RATE_384KHZ:
  1416. sample_rate_val = 12;
  1417. break;
  1418. case SAMPLING_RATE_352P8KHZ:
  1419. sample_rate_val = 11;
  1420. break;
  1421. case SAMPLING_RATE_192KHZ:
  1422. sample_rate_val = 10;
  1423. break;
  1424. case SAMPLING_RATE_176P4KHZ:
  1425. sample_rate_val = 9;
  1426. break;
  1427. case SAMPLING_RATE_96KHZ:
  1428. sample_rate_val = 8;
  1429. break;
  1430. case SAMPLING_RATE_88P2KHZ:
  1431. sample_rate_val = 7;
  1432. break;
  1433. case SAMPLING_RATE_48KHZ:
  1434. sample_rate_val = 6;
  1435. break;
  1436. case SAMPLING_RATE_44P1KHZ:
  1437. sample_rate_val = 5;
  1438. break;
  1439. case SAMPLING_RATE_32KHZ:
  1440. sample_rate_val = 4;
  1441. break;
  1442. case SAMPLING_RATE_22P05KHZ:
  1443. sample_rate_val = 3;
  1444. break;
  1445. case SAMPLING_RATE_16KHZ:
  1446. sample_rate_val = 2;
  1447. break;
  1448. case SAMPLING_RATE_11P025KHZ:
  1449. sample_rate_val = 1;
  1450. break;
  1451. case SAMPLING_RATE_8KHZ:
  1452. default:
  1453. sample_rate_val = 0;
  1454. break;
  1455. }
  1456. ucontrol->value.integer.value[0] = sample_rate_val;
  1457. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1458. usb_rx_cfg.sample_rate);
  1459. return 0;
  1460. }
  1461. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1462. struct snd_ctl_elem_value *ucontrol)
  1463. {
  1464. switch (ucontrol->value.integer.value[0]) {
  1465. case 12:
  1466. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1467. break;
  1468. case 11:
  1469. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1470. break;
  1471. case 10:
  1472. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1473. break;
  1474. case 9:
  1475. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1476. break;
  1477. case 8:
  1478. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1479. break;
  1480. case 7:
  1481. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1482. break;
  1483. case 6:
  1484. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1485. break;
  1486. case 5:
  1487. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1488. break;
  1489. case 4:
  1490. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1491. break;
  1492. case 3:
  1493. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1494. break;
  1495. case 2:
  1496. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1497. break;
  1498. case 1:
  1499. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1500. break;
  1501. case 0:
  1502. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1503. break;
  1504. default:
  1505. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1506. break;
  1507. }
  1508. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1509. __func__, ucontrol->value.integer.value[0],
  1510. usb_rx_cfg.sample_rate);
  1511. return 0;
  1512. }
  1513. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1514. struct snd_ctl_elem_value *ucontrol)
  1515. {
  1516. switch (usb_rx_cfg.bit_format) {
  1517. case SNDRV_PCM_FORMAT_S32_LE:
  1518. ucontrol->value.integer.value[0] = 3;
  1519. break;
  1520. case SNDRV_PCM_FORMAT_S24_3LE:
  1521. ucontrol->value.integer.value[0] = 2;
  1522. break;
  1523. case SNDRV_PCM_FORMAT_S24_LE:
  1524. ucontrol->value.integer.value[0] = 1;
  1525. break;
  1526. case SNDRV_PCM_FORMAT_S16_LE:
  1527. default:
  1528. ucontrol->value.integer.value[0] = 0;
  1529. break;
  1530. }
  1531. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1532. __func__, usb_rx_cfg.bit_format,
  1533. ucontrol->value.integer.value[0]);
  1534. return 0;
  1535. }
  1536. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_value *ucontrol)
  1538. {
  1539. int rc = 0;
  1540. switch (ucontrol->value.integer.value[0]) {
  1541. case 3:
  1542. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1543. break;
  1544. case 2:
  1545. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1546. break;
  1547. case 1:
  1548. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1549. break;
  1550. case 0:
  1551. default:
  1552. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1553. break;
  1554. }
  1555. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1556. __func__, usb_rx_cfg.bit_format,
  1557. ucontrol->value.integer.value[0]);
  1558. return rc;
  1559. }
  1560. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1561. struct snd_ctl_elem_value *ucontrol)
  1562. {
  1563. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1564. usb_tx_cfg.channels);
  1565. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1566. return 0;
  1567. }
  1568. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1569. struct snd_ctl_elem_value *ucontrol)
  1570. {
  1571. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1572. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1573. return 1;
  1574. }
  1575. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1576. struct snd_ctl_elem_value *ucontrol)
  1577. {
  1578. int sample_rate_val;
  1579. switch (usb_tx_cfg.sample_rate) {
  1580. case SAMPLING_RATE_384KHZ:
  1581. sample_rate_val = 12;
  1582. break;
  1583. case SAMPLING_RATE_352P8KHZ:
  1584. sample_rate_val = 11;
  1585. break;
  1586. case SAMPLING_RATE_192KHZ:
  1587. sample_rate_val = 10;
  1588. break;
  1589. case SAMPLING_RATE_176P4KHZ:
  1590. sample_rate_val = 9;
  1591. break;
  1592. case SAMPLING_RATE_96KHZ:
  1593. sample_rate_val = 8;
  1594. break;
  1595. case SAMPLING_RATE_88P2KHZ:
  1596. sample_rate_val = 7;
  1597. break;
  1598. case SAMPLING_RATE_48KHZ:
  1599. sample_rate_val = 6;
  1600. break;
  1601. case SAMPLING_RATE_44P1KHZ:
  1602. sample_rate_val = 5;
  1603. break;
  1604. case SAMPLING_RATE_32KHZ:
  1605. sample_rate_val = 4;
  1606. break;
  1607. case SAMPLING_RATE_22P05KHZ:
  1608. sample_rate_val = 3;
  1609. break;
  1610. case SAMPLING_RATE_16KHZ:
  1611. sample_rate_val = 2;
  1612. break;
  1613. case SAMPLING_RATE_11P025KHZ:
  1614. sample_rate_val = 1;
  1615. break;
  1616. case SAMPLING_RATE_8KHZ:
  1617. sample_rate_val = 0;
  1618. break;
  1619. default:
  1620. sample_rate_val = 6;
  1621. break;
  1622. }
  1623. ucontrol->value.integer.value[0] = sample_rate_val;
  1624. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1625. usb_tx_cfg.sample_rate);
  1626. return 0;
  1627. }
  1628. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1629. struct snd_ctl_elem_value *ucontrol)
  1630. {
  1631. switch (ucontrol->value.integer.value[0]) {
  1632. case 12:
  1633. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1634. break;
  1635. case 11:
  1636. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1637. break;
  1638. case 10:
  1639. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1640. break;
  1641. case 9:
  1642. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1643. break;
  1644. case 8:
  1645. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1646. break;
  1647. case 7:
  1648. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1649. break;
  1650. case 6:
  1651. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1652. break;
  1653. case 5:
  1654. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1655. break;
  1656. case 4:
  1657. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1658. break;
  1659. case 3:
  1660. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1661. break;
  1662. case 2:
  1663. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1664. break;
  1665. case 1:
  1666. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1667. break;
  1668. case 0:
  1669. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1670. break;
  1671. default:
  1672. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1673. break;
  1674. }
  1675. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1676. __func__, ucontrol->value.integer.value[0],
  1677. usb_tx_cfg.sample_rate);
  1678. return 0;
  1679. }
  1680. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1681. struct snd_ctl_elem_value *ucontrol)
  1682. {
  1683. switch (usb_tx_cfg.bit_format) {
  1684. case SNDRV_PCM_FORMAT_S32_LE:
  1685. ucontrol->value.integer.value[0] = 3;
  1686. break;
  1687. case SNDRV_PCM_FORMAT_S24_3LE:
  1688. ucontrol->value.integer.value[0] = 2;
  1689. break;
  1690. case SNDRV_PCM_FORMAT_S24_LE:
  1691. ucontrol->value.integer.value[0] = 1;
  1692. break;
  1693. case SNDRV_PCM_FORMAT_S16_LE:
  1694. default:
  1695. ucontrol->value.integer.value[0] = 0;
  1696. break;
  1697. }
  1698. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1699. __func__, usb_tx_cfg.bit_format,
  1700. ucontrol->value.integer.value[0]);
  1701. return 0;
  1702. }
  1703. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1704. struct snd_ctl_elem_value *ucontrol)
  1705. {
  1706. int rc = 0;
  1707. switch (ucontrol->value.integer.value[0]) {
  1708. case 3:
  1709. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1710. break;
  1711. case 2:
  1712. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1713. break;
  1714. case 1:
  1715. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1716. break;
  1717. case 0:
  1718. default:
  1719. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1720. break;
  1721. }
  1722. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1723. __func__, usb_tx_cfg.bit_format,
  1724. ucontrol->value.integer.value[0]);
  1725. return rc;
  1726. }
  1727. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1728. struct snd_ctl_elem_value *ucontrol)
  1729. {
  1730. pr_debug("%s: proxy_rx channels = %d\n",
  1731. __func__, proxy_rx_cfg.channels);
  1732. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1733. return 0;
  1734. }
  1735. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1736. struct snd_ctl_elem_value *ucontrol)
  1737. {
  1738. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1739. pr_debug("%s: proxy_rx channels = %d\n",
  1740. __func__, proxy_rx_cfg.channels);
  1741. return 1;
  1742. }
  1743. static int tdm_get_sample_rate(int value)
  1744. {
  1745. int sample_rate = 0;
  1746. switch (value) {
  1747. case 0:
  1748. sample_rate = SAMPLING_RATE_8KHZ;
  1749. break;
  1750. case 1:
  1751. sample_rate = SAMPLING_RATE_16KHZ;
  1752. break;
  1753. case 2:
  1754. sample_rate = SAMPLING_RATE_32KHZ;
  1755. break;
  1756. case 3:
  1757. sample_rate = SAMPLING_RATE_48KHZ;
  1758. break;
  1759. case 4:
  1760. sample_rate = SAMPLING_RATE_176P4KHZ;
  1761. break;
  1762. case 5:
  1763. sample_rate = SAMPLING_RATE_352P8KHZ;
  1764. break;
  1765. default:
  1766. sample_rate = SAMPLING_RATE_48KHZ;
  1767. break;
  1768. }
  1769. return sample_rate;
  1770. }
  1771. static int aux_pcm_get_sample_rate(int value)
  1772. {
  1773. int sample_rate;
  1774. switch (value) {
  1775. case 1:
  1776. sample_rate = SAMPLING_RATE_16KHZ;
  1777. break;
  1778. case 0:
  1779. default:
  1780. sample_rate = SAMPLING_RATE_8KHZ;
  1781. break;
  1782. }
  1783. return sample_rate;
  1784. }
  1785. static int tdm_get_sample_rate_val(int sample_rate)
  1786. {
  1787. int sample_rate_val = 0;
  1788. switch (sample_rate) {
  1789. case SAMPLING_RATE_8KHZ:
  1790. sample_rate_val = 0;
  1791. break;
  1792. case SAMPLING_RATE_16KHZ:
  1793. sample_rate_val = 1;
  1794. break;
  1795. case SAMPLING_RATE_32KHZ:
  1796. sample_rate_val = 2;
  1797. break;
  1798. case SAMPLING_RATE_48KHZ:
  1799. sample_rate_val = 3;
  1800. break;
  1801. case SAMPLING_RATE_176P4KHZ:
  1802. sample_rate_val = 4;
  1803. break;
  1804. case SAMPLING_RATE_352P8KHZ:
  1805. sample_rate_val = 5;
  1806. break;
  1807. default:
  1808. sample_rate_val = 3;
  1809. break;
  1810. }
  1811. return sample_rate_val;
  1812. }
  1813. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1814. {
  1815. int sample_rate_val;
  1816. switch (sample_rate) {
  1817. case SAMPLING_RATE_16KHZ:
  1818. sample_rate_val = 1;
  1819. break;
  1820. case SAMPLING_RATE_8KHZ:
  1821. default:
  1822. sample_rate_val = 0;
  1823. break;
  1824. }
  1825. return sample_rate_val;
  1826. }
  1827. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1828. struct tdm_port *port)
  1829. {
  1830. if (port) {
  1831. if (strnstr(kcontrol->id.name, "PRI",
  1832. sizeof(kcontrol->id.name))) {
  1833. port->mode = TDM_PRI;
  1834. } else if (strnstr(kcontrol->id.name, "SEC",
  1835. sizeof(kcontrol->id.name))) {
  1836. port->mode = TDM_SEC;
  1837. } else if (strnstr(kcontrol->id.name, "TERT",
  1838. sizeof(kcontrol->id.name))) {
  1839. port->mode = TDM_TERT;
  1840. } else if (strnstr(kcontrol->id.name, "QUAT",
  1841. sizeof(kcontrol->id.name))) {
  1842. port->mode = TDM_QUAT;
  1843. } else if (strnstr(kcontrol->id.name, "QUIN",
  1844. sizeof(kcontrol->id.name))) {
  1845. port->mode = TDM_QUIN;
  1846. } else {
  1847. pr_err("%s: unsupported mode in: %s",
  1848. __func__, kcontrol->id.name);
  1849. return -EINVAL;
  1850. }
  1851. if (strnstr(kcontrol->id.name, "RX_0",
  1852. sizeof(kcontrol->id.name)) ||
  1853. strnstr(kcontrol->id.name, "TX_0",
  1854. sizeof(kcontrol->id.name))) {
  1855. port->channel = TDM_0;
  1856. } else if (strnstr(kcontrol->id.name, "RX_1",
  1857. sizeof(kcontrol->id.name)) ||
  1858. strnstr(kcontrol->id.name, "TX_1",
  1859. sizeof(kcontrol->id.name))) {
  1860. port->channel = TDM_1;
  1861. } else if (strnstr(kcontrol->id.name, "RX_2",
  1862. sizeof(kcontrol->id.name)) ||
  1863. strnstr(kcontrol->id.name, "TX_2",
  1864. sizeof(kcontrol->id.name))) {
  1865. port->channel = TDM_2;
  1866. } else if (strnstr(kcontrol->id.name, "RX_3",
  1867. sizeof(kcontrol->id.name)) ||
  1868. strnstr(kcontrol->id.name, "TX_3",
  1869. sizeof(kcontrol->id.name))) {
  1870. port->channel = TDM_3;
  1871. } else if (strnstr(kcontrol->id.name, "RX_4",
  1872. sizeof(kcontrol->id.name)) ||
  1873. strnstr(kcontrol->id.name, "TX_4",
  1874. sizeof(kcontrol->id.name))) {
  1875. port->channel = TDM_4;
  1876. } else if (strnstr(kcontrol->id.name, "RX_5",
  1877. sizeof(kcontrol->id.name)) ||
  1878. strnstr(kcontrol->id.name, "TX_5",
  1879. sizeof(kcontrol->id.name))) {
  1880. port->channel = TDM_5;
  1881. } else if (strnstr(kcontrol->id.name, "RX_6",
  1882. sizeof(kcontrol->id.name)) ||
  1883. strnstr(kcontrol->id.name, "TX_6",
  1884. sizeof(kcontrol->id.name))) {
  1885. port->channel = TDM_6;
  1886. } else if (strnstr(kcontrol->id.name, "RX_7",
  1887. sizeof(kcontrol->id.name)) ||
  1888. strnstr(kcontrol->id.name, "TX_7",
  1889. sizeof(kcontrol->id.name))) {
  1890. port->channel = TDM_7;
  1891. } else {
  1892. pr_err("%s: unsupported channel in: %s",
  1893. __func__, kcontrol->id.name);
  1894. return -EINVAL;
  1895. }
  1896. } else
  1897. return -EINVAL;
  1898. return 0;
  1899. }
  1900. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1901. struct snd_ctl_elem_value *ucontrol)
  1902. {
  1903. struct tdm_port port;
  1904. int ret = tdm_get_port_idx(kcontrol, &port);
  1905. if (ret) {
  1906. pr_err("%s: unsupported control: %s",
  1907. __func__, kcontrol->id.name);
  1908. } else {
  1909. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1910. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1911. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1912. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1913. ucontrol->value.enumerated.item[0]);
  1914. }
  1915. return ret;
  1916. }
  1917. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1918. struct snd_ctl_elem_value *ucontrol)
  1919. {
  1920. struct tdm_port port;
  1921. int ret = tdm_get_port_idx(kcontrol, &port);
  1922. if (ret) {
  1923. pr_err("%s: unsupported control: %s",
  1924. __func__, kcontrol->id.name);
  1925. } else {
  1926. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1927. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1928. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1929. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1930. ucontrol->value.enumerated.item[0]);
  1931. }
  1932. return ret;
  1933. }
  1934. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1935. struct snd_ctl_elem_value *ucontrol)
  1936. {
  1937. struct tdm_port port;
  1938. int ret = tdm_get_port_idx(kcontrol, &port);
  1939. if (ret) {
  1940. pr_err("%s: unsupported control: %s",
  1941. __func__, kcontrol->id.name);
  1942. } else {
  1943. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1944. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1945. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1946. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1947. ucontrol->value.enumerated.item[0]);
  1948. }
  1949. return ret;
  1950. }
  1951. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1952. struct snd_ctl_elem_value *ucontrol)
  1953. {
  1954. struct tdm_port port;
  1955. int ret = tdm_get_port_idx(kcontrol, &port);
  1956. if (ret) {
  1957. pr_err("%s: unsupported control: %s",
  1958. __func__, kcontrol->id.name);
  1959. } else {
  1960. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1961. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1962. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1963. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1964. ucontrol->value.enumerated.item[0]);
  1965. }
  1966. return ret;
  1967. }
  1968. static int tdm_get_format(int value)
  1969. {
  1970. int format = 0;
  1971. switch (value) {
  1972. case 0:
  1973. format = SNDRV_PCM_FORMAT_S16_LE;
  1974. break;
  1975. case 1:
  1976. format = SNDRV_PCM_FORMAT_S24_LE;
  1977. break;
  1978. case 2:
  1979. format = SNDRV_PCM_FORMAT_S32_LE;
  1980. break;
  1981. default:
  1982. format = SNDRV_PCM_FORMAT_S16_LE;
  1983. break;
  1984. }
  1985. return format;
  1986. }
  1987. static int tdm_get_format_val(int format)
  1988. {
  1989. int value = 0;
  1990. switch (format) {
  1991. case SNDRV_PCM_FORMAT_S16_LE:
  1992. value = 0;
  1993. break;
  1994. case SNDRV_PCM_FORMAT_S24_LE:
  1995. value = 1;
  1996. break;
  1997. case SNDRV_PCM_FORMAT_S32_LE:
  1998. value = 2;
  1999. break;
  2000. default:
  2001. value = 0;
  2002. break;
  2003. }
  2004. return value;
  2005. }
  2006. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2007. struct snd_ctl_elem_value *ucontrol)
  2008. {
  2009. struct tdm_port port;
  2010. int ret = tdm_get_port_idx(kcontrol, &port);
  2011. if (ret) {
  2012. pr_err("%s: unsupported control: %s",
  2013. __func__, kcontrol->id.name);
  2014. } else {
  2015. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2016. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2017. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2018. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2019. ucontrol->value.enumerated.item[0]);
  2020. }
  2021. return ret;
  2022. }
  2023. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2024. struct snd_ctl_elem_value *ucontrol)
  2025. {
  2026. struct tdm_port port;
  2027. int ret = tdm_get_port_idx(kcontrol, &port);
  2028. if (ret) {
  2029. pr_err("%s: unsupported control: %s",
  2030. __func__, kcontrol->id.name);
  2031. } else {
  2032. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2033. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2034. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2035. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2036. ucontrol->value.enumerated.item[0]);
  2037. }
  2038. return ret;
  2039. }
  2040. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2041. struct snd_ctl_elem_value *ucontrol)
  2042. {
  2043. struct tdm_port port;
  2044. int ret = tdm_get_port_idx(kcontrol, &port);
  2045. if (ret) {
  2046. pr_err("%s: unsupported control: %s",
  2047. __func__, kcontrol->id.name);
  2048. } else {
  2049. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2050. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2051. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2052. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2053. ucontrol->value.enumerated.item[0]);
  2054. }
  2055. return ret;
  2056. }
  2057. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2058. struct snd_ctl_elem_value *ucontrol)
  2059. {
  2060. struct tdm_port port;
  2061. int ret = tdm_get_port_idx(kcontrol, &port);
  2062. if (ret) {
  2063. pr_err("%s: unsupported control: %s",
  2064. __func__, kcontrol->id.name);
  2065. } else {
  2066. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2067. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2068. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2069. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2070. ucontrol->value.enumerated.item[0]);
  2071. }
  2072. return ret;
  2073. }
  2074. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2075. struct snd_ctl_elem_value *ucontrol)
  2076. {
  2077. struct tdm_port port;
  2078. int ret = tdm_get_port_idx(kcontrol, &port);
  2079. if (ret) {
  2080. pr_err("%s: unsupported control: %s",
  2081. __func__, kcontrol->id.name);
  2082. } else {
  2083. ucontrol->value.enumerated.item[0] =
  2084. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2085. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2086. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2087. ucontrol->value.enumerated.item[0]);
  2088. }
  2089. return ret;
  2090. }
  2091. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2092. struct snd_ctl_elem_value *ucontrol)
  2093. {
  2094. struct tdm_port port;
  2095. int ret = tdm_get_port_idx(kcontrol, &port);
  2096. if (ret) {
  2097. pr_err("%s: unsupported control: %s",
  2098. __func__, kcontrol->id.name);
  2099. } else {
  2100. tdm_rx_cfg[port.mode][port.channel].channels =
  2101. ucontrol->value.enumerated.item[0] + 1;
  2102. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2103. tdm_rx_cfg[port.mode][port.channel].channels,
  2104. ucontrol->value.enumerated.item[0] + 1);
  2105. }
  2106. return ret;
  2107. }
  2108. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2109. struct snd_ctl_elem_value *ucontrol)
  2110. {
  2111. struct tdm_port port;
  2112. int ret = tdm_get_port_idx(kcontrol, &port);
  2113. if (ret) {
  2114. pr_err("%s: unsupported control: %s",
  2115. __func__, kcontrol->id.name);
  2116. } else {
  2117. ucontrol->value.enumerated.item[0] =
  2118. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2119. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2120. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2121. ucontrol->value.enumerated.item[0]);
  2122. }
  2123. return ret;
  2124. }
  2125. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2126. struct snd_ctl_elem_value *ucontrol)
  2127. {
  2128. struct tdm_port port;
  2129. int ret = tdm_get_port_idx(kcontrol, &port);
  2130. if (ret) {
  2131. pr_err("%s: unsupported control: %s",
  2132. __func__, kcontrol->id.name);
  2133. } else {
  2134. tdm_tx_cfg[port.mode][port.channel].channels =
  2135. ucontrol->value.enumerated.item[0] + 1;
  2136. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2137. tdm_tx_cfg[port.mode][port.channel].channels,
  2138. ucontrol->value.enumerated.item[0] + 1);
  2139. }
  2140. return ret;
  2141. }
  2142. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2143. {
  2144. int idx;
  2145. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2146. sizeof("PRIM_AUX_PCM")))
  2147. idx = PRIM_AUX_PCM;
  2148. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2149. sizeof("SEC_AUX_PCM")))
  2150. idx = SEC_AUX_PCM;
  2151. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2152. sizeof("TERT_AUX_PCM")))
  2153. idx = TERT_AUX_PCM;
  2154. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2155. sizeof("QUAT_AUX_PCM")))
  2156. idx = QUAT_AUX_PCM;
  2157. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2158. sizeof("QUIN_AUX_PCM")))
  2159. idx = QUIN_AUX_PCM;
  2160. else {
  2161. pr_err("%s: unsupported port: %s",
  2162. __func__, kcontrol->id.name);
  2163. idx = -EINVAL;
  2164. }
  2165. return idx;
  2166. }
  2167. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2168. struct snd_ctl_elem_value *ucontrol)
  2169. {
  2170. int idx = aux_pcm_get_port_idx(kcontrol);
  2171. if (idx < 0)
  2172. return idx;
  2173. aux_pcm_rx_cfg[idx].sample_rate =
  2174. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2175. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2176. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2177. ucontrol->value.enumerated.item[0]);
  2178. return 0;
  2179. }
  2180. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2181. struct snd_ctl_elem_value *ucontrol)
  2182. {
  2183. int idx = aux_pcm_get_port_idx(kcontrol);
  2184. if (idx < 0)
  2185. return idx;
  2186. ucontrol->value.enumerated.item[0] =
  2187. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2188. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2189. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2190. ucontrol->value.enumerated.item[0]);
  2191. return 0;
  2192. }
  2193. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2194. struct snd_ctl_elem_value *ucontrol)
  2195. {
  2196. int idx = aux_pcm_get_port_idx(kcontrol);
  2197. if (idx < 0)
  2198. return idx;
  2199. aux_pcm_tx_cfg[idx].sample_rate =
  2200. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2201. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2202. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2203. ucontrol->value.enumerated.item[0]);
  2204. return 0;
  2205. }
  2206. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2207. struct snd_ctl_elem_value *ucontrol)
  2208. {
  2209. int idx = aux_pcm_get_port_idx(kcontrol);
  2210. if (idx < 0)
  2211. return idx;
  2212. ucontrol->value.enumerated.item[0] =
  2213. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2214. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2215. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2216. ucontrol->value.enumerated.item[0]);
  2217. return 0;
  2218. }
  2219. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2220. {
  2221. int idx;
  2222. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2223. sizeof("PRIM_MI2S_RX")))
  2224. idx = PRIM_MI2S;
  2225. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2226. sizeof("SEC_MI2S_RX")))
  2227. idx = SEC_MI2S;
  2228. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2229. sizeof("TERT_MI2S_RX")))
  2230. idx = TERT_MI2S;
  2231. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2232. sizeof("QUAT_MI2S_RX")))
  2233. idx = QUAT_MI2S;
  2234. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2235. sizeof("QUIN_MI2S_RX")))
  2236. idx = QUIN_MI2S;
  2237. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2238. sizeof("PRIM_MI2S_TX")))
  2239. idx = PRIM_MI2S;
  2240. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2241. sizeof("SEC_MI2S_TX")))
  2242. idx = SEC_MI2S;
  2243. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2244. sizeof("TERT_MI2S_TX")))
  2245. idx = TERT_MI2S;
  2246. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2247. sizeof("QUAT_MI2S_TX")))
  2248. idx = QUAT_MI2S;
  2249. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2250. sizeof("QUIN_MI2S_TX")))
  2251. idx = QUIN_MI2S;
  2252. else {
  2253. pr_err("%s: unsupported channel: %s",
  2254. __func__, kcontrol->id.name);
  2255. idx = -EINVAL;
  2256. }
  2257. return idx;
  2258. }
  2259. static int mi2s_get_sample_rate_val(int sample_rate)
  2260. {
  2261. int sample_rate_val;
  2262. switch (sample_rate) {
  2263. case SAMPLING_RATE_8KHZ:
  2264. sample_rate_val = 0;
  2265. break;
  2266. case SAMPLING_RATE_11P025KHZ:
  2267. sample_rate_val = 1;
  2268. break;
  2269. case SAMPLING_RATE_16KHZ:
  2270. sample_rate_val = 2;
  2271. break;
  2272. case SAMPLING_RATE_22P05KHZ:
  2273. sample_rate_val = 3;
  2274. break;
  2275. case SAMPLING_RATE_32KHZ:
  2276. sample_rate_val = 4;
  2277. break;
  2278. case SAMPLING_RATE_44P1KHZ:
  2279. sample_rate_val = 5;
  2280. break;
  2281. case SAMPLING_RATE_48KHZ:
  2282. sample_rate_val = 6;
  2283. break;
  2284. case SAMPLING_RATE_96KHZ:
  2285. sample_rate_val = 7;
  2286. break;
  2287. case SAMPLING_RATE_192KHZ:
  2288. sample_rate_val = 8;
  2289. break;
  2290. default:
  2291. sample_rate_val = 6;
  2292. break;
  2293. }
  2294. return sample_rate_val;
  2295. }
  2296. static int mi2s_get_sample_rate(int value)
  2297. {
  2298. int sample_rate;
  2299. switch (value) {
  2300. case 0:
  2301. sample_rate = SAMPLING_RATE_8KHZ;
  2302. break;
  2303. case 1:
  2304. sample_rate = SAMPLING_RATE_11P025KHZ;
  2305. break;
  2306. case 2:
  2307. sample_rate = SAMPLING_RATE_16KHZ;
  2308. break;
  2309. case 3:
  2310. sample_rate = SAMPLING_RATE_22P05KHZ;
  2311. break;
  2312. case 4:
  2313. sample_rate = SAMPLING_RATE_32KHZ;
  2314. break;
  2315. case 5:
  2316. sample_rate = SAMPLING_RATE_44P1KHZ;
  2317. break;
  2318. case 6:
  2319. sample_rate = SAMPLING_RATE_48KHZ;
  2320. break;
  2321. case 7:
  2322. sample_rate = SAMPLING_RATE_96KHZ;
  2323. break;
  2324. case 8:
  2325. sample_rate = SAMPLING_RATE_192KHZ;
  2326. break;
  2327. default:
  2328. sample_rate = SAMPLING_RATE_48KHZ;
  2329. break;
  2330. }
  2331. return sample_rate;
  2332. }
  2333. static int mi2s_auxpcm_get_format(int value)
  2334. {
  2335. int format;
  2336. switch (value) {
  2337. case 0:
  2338. format = SNDRV_PCM_FORMAT_S16_LE;
  2339. break;
  2340. case 1:
  2341. format = SNDRV_PCM_FORMAT_S24_LE;
  2342. break;
  2343. case 2:
  2344. format = SNDRV_PCM_FORMAT_S24_3LE;
  2345. break;
  2346. case 3:
  2347. format = SNDRV_PCM_FORMAT_S32_LE;
  2348. break;
  2349. default:
  2350. format = SNDRV_PCM_FORMAT_S16_LE;
  2351. break;
  2352. }
  2353. return format;
  2354. }
  2355. static int mi2s_auxpcm_get_format_value(int format)
  2356. {
  2357. int value;
  2358. switch (format) {
  2359. case SNDRV_PCM_FORMAT_S16_LE:
  2360. value = 0;
  2361. break;
  2362. case SNDRV_PCM_FORMAT_S24_LE:
  2363. value = 1;
  2364. break;
  2365. case SNDRV_PCM_FORMAT_S24_3LE:
  2366. value = 2;
  2367. break;
  2368. case SNDRV_PCM_FORMAT_S32_LE:
  2369. value = 3;
  2370. break;
  2371. default:
  2372. value = 0;
  2373. break;
  2374. }
  2375. return value;
  2376. }
  2377. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2378. struct snd_ctl_elem_value *ucontrol)
  2379. {
  2380. int idx = mi2s_get_port_idx(kcontrol);
  2381. if (idx < 0)
  2382. return idx;
  2383. mi2s_rx_cfg[idx].sample_rate =
  2384. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2385. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2386. idx, mi2s_rx_cfg[idx].sample_rate,
  2387. ucontrol->value.enumerated.item[0]);
  2388. return 0;
  2389. }
  2390. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2391. struct snd_ctl_elem_value *ucontrol)
  2392. {
  2393. int idx = mi2s_get_port_idx(kcontrol);
  2394. if (idx < 0)
  2395. return idx;
  2396. ucontrol->value.enumerated.item[0] =
  2397. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2398. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2399. idx, mi2s_rx_cfg[idx].sample_rate,
  2400. ucontrol->value.enumerated.item[0]);
  2401. return 0;
  2402. }
  2403. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2404. struct snd_ctl_elem_value *ucontrol)
  2405. {
  2406. int idx = mi2s_get_port_idx(kcontrol);
  2407. if (idx < 0)
  2408. return idx;
  2409. mi2s_tx_cfg[idx].sample_rate =
  2410. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2411. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2412. idx, mi2s_tx_cfg[idx].sample_rate,
  2413. ucontrol->value.enumerated.item[0]);
  2414. return 0;
  2415. }
  2416. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2417. struct snd_ctl_elem_value *ucontrol)
  2418. {
  2419. int idx = mi2s_get_port_idx(kcontrol);
  2420. if (idx < 0)
  2421. return idx;
  2422. ucontrol->value.enumerated.item[0] =
  2423. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2424. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2425. idx, mi2s_tx_cfg[idx].sample_rate,
  2426. ucontrol->value.enumerated.item[0]);
  2427. return 0;
  2428. }
  2429. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2430. struct snd_ctl_elem_value *ucontrol)
  2431. {
  2432. int idx = mi2s_get_port_idx(kcontrol);
  2433. if (idx < 0)
  2434. return idx;
  2435. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2436. idx, mi2s_rx_cfg[idx].channels);
  2437. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2438. return 0;
  2439. }
  2440. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2441. struct snd_ctl_elem_value *ucontrol)
  2442. {
  2443. int idx = mi2s_get_port_idx(kcontrol);
  2444. if (idx < 0)
  2445. return idx;
  2446. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2447. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2448. idx, mi2s_rx_cfg[idx].channels);
  2449. return 1;
  2450. }
  2451. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2452. struct snd_ctl_elem_value *ucontrol)
  2453. {
  2454. int idx = mi2s_get_port_idx(kcontrol);
  2455. if (idx < 0)
  2456. return idx;
  2457. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2458. idx, mi2s_tx_cfg[idx].channels);
  2459. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2460. return 0;
  2461. }
  2462. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2463. struct snd_ctl_elem_value *ucontrol)
  2464. {
  2465. int idx = mi2s_get_port_idx(kcontrol);
  2466. if (idx < 0)
  2467. return idx;
  2468. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2469. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2470. idx, mi2s_tx_cfg[idx].channels);
  2471. return 1;
  2472. }
  2473. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2474. struct snd_ctl_elem_value *ucontrol)
  2475. {
  2476. int idx = mi2s_get_port_idx(kcontrol);
  2477. if (idx < 0)
  2478. return idx;
  2479. ucontrol->value.enumerated.item[0] =
  2480. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2481. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2482. idx, mi2s_rx_cfg[idx].bit_format,
  2483. ucontrol->value.enumerated.item[0]);
  2484. return 0;
  2485. }
  2486. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2487. struct snd_ctl_elem_value *ucontrol)
  2488. {
  2489. int idx = mi2s_get_port_idx(kcontrol);
  2490. if (idx < 0)
  2491. return idx;
  2492. mi2s_rx_cfg[idx].bit_format =
  2493. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2494. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2495. idx, mi2s_rx_cfg[idx].bit_format,
  2496. ucontrol->value.enumerated.item[0]);
  2497. return 0;
  2498. }
  2499. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2500. struct snd_ctl_elem_value *ucontrol)
  2501. {
  2502. int idx = mi2s_get_port_idx(kcontrol);
  2503. if (idx < 0)
  2504. return idx;
  2505. ucontrol->value.enumerated.item[0] =
  2506. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2507. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2508. idx, mi2s_tx_cfg[idx].bit_format,
  2509. ucontrol->value.enumerated.item[0]);
  2510. return 0;
  2511. }
  2512. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2513. struct snd_ctl_elem_value *ucontrol)
  2514. {
  2515. int idx = mi2s_get_port_idx(kcontrol);
  2516. if (idx < 0)
  2517. return idx;
  2518. mi2s_tx_cfg[idx].bit_format =
  2519. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2520. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2521. idx, mi2s_tx_cfg[idx].bit_format,
  2522. ucontrol->value.enumerated.item[0]);
  2523. return 0;
  2524. }
  2525. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2526. struct snd_ctl_elem_value *ucontrol)
  2527. {
  2528. int idx = aux_pcm_get_port_idx(kcontrol);
  2529. if (idx < 0)
  2530. return idx;
  2531. ucontrol->value.enumerated.item[0] =
  2532. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2533. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2534. idx, aux_pcm_rx_cfg[idx].bit_format,
  2535. ucontrol->value.enumerated.item[0]);
  2536. return 0;
  2537. }
  2538. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2539. struct snd_ctl_elem_value *ucontrol)
  2540. {
  2541. int idx = aux_pcm_get_port_idx(kcontrol);
  2542. if (idx < 0)
  2543. return idx;
  2544. aux_pcm_rx_cfg[idx].bit_format =
  2545. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2546. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2547. idx, aux_pcm_rx_cfg[idx].bit_format,
  2548. ucontrol->value.enumerated.item[0]);
  2549. return 0;
  2550. }
  2551. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2552. struct snd_ctl_elem_value *ucontrol)
  2553. {
  2554. int idx = aux_pcm_get_port_idx(kcontrol);
  2555. if (idx < 0)
  2556. return idx;
  2557. ucontrol->value.enumerated.item[0] =
  2558. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2559. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2560. idx, aux_pcm_tx_cfg[idx].bit_format,
  2561. ucontrol->value.enumerated.item[0]);
  2562. return 0;
  2563. }
  2564. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2565. struct snd_ctl_elem_value *ucontrol)
  2566. {
  2567. int idx = aux_pcm_get_port_idx(kcontrol);
  2568. if (idx < 0)
  2569. return idx;
  2570. aux_pcm_tx_cfg[idx].bit_format =
  2571. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2572. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2573. idx, aux_pcm_tx_cfg[idx].bit_format,
  2574. ucontrol->value.enumerated.item[0]);
  2575. return 0;
  2576. }
  2577. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2578. {
  2579. int idx;
  2580. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2581. sizeof("PRIM_SPDIF_RX")))
  2582. idx = PRIM_SPDIF_RX;
  2583. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2584. sizeof("SEC_SPDIF_RX")))
  2585. idx = SEC_SPDIF_RX;
  2586. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2587. sizeof("PRIM_SPDIF_TX")))
  2588. idx = PRIM_SPDIF_TX;
  2589. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2590. sizeof("SEC_SPDIF_TX")))
  2591. idx = SEC_SPDIF_TX;
  2592. else {
  2593. pr_err("%s: unsupported channel: %s",
  2594. __func__, kcontrol->id.name);
  2595. idx = -EINVAL;
  2596. }
  2597. return idx;
  2598. }
  2599. static int spdif_get_sample_rate_val(int sample_rate)
  2600. {
  2601. int sample_rate_val;
  2602. switch (sample_rate) {
  2603. case SAMPLING_RATE_32KHZ:
  2604. sample_rate_val = 0;
  2605. break;
  2606. case SAMPLING_RATE_44P1KHZ:
  2607. sample_rate_val = 1;
  2608. break;
  2609. case SAMPLING_RATE_48KHZ:
  2610. sample_rate_val = 2;
  2611. break;
  2612. case SAMPLING_RATE_88P2KHZ:
  2613. sample_rate_val = 3;
  2614. break;
  2615. case SAMPLING_RATE_96KHZ:
  2616. sample_rate_val = 4;
  2617. break;
  2618. case SAMPLING_RATE_176P4KHZ:
  2619. sample_rate_val = 5;
  2620. break;
  2621. case SAMPLING_RATE_192KHZ:
  2622. sample_rate_val = 6;
  2623. break;
  2624. default:
  2625. sample_rate_val = 2;
  2626. break;
  2627. }
  2628. return sample_rate_val;
  2629. }
  2630. static int spdif_get_sample_rate(int value)
  2631. {
  2632. int sample_rate;
  2633. switch (value) {
  2634. case 0:
  2635. sample_rate = SAMPLING_RATE_32KHZ;
  2636. break;
  2637. case 1:
  2638. sample_rate = SAMPLING_RATE_44P1KHZ;
  2639. break;
  2640. case 2:
  2641. sample_rate = SAMPLING_RATE_48KHZ;
  2642. break;
  2643. case 3:
  2644. sample_rate = SAMPLING_RATE_88P2KHZ;
  2645. break;
  2646. case 4:
  2647. sample_rate = SAMPLING_RATE_96KHZ;
  2648. break;
  2649. case 5:
  2650. sample_rate = SAMPLING_RATE_176P4KHZ;
  2651. break;
  2652. case 6:
  2653. sample_rate = SAMPLING_RATE_192KHZ;
  2654. break;
  2655. default:
  2656. sample_rate = SAMPLING_RATE_48KHZ;
  2657. break;
  2658. }
  2659. return sample_rate;
  2660. }
  2661. static int spdif_get_format(int value)
  2662. {
  2663. int format;
  2664. switch (value) {
  2665. case 0:
  2666. format = SNDRV_PCM_FORMAT_S16_LE;
  2667. break;
  2668. case 1:
  2669. format = SNDRV_PCM_FORMAT_S24_LE;
  2670. break;
  2671. default:
  2672. format = SNDRV_PCM_FORMAT_S16_LE;
  2673. break;
  2674. }
  2675. return format;
  2676. }
  2677. static int spdif_get_format_value(int format)
  2678. {
  2679. int value;
  2680. switch (format) {
  2681. case SNDRV_PCM_FORMAT_S16_LE:
  2682. value = 0;
  2683. break;
  2684. case SNDRV_PCM_FORMAT_S24_LE:
  2685. value = 1;
  2686. break;
  2687. default:
  2688. value = 0;
  2689. break;
  2690. }
  2691. return value;
  2692. }
  2693. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2694. struct snd_ctl_elem_value *ucontrol)
  2695. {
  2696. int idx = spdif_get_port_idx(kcontrol);
  2697. if (idx < 0)
  2698. return idx;
  2699. spdif_rx_cfg[idx].sample_rate =
  2700. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2701. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2702. idx, spdif_rx_cfg[idx].sample_rate,
  2703. ucontrol->value.enumerated.item[0]);
  2704. return 0;
  2705. }
  2706. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2707. struct snd_ctl_elem_value *ucontrol)
  2708. {
  2709. int idx = spdif_get_port_idx(kcontrol);
  2710. if (idx < 0)
  2711. return idx;
  2712. ucontrol->value.enumerated.item[0] =
  2713. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2714. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2715. idx, spdif_rx_cfg[idx].sample_rate,
  2716. ucontrol->value.enumerated.item[0]);
  2717. return 0;
  2718. }
  2719. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2720. struct snd_ctl_elem_value *ucontrol)
  2721. {
  2722. int idx = spdif_get_port_idx(kcontrol);
  2723. if (idx < 0)
  2724. return idx;
  2725. spdif_tx_cfg[idx].sample_rate =
  2726. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2727. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2728. idx, spdif_tx_cfg[idx].sample_rate,
  2729. ucontrol->value.enumerated.item[0]);
  2730. return 0;
  2731. }
  2732. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2733. struct snd_ctl_elem_value *ucontrol)
  2734. {
  2735. int idx = spdif_get_port_idx(kcontrol);
  2736. if (idx < 0)
  2737. return idx;
  2738. ucontrol->value.enumerated.item[0] =
  2739. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2740. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2741. idx, spdif_tx_cfg[idx].sample_rate,
  2742. ucontrol->value.enumerated.item[0]);
  2743. return 0;
  2744. }
  2745. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2746. struct snd_ctl_elem_value *ucontrol)
  2747. {
  2748. int idx = spdif_get_port_idx(kcontrol);
  2749. if (idx < 0)
  2750. return idx;
  2751. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2752. idx, spdif_rx_cfg[idx].channels);
  2753. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2754. return 0;
  2755. }
  2756. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2757. struct snd_ctl_elem_value *ucontrol)
  2758. {
  2759. int idx = spdif_get_port_idx(kcontrol);
  2760. if (idx < 0)
  2761. return idx;
  2762. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2763. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2764. idx, spdif_rx_cfg[idx].channels);
  2765. return 1;
  2766. }
  2767. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2768. struct snd_ctl_elem_value *ucontrol)
  2769. {
  2770. int idx = spdif_get_port_idx(kcontrol);
  2771. if (idx < 0)
  2772. return idx;
  2773. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2774. idx, spdif_tx_cfg[idx].channels);
  2775. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2776. return 0;
  2777. }
  2778. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2779. struct snd_ctl_elem_value *ucontrol)
  2780. {
  2781. int idx = spdif_get_port_idx(kcontrol);
  2782. if (idx < 0)
  2783. return idx;
  2784. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2785. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2786. idx, spdif_tx_cfg[idx].channels);
  2787. return 1;
  2788. }
  2789. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2790. struct snd_ctl_elem_value *ucontrol)
  2791. {
  2792. int idx = spdif_get_port_idx(kcontrol);
  2793. if (idx < 0)
  2794. return idx;
  2795. ucontrol->value.enumerated.item[0] =
  2796. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2797. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2798. idx, spdif_rx_cfg[idx].bit_format,
  2799. ucontrol->value.enumerated.item[0]);
  2800. return 0;
  2801. }
  2802. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2803. struct snd_ctl_elem_value *ucontrol)
  2804. {
  2805. int idx = spdif_get_port_idx(kcontrol);
  2806. if (idx < 0)
  2807. return idx;
  2808. spdif_rx_cfg[idx].bit_format =
  2809. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2810. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2811. idx, spdif_rx_cfg[idx].bit_format,
  2812. ucontrol->value.enumerated.item[0]);
  2813. return 0;
  2814. }
  2815. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2816. struct snd_ctl_elem_value *ucontrol)
  2817. {
  2818. int idx = spdif_get_port_idx(kcontrol);
  2819. if (idx < 0)
  2820. return idx;
  2821. ucontrol->value.enumerated.item[0] =
  2822. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2823. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2824. idx, spdif_tx_cfg[idx].bit_format,
  2825. ucontrol->value.enumerated.item[0]);
  2826. return 0;
  2827. }
  2828. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2829. struct snd_ctl_elem_value *ucontrol)
  2830. {
  2831. int idx = spdif_get_port_idx(kcontrol);
  2832. if (idx < 0)
  2833. return idx;
  2834. spdif_tx_cfg[idx].bit_format =
  2835. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2836. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2837. idx, spdif_tx_cfg[idx].bit_format,
  2838. ucontrol->value.enumerated.item[0]);
  2839. return 0;
  2840. }
  2841. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2842. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2843. slim_rx_ch_get, slim_rx_ch_put),
  2844. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2845. slim_rx_ch_get, slim_rx_ch_put),
  2846. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2847. slim_tx_ch_get, slim_tx_ch_put),
  2848. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2849. slim_tx_ch_get, slim_tx_ch_put),
  2850. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2851. slim_rx_ch_get, slim_rx_ch_put),
  2852. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2853. slim_rx_ch_get, slim_rx_ch_put),
  2854. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2855. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2856. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2857. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2858. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2859. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2860. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2861. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2862. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2863. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2864. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2865. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2866. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2867. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2868. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2869. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2870. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2871. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2872. };
  2873. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2874. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2875. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2876. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2877. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2878. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2879. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2880. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2881. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2882. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2883. va_cdc_dma_tx_0_sample_rate,
  2884. cdc_dma_tx_sample_rate_get,
  2885. cdc_dma_tx_sample_rate_put),
  2886. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2887. va_cdc_dma_tx_1_sample_rate,
  2888. cdc_dma_tx_sample_rate_get,
  2889. cdc_dma_tx_sample_rate_put),
  2890. };
  2891. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2892. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2893. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2894. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2895. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2896. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2897. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2898. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2899. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2900. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2901. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2902. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2903. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2904. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2905. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2906. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2907. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2908. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2909. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2910. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2911. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2912. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2913. wsa_cdc_dma_rx_0_sample_rate,
  2914. cdc_dma_rx_sample_rate_get,
  2915. cdc_dma_rx_sample_rate_put),
  2916. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2917. wsa_cdc_dma_rx_1_sample_rate,
  2918. cdc_dma_rx_sample_rate_get,
  2919. cdc_dma_rx_sample_rate_put),
  2920. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2921. wsa_cdc_dma_tx_0_sample_rate,
  2922. cdc_dma_tx_sample_rate_get,
  2923. cdc_dma_tx_sample_rate_put),
  2924. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2925. wsa_cdc_dma_tx_1_sample_rate,
  2926. cdc_dma_tx_sample_rate_get,
  2927. cdc_dma_tx_sample_rate_put),
  2928. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2929. wsa_cdc_dma_tx_2_sample_rate,
  2930. cdc_dma_tx_sample_rate_get,
  2931. cdc_dma_tx_sample_rate_put),
  2932. };
  2933. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2934. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2935. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2936. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2937. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2938. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2939. proxy_rx_ch_get, proxy_rx_ch_put),
  2940. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2941. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2942. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2943. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2944. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2945. msm_bt_sample_rate_get,
  2946. msm_bt_sample_rate_put),
  2947. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2948. usb_audio_rx_sample_rate_get,
  2949. usb_audio_rx_sample_rate_put),
  2950. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2951. usb_audio_tx_sample_rate_get,
  2952. usb_audio_tx_sample_rate_put),
  2953. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2954. tdm_rx_sample_rate_get,
  2955. tdm_rx_sample_rate_put),
  2956. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2957. tdm_tx_sample_rate_get,
  2958. tdm_tx_sample_rate_put),
  2959. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2960. tdm_rx_format_get,
  2961. tdm_rx_format_put),
  2962. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2963. tdm_tx_format_get,
  2964. tdm_tx_format_put),
  2965. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2966. tdm_rx_ch_get,
  2967. tdm_rx_ch_put),
  2968. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2969. tdm_tx_ch_get,
  2970. tdm_tx_ch_put),
  2971. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2972. tdm_rx_sample_rate_get,
  2973. tdm_rx_sample_rate_put),
  2974. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2975. tdm_tx_sample_rate_get,
  2976. tdm_tx_sample_rate_put),
  2977. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2978. tdm_rx_format_get,
  2979. tdm_rx_format_put),
  2980. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2981. tdm_tx_format_get,
  2982. tdm_tx_format_put),
  2983. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2984. tdm_rx_ch_get,
  2985. tdm_rx_ch_put),
  2986. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2987. tdm_tx_ch_get,
  2988. tdm_tx_ch_put),
  2989. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2990. tdm_rx_sample_rate_get,
  2991. tdm_rx_sample_rate_put),
  2992. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2993. tdm_tx_sample_rate_get,
  2994. tdm_tx_sample_rate_put),
  2995. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2996. tdm_rx_format_get,
  2997. tdm_rx_format_put),
  2998. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2999. tdm_tx_format_get,
  3000. tdm_tx_format_put),
  3001. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3002. tdm_rx_ch_get,
  3003. tdm_rx_ch_put),
  3004. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3005. tdm_tx_ch_get,
  3006. tdm_tx_ch_put),
  3007. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3008. tdm_rx_sample_rate_get,
  3009. tdm_rx_sample_rate_put),
  3010. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3011. tdm_tx_sample_rate_get,
  3012. tdm_tx_sample_rate_put),
  3013. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3014. tdm_rx_format_get,
  3015. tdm_rx_format_put),
  3016. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3017. tdm_tx_format_get,
  3018. tdm_tx_format_put),
  3019. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3020. tdm_rx_ch_get,
  3021. tdm_rx_ch_put),
  3022. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3023. tdm_tx_ch_get,
  3024. tdm_tx_ch_put),
  3025. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3026. tdm_rx_sample_rate_get,
  3027. tdm_rx_sample_rate_put),
  3028. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3029. tdm_tx_sample_rate_get,
  3030. tdm_tx_sample_rate_put),
  3031. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3032. tdm_rx_format_get,
  3033. tdm_rx_format_put),
  3034. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3035. tdm_tx_format_get,
  3036. tdm_tx_format_put),
  3037. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3038. tdm_rx_ch_get,
  3039. tdm_rx_ch_put),
  3040. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3041. tdm_tx_ch_get,
  3042. tdm_tx_ch_put),
  3043. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3044. aux_pcm_rx_sample_rate_get,
  3045. aux_pcm_rx_sample_rate_put),
  3046. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3047. aux_pcm_rx_sample_rate_get,
  3048. aux_pcm_rx_sample_rate_put),
  3049. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3050. aux_pcm_rx_sample_rate_get,
  3051. aux_pcm_rx_sample_rate_put),
  3052. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3053. aux_pcm_rx_sample_rate_get,
  3054. aux_pcm_rx_sample_rate_put),
  3055. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3056. aux_pcm_rx_sample_rate_get,
  3057. aux_pcm_rx_sample_rate_put),
  3058. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3059. aux_pcm_tx_sample_rate_get,
  3060. aux_pcm_tx_sample_rate_put),
  3061. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3062. aux_pcm_tx_sample_rate_get,
  3063. aux_pcm_tx_sample_rate_put),
  3064. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3065. aux_pcm_tx_sample_rate_get,
  3066. aux_pcm_tx_sample_rate_put),
  3067. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3068. aux_pcm_tx_sample_rate_get,
  3069. aux_pcm_tx_sample_rate_put),
  3070. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3071. aux_pcm_tx_sample_rate_get,
  3072. aux_pcm_tx_sample_rate_put),
  3073. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3074. mi2s_rx_sample_rate_get,
  3075. mi2s_rx_sample_rate_put),
  3076. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3077. mi2s_rx_sample_rate_get,
  3078. mi2s_rx_sample_rate_put),
  3079. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3080. mi2s_rx_sample_rate_get,
  3081. mi2s_rx_sample_rate_put),
  3082. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3083. mi2s_rx_sample_rate_get,
  3084. mi2s_rx_sample_rate_put),
  3085. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3086. mi2s_rx_sample_rate_get,
  3087. mi2s_rx_sample_rate_put),
  3088. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3089. mi2s_tx_sample_rate_get,
  3090. mi2s_tx_sample_rate_put),
  3091. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3092. mi2s_tx_sample_rate_get,
  3093. mi2s_tx_sample_rate_put),
  3094. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3095. mi2s_tx_sample_rate_get,
  3096. mi2s_tx_sample_rate_put),
  3097. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3098. mi2s_tx_sample_rate_get,
  3099. mi2s_tx_sample_rate_put),
  3100. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3101. mi2s_tx_sample_rate_get,
  3102. mi2s_tx_sample_rate_put),
  3103. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3104. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3105. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3106. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3107. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3108. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3109. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3110. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3111. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3112. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3113. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3114. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3115. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3116. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3117. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3118. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3119. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3120. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3121. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3122. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3123. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3124. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3125. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3126. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3127. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3128. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3129. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3130. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3131. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3132. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3133. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3134. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3135. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3136. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3137. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3138. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3139. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3140. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3141. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3142. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3143. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3144. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3145. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3146. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3147. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3148. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3149. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3150. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3151. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3152. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3153. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3154. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3155. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3156. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3157. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3158. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3159. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3160. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3161. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3162. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3163. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3164. msm_snd_vad_cfg_put),
  3165. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3166. msm_spdif_rx_sample_rate_get,
  3167. msm_spdif_rx_sample_rate_put),
  3168. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3169. msm_spdif_tx_sample_rate_get,
  3170. msm_spdif_tx_sample_rate_put),
  3171. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3172. msm_spdif_rx_sample_rate_get,
  3173. msm_spdif_rx_sample_rate_put),
  3174. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3175. msm_spdif_tx_sample_rate_get,
  3176. msm_spdif_tx_sample_rate_put),
  3177. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3178. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3179. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3180. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3181. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3182. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3183. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3184. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3185. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3186. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3187. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3188. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3189. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3190. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3191. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3192. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3193. };
  3194. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3195. int enable, bool dapm)
  3196. {
  3197. int ret = 0;
  3198. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3199. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3200. } else {
  3201. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3202. __func__);
  3203. ret = -EINVAL;
  3204. }
  3205. return ret;
  3206. }
  3207. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3208. int enable, bool dapm)
  3209. {
  3210. int ret = 0;
  3211. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3212. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3213. } else {
  3214. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3215. __func__);
  3216. ret = -EINVAL;
  3217. }
  3218. return ret;
  3219. }
  3220. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3221. struct snd_kcontrol *kcontrol, int event)
  3222. {
  3223. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3224. pr_debug("%s: event = %d\n", __func__, event);
  3225. switch (event) {
  3226. case SND_SOC_DAPM_PRE_PMU:
  3227. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3228. case SND_SOC_DAPM_POST_PMD:
  3229. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3230. }
  3231. return 0;
  3232. }
  3233. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3234. struct snd_kcontrol *kcontrol, int event)
  3235. {
  3236. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3237. pr_debug("%s: event = %d\n", __func__, event);
  3238. switch (event) {
  3239. case SND_SOC_DAPM_PRE_PMU:
  3240. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3241. case SND_SOC_DAPM_POST_PMD:
  3242. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3243. }
  3244. return 0;
  3245. }
  3246. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3247. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3248. msm_mclk_event,
  3249. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3250. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3251. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3252. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3253. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3254. };
  3255. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3256. struct snd_kcontrol *kcontrol, int event)
  3257. {
  3258. struct msm_asoc_mach_data *pdata = NULL;
  3259. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3260. int ret = 0;
  3261. uint32_t dmic_idx;
  3262. int *dmic_gpio_cnt;
  3263. struct device_node *dmic_gpio;
  3264. char *wname;
  3265. wname = strpbrk(w->name, "01234567");
  3266. if (!wname) {
  3267. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3268. return -EINVAL;
  3269. }
  3270. ret = kstrtouint(wname, 10, &dmic_idx);
  3271. if (ret < 0) {
  3272. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3273. __func__);
  3274. return -EINVAL;
  3275. }
  3276. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3277. switch (dmic_idx) {
  3278. case 0:
  3279. case 1:
  3280. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3281. dmic_gpio = pdata->dmic_01_gpio_p;
  3282. break;
  3283. case 2:
  3284. case 3:
  3285. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3286. dmic_gpio = pdata->dmic_23_gpio_p;
  3287. break;
  3288. case 4:
  3289. case 5:
  3290. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3291. dmic_gpio = pdata->dmic_45_gpio_p;
  3292. break;
  3293. case 6:
  3294. case 7:
  3295. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3296. dmic_gpio = pdata->dmic_67_gpio_p;
  3297. break;
  3298. default:
  3299. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3300. __func__);
  3301. return -EINVAL;
  3302. }
  3303. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3304. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3305. switch (event) {
  3306. case SND_SOC_DAPM_PRE_PMU:
  3307. (*dmic_gpio_cnt)++;
  3308. if (*dmic_gpio_cnt == 1) {
  3309. ret = msm_cdc_pinctrl_select_active_state(
  3310. dmic_gpio);
  3311. if (ret < 0) {
  3312. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3313. __func__, "dmic_gpio");
  3314. return ret;
  3315. }
  3316. }
  3317. break;
  3318. case SND_SOC_DAPM_POST_PMD:
  3319. (*dmic_gpio_cnt)--;
  3320. if (*dmic_gpio_cnt == 0) {
  3321. ret = msm_cdc_pinctrl_select_sleep_state(
  3322. dmic_gpio);
  3323. if (ret < 0) {
  3324. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3325. __func__, "dmic_gpio");
  3326. return ret;
  3327. }
  3328. }
  3329. break;
  3330. default:
  3331. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3332. __func__, event);
  3333. return -EINVAL;
  3334. }
  3335. return 0;
  3336. }
  3337. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3338. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3339. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3340. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3341. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3342. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3343. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3344. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3345. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3346. };
  3347. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3348. };
  3349. static inline int param_is_mask(int p)
  3350. {
  3351. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3352. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3353. }
  3354. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3355. int n)
  3356. {
  3357. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3358. }
  3359. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3360. unsigned int bit)
  3361. {
  3362. if (bit >= SNDRV_MASK_MAX)
  3363. return;
  3364. if (param_is_mask(n)) {
  3365. struct snd_mask *m = param_to_mask(p, n);
  3366. m->bits[0] = 0;
  3367. m->bits[1] = 0;
  3368. m->bits[bit >> 5] |= (1 << (bit & 31));
  3369. }
  3370. }
  3371. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3372. {
  3373. int ch_id = 0;
  3374. switch (be_id) {
  3375. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3376. ch_id = SLIM_RX_0;
  3377. break;
  3378. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3379. ch_id = SLIM_RX_1;
  3380. break;
  3381. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3382. ch_id = SLIM_RX_2;
  3383. break;
  3384. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3385. ch_id = SLIM_RX_3;
  3386. break;
  3387. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3388. ch_id = SLIM_RX_4;
  3389. break;
  3390. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3391. ch_id = SLIM_RX_6;
  3392. break;
  3393. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3394. ch_id = SLIM_TX_0;
  3395. break;
  3396. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3397. ch_id = SLIM_TX_3;
  3398. break;
  3399. default:
  3400. ch_id = SLIM_RX_0;
  3401. break;
  3402. }
  3403. return ch_id;
  3404. }
  3405. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3406. {
  3407. *port_id = 0xFFFF;
  3408. switch (be_id) {
  3409. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3410. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3411. break;
  3412. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3413. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3414. break;
  3415. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3416. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3417. break;
  3418. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3419. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3420. break;
  3421. default:
  3422. return -EINVAL;
  3423. }
  3424. return 0;
  3425. }
  3426. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3427. {
  3428. int idx = 0;
  3429. switch (be_id) {
  3430. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3431. idx = WSA_CDC_DMA_RX_0;
  3432. break;
  3433. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3434. idx = WSA_CDC_DMA_TX_0;
  3435. break;
  3436. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3437. idx = WSA_CDC_DMA_RX_1;
  3438. break;
  3439. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3440. idx = WSA_CDC_DMA_TX_1;
  3441. break;
  3442. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3443. idx = WSA_CDC_DMA_TX_2;
  3444. break;
  3445. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3446. idx = VA_CDC_DMA_TX_0;
  3447. break;
  3448. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3449. idx = VA_CDC_DMA_TX_1;
  3450. break;
  3451. default:
  3452. idx = VA_CDC_DMA_TX_0;
  3453. break;
  3454. }
  3455. return idx;
  3456. }
  3457. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3458. struct snd_pcm_hw_params *params)
  3459. {
  3460. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3461. struct snd_interval *rate = hw_param_interval(params,
  3462. SNDRV_PCM_HW_PARAM_RATE);
  3463. struct snd_interval *channels = hw_param_interval(params,
  3464. SNDRV_PCM_HW_PARAM_CHANNELS);
  3465. int rc = 0;
  3466. int idx;
  3467. void *config = NULL;
  3468. struct snd_soc_codec *codec = NULL;
  3469. pr_debug("%s: format = %d, rate = %d\n",
  3470. __func__, params_format(params), params_rate(params));
  3471. switch (dai_link->id) {
  3472. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3473. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3474. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3475. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3476. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3477. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3478. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3479. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3480. slim_rx_cfg[idx].bit_format);
  3481. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3482. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3483. break;
  3484. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3485. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3486. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3487. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3488. slim_tx_cfg[idx].bit_format);
  3489. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3490. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3491. break;
  3492. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3493. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3494. slim_tx_cfg[1].bit_format);
  3495. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3496. channels->min = channels->max = slim_tx_cfg[1].channels;
  3497. break;
  3498. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3499. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3500. SNDRV_PCM_FORMAT_S32_LE);
  3501. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3502. channels->min = channels->max = msm_vi_feed_tx_ch;
  3503. break;
  3504. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3505. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3506. slim_rx_cfg[5].bit_format);
  3507. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3508. channels->min = channels->max = slim_rx_cfg[5].channels;
  3509. break;
  3510. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3511. codec = rtd->codec;
  3512. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3513. channels->min = channels->max = 1;
  3514. config = msm_codec_fn.get_afe_config_fn(codec,
  3515. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3516. if (config) {
  3517. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3518. config, SLIMBUS_5_TX);
  3519. if (rc)
  3520. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3521. __func__, rc);
  3522. }
  3523. break;
  3524. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3525. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3526. slim_rx_cfg[SLIM_RX_7].bit_format);
  3527. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3528. channels->min = channels->max =
  3529. slim_rx_cfg[SLIM_RX_7].channels;
  3530. break;
  3531. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3532. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3533. channels->min = channels->max =
  3534. slim_tx_cfg[SLIM_TX_7].channels;
  3535. break;
  3536. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3537. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3538. channels->min = channels->max =
  3539. slim_tx_cfg[SLIM_TX_8].channels;
  3540. break;
  3541. case MSM_BACKEND_DAI_USB_RX:
  3542. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3543. usb_rx_cfg.bit_format);
  3544. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3545. channels->min = channels->max = usb_rx_cfg.channels;
  3546. break;
  3547. case MSM_BACKEND_DAI_USB_TX:
  3548. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3549. usb_tx_cfg.bit_format);
  3550. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3551. channels->min = channels->max = usb_tx_cfg.channels;
  3552. break;
  3553. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3554. channels->min = channels->max = proxy_rx_cfg.channels;
  3555. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3556. break;
  3557. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3558. channels->min = channels->max =
  3559. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3560. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3561. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3562. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3563. break;
  3564. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3565. channels->min = channels->max =
  3566. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3567. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3568. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3569. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3570. break;
  3571. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3572. channels->min = channels->max =
  3573. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3574. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3575. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3576. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3577. break;
  3578. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3579. channels->min = channels->max =
  3580. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3581. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3582. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3583. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3584. break;
  3585. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3586. channels->min = channels->max =
  3587. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3588. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3589. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3590. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3591. break;
  3592. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3593. channels->min = channels->max =
  3594. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3595. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3596. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3597. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3598. break;
  3599. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3600. channels->min = channels->max =
  3601. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3602. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3603. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3604. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3605. break;
  3606. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3607. channels->min = channels->max =
  3608. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3609. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3610. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3611. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3612. break;
  3613. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3614. channels->min = channels->max =
  3615. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3616. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3617. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3618. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3619. break;
  3620. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3621. channels->min = channels->max =
  3622. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3623. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3624. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3625. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3626. break;
  3627. case MSM_BACKEND_DAI_AUXPCM_RX:
  3628. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3629. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3630. rate->min = rate->max =
  3631. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3632. channels->min = channels->max =
  3633. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3634. break;
  3635. case MSM_BACKEND_DAI_AUXPCM_TX:
  3636. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3637. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3638. rate->min = rate->max =
  3639. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3640. channels->min = channels->max =
  3641. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3642. break;
  3643. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3644. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3645. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3646. rate->min = rate->max =
  3647. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3648. channels->min = channels->max =
  3649. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3650. break;
  3651. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3652. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3653. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3654. rate->min = rate->max =
  3655. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3656. channels->min = channels->max =
  3657. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3658. break;
  3659. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3660. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3661. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3662. rate->min = rate->max =
  3663. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3664. channels->min = channels->max =
  3665. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3666. break;
  3667. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3668. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3669. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3670. rate->min = rate->max =
  3671. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3672. channels->min = channels->max =
  3673. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3674. break;
  3675. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3676. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3677. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3678. rate->min = rate->max =
  3679. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3680. channels->min = channels->max =
  3681. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3682. break;
  3683. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3684. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3685. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3686. rate->min = rate->max =
  3687. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3688. channels->min = channels->max =
  3689. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3690. break;
  3691. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3692. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3693. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3694. rate->min = rate->max =
  3695. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3696. channels->min = channels->max =
  3697. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3698. break;
  3699. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3700. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3701. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3702. rate->min = rate->max =
  3703. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3704. channels->min = channels->max =
  3705. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3706. break;
  3707. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3708. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3709. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3710. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3711. channels->min = channels->max =
  3712. mi2s_rx_cfg[PRIM_MI2S].channels;
  3713. break;
  3714. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3715. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3716. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3717. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3718. channels->min = channels->max =
  3719. mi2s_tx_cfg[PRIM_MI2S].channels;
  3720. break;
  3721. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3722. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3723. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3724. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3725. channels->min = channels->max =
  3726. mi2s_rx_cfg[SEC_MI2S].channels;
  3727. break;
  3728. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3729. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3730. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3731. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3732. channels->min = channels->max =
  3733. mi2s_tx_cfg[SEC_MI2S].channels;
  3734. break;
  3735. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3736. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3737. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3738. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3739. channels->min = channels->max =
  3740. mi2s_rx_cfg[TERT_MI2S].channels;
  3741. break;
  3742. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3743. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3744. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3745. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3746. channels->min = channels->max =
  3747. mi2s_tx_cfg[TERT_MI2S].channels;
  3748. break;
  3749. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3750. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3751. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3752. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3753. channels->min = channels->max =
  3754. mi2s_rx_cfg[QUAT_MI2S].channels;
  3755. break;
  3756. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3757. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3758. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3759. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3760. channels->min = channels->max =
  3761. mi2s_tx_cfg[QUAT_MI2S].channels;
  3762. break;
  3763. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3764. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3765. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3766. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3767. channels->min = channels->max =
  3768. mi2s_rx_cfg[QUIN_MI2S].channels;
  3769. break;
  3770. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3771. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3772. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3773. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3774. channels->min = channels->max =
  3775. mi2s_tx_cfg[QUIN_MI2S].channels;
  3776. break;
  3777. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3778. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3779. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3780. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3781. cdc_dma_rx_cfg[idx].bit_format);
  3782. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3783. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3784. break;
  3785. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3786. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3787. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3788. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3789. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3790. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3791. cdc_dma_tx_cfg[idx].bit_format);
  3792. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3793. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3794. break;
  3795. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3796. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3797. SNDRV_PCM_FORMAT_S32_LE);
  3798. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3799. channels->min = channels->max = msm_vi_feed_tx_ch;
  3800. break;
  3801. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3802. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3803. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3804. rate->min = rate->max =
  3805. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3806. channels->min = channels->max =
  3807. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3808. break;
  3809. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3810. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3811. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3812. rate->min = rate->max =
  3813. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3814. channels->min = channels->max =
  3815. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3816. break;
  3817. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  3818. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3819. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  3820. rate->min = rate->max =
  3821. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  3822. channels->min = channels->max =
  3823. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  3824. break;
  3825. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  3826. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3827. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  3828. rate->min = rate->max =
  3829. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  3830. channels->min = channels->max =
  3831. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  3832. break;
  3833. default:
  3834. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3835. break;
  3836. }
  3837. return rc;
  3838. }
  3839. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3840. {
  3841. int ret = 0;
  3842. void *config_data = NULL;
  3843. if (!msm_codec_fn.get_afe_config_fn) {
  3844. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3845. __func__);
  3846. return -EINVAL;
  3847. }
  3848. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3849. AFE_CDC_REGISTERS_CONFIG);
  3850. if (config_data) {
  3851. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3852. if (ret) {
  3853. dev_err(codec->dev,
  3854. "%s: Failed to set codec registers config %d\n",
  3855. __func__, ret);
  3856. return ret;
  3857. }
  3858. }
  3859. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3860. AFE_CDC_REGISTER_PAGE_CONFIG);
  3861. if (config_data) {
  3862. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3863. 0);
  3864. if (ret)
  3865. dev_err(codec->dev,
  3866. "%s: Failed to set cdc register page config\n",
  3867. __func__);
  3868. }
  3869. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3870. AFE_SLIMBUS_SLAVE_CONFIG);
  3871. if (config_data) {
  3872. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3873. if (ret) {
  3874. dev_err(codec->dev,
  3875. "%s: Failed to set slimbus slave config %d\n",
  3876. __func__, ret);
  3877. return ret;
  3878. }
  3879. }
  3880. return 0;
  3881. }
  3882. static void msm_afe_clear_config(void)
  3883. {
  3884. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3885. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3886. }
  3887. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3888. struct snd_card *card)
  3889. {
  3890. int ret = 0;
  3891. unsigned long timeout;
  3892. int adsp_ready = 0;
  3893. bool snd_card_online = 0;
  3894. timeout = jiffies +
  3895. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3896. do {
  3897. if (!snd_card_online) {
  3898. snd_card_online = snd_card_is_online_state(card);
  3899. pr_debug("%s: Sound card is %s\n", __func__,
  3900. snd_card_online ? "Online" : "Offline");
  3901. }
  3902. if (!adsp_ready) {
  3903. adsp_ready = q6core_is_adsp_ready();
  3904. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3905. adsp_ready ? "ready" : "not ready");
  3906. }
  3907. if (snd_card_online && adsp_ready)
  3908. break;
  3909. /*
  3910. * Sound card/ADSP will be coming up after subsystem restart and
  3911. * it might not be fully up when the control reaches
  3912. * here. So, wait for 50msec before checking ADSP state
  3913. */
  3914. msleep(50);
  3915. } while (time_after(timeout, jiffies));
  3916. if (!snd_card_online || !adsp_ready) {
  3917. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3918. __func__,
  3919. snd_card_online ? "Online" : "Offline",
  3920. adsp_ready ? "ready" : "not ready");
  3921. ret = -ETIMEDOUT;
  3922. goto err;
  3923. }
  3924. ret = msm_afe_set_config(codec);
  3925. if (ret)
  3926. pr_err("%s: Failed to set AFE config. err %d\n",
  3927. __func__, ret);
  3928. return 0;
  3929. err:
  3930. return ret;
  3931. }
  3932. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3933. unsigned long opcode, void *ptr)
  3934. {
  3935. int ret;
  3936. struct snd_soc_card *card = NULL;
  3937. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3938. struct snd_soc_pcm_runtime *rtd;
  3939. struct snd_soc_codec *codec;
  3940. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3941. switch (opcode) {
  3942. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3943. /*
  3944. * Use flag to ignore initial boot notifications
  3945. * On initial boot msm_adsp_power_up_config is
  3946. * called on init. There is no need to clear
  3947. * and set the config again on initial boot.
  3948. */
  3949. if (is_initial_boot)
  3950. break;
  3951. msm_afe_clear_config();
  3952. break;
  3953. case AUDIO_NOTIFIER_SERVICE_UP:
  3954. if (is_initial_boot) {
  3955. is_initial_boot = false;
  3956. break;
  3957. }
  3958. if (!spdev)
  3959. return -EINVAL;
  3960. card = platform_get_drvdata(spdev);
  3961. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3962. if (!rtd) {
  3963. dev_err(card->dev,
  3964. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3965. __func__, be_dl_name);
  3966. ret = -EINVAL;
  3967. goto err;
  3968. }
  3969. codec = rtd->codec;
  3970. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3971. if (ret < 0) {
  3972. dev_err(card->dev,
  3973. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3974. __func__, ret);
  3975. goto err;
  3976. }
  3977. break;
  3978. default:
  3979. break;
  3980. }
  3981. err:
  3982. return NOTIFY_OK;
  3983. }
  3984. static struct notifier_block service_nb = {
  3985. .notifier_call = qcs405_notifier_service_cb,
  3986. .priority = -INT_MAX,
  3987. };
  3988. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3989. {
  3990. int ret = 0;
  3991. void *config_data;
  3992. struct snd_soc_codec *codec = rtd->codec;
  3993. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3994. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3995. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3996. struct snd_card *card;
  3997. struct msm_asoc_mach_data *pdata =
  3998. snd_soc_card_get_drvdata(rtd->card);
  3999. /*
  4000. * Codec SLIMBUS configuration
  4001. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4002. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4003. * TX14, TX15, TX16
  4004. */
  4005. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4006. 151, 152, 153, 154, 155, 156};
  4007. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4008. 134, 135, 136, 137, 138, 139,
  4009. 140, 141, 142, 143};
  4010. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4011. rtd->pmdown_time = 0;
  4012. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4013. ARRAY_SIZE(msm_snd_sb_controls));
  4014. if (ret < 0) {
  4015. pr_err("%s: add_codec_controls failed, err %d\n",
  4016. __func__, ret);
  4017. return ret;
  4018. }
  4019. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4020. ARRAY_SIZE(msm_dapm_widgets));
  4021. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4022. ARRAY_SIZE(wcd_audio_paths));
  4023. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4024. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4025. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4026. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4027. snd_soc_dapm_sync(dapm);
  4028. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4029. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4030. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4031. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4032. if (ret) {
  4033. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4034. __func__, ret);
  4035. goto err;
  4036. }
  4037. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4038. AFE_AANC_VERSION);
  4039. if (config_data) {
  4040. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4041. if (ret) {
  4042. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4043. __func__, ret);
  4044. goto err;
  4045. }
  4046. }
  4047. card = rtd->card->snd_card;
  4048. if (!pdata->codec_root)
  4049. pdata->codec_root = snd_info_create_subdir(card->module,
  4050. "codecs", card->proc_root);
  4051. if (!pdata->codec_root) {
  4052. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4053. __func__);
  4054. ret = 0;
  4055. goto err;
  4056. }
  4057. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4058. codec_reg_done = true;
  4059. return 0;
  4060. err:
  4061. return ret;
  4062. }
  4063. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4064. {
  4065. int ret = 0;
  4066. struct snd_soc_codec *codec = rtd->codec;
  4067. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4068. struct snd_card *card;
  4069. struct msm_asoc_mach_data *pdata =
  4070. snd_soc_card_get_drvdata(rtd->card);
  4071. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4072. ARRAY_SIZE(msm_snd_va_controls));
  4073. if (ret < 0) {
  4074. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4075. __func__, ret);
  4076. return ret;
  4077. }
  4078. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4079. ARRAY_SIZE(msm_va_dapm_widgets));
  4080. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4081. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4082. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4083. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4084. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4085. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4086. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4087. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4088. snd_soc_dapm_sync(dapm);
  4089. card = rtd->card->snd_card;
  4090. if (!pdata->codec_root)
  4091. pdata->codec_root = snd_info_create_subdir(card->module,
  4092. "codecs", card->proc_root);
  4093. if (!pdata->codec_root) {
  4094. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4095. __func__);
  4096. ret = 0;
  4097. goto done;
  4098. }
  4099. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4100. done:
  4101. return ret;
  4102. }
  4103. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4104. {
  4105. int ret = 0;
  4106. struct snd_soc_codec *codec = rtd->codec;
  4107. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4108. struct snd_soc_component *aux_comp;
  4109. struct snd_card *card;
  4110. struct msm_asoc_mach_data *pdata =
  4111. snd_soc_card_get_drvdata(rtd->card);
  4112. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4113. ARRAY_SIZE(msm_snd_wsa_controls));
  4114. if (ret < 0) {
  4115. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4116. __func__, ret);
  4117. return ret;
  4118. }
  4119. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4120. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4121. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4122. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4123. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4124. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4125. snd_soc_dapm_sync(dapm);
  4126. /*
  4127. * Send speaker configuration only for WSA8810.
  4128. * Default configuration is for WSA8815.
  4129. */
  4130. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4131. __func__, rtd->card->num_aux_devs);
  4132. if (rtd->card->num_aux_devs &&
  4133. !list_empty(&rtd->card->component_dev_list)) {
  4134. aux_comp = list_first_entry(
  4135. &rtd->card->component_dev_list,
  4136. struct snd_soc_component,
  4137. card_aux_list);
  4138. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4139. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4140. wsa_macro_set_spkr_mode(rtd->codec,
  4141. WSA_MACRO_SPKR_MODE_1);
  4142. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4143. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4144. }
  4145. }
  4146. card = rtd->card->snd_card;
  4147. if (!pdata->codec_root)
  4148. pdata->codec_root = snd_info_create_subdir(card->module,
  4149. "codecs", card->proc_root);
  4150. if (!pdata->codec_root) {
  4151. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4152. __func__);
  4153. ret = 0;
  4154. goto done;
  4155. }
  4156. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4157. done:
  4158. return ret;
  4159. }
  4160. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4161. {
  4162. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4163. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  4164. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4165. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4166. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4167. }
  4168. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4169. struct snd_pcm_hw_params *params)
  4170. {
  4171. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4172. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4173. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4174. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4175. int ret = 0;
  4176. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4177. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4178. u32 user_set_tx_ch = 0;
  4179. u32 rx_ch_count;
  4180. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4181. ret = snd_soc_dai_get_channel_map(codec_dai,
  4182. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4183. if (ret < 0) {
  4184. pr_err("%s: failed to get codec chan map, err:%d\n",
  4185. __func__, ret);
  4186. goto err;
  4187. }
  4188. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4189. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4190. slim_rx_cfg[5].channels);
  4191. rx_ch_count = slim_rx_cfg[5].channels;
  4192. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4193. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4194. slim_rx_cfg[2].channels);
  4195. rx_ch_count = slim_rx_cfg[2].channels;
  4196. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4197. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4198. slim_rx_cfg[6].channels);
  4199. rx_ch_count = slim_rx_cfg[6].channels;
  4200. } else {
  4201. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4202. slim_rx_cfg[0].channels);
  4203. rx_ch_count = slim_rx_cfg[0].channels;
  4204. }
  4205. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4206. rx_ch_count, rx_ch);
  4207. if (ret < 0) {
  4208. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4209. __func__, ret);
  4210. goto err;
  4211. }
  4212. } else {
  4213. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4214. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4215. ret = snd_soc_dai_get_channel_map(codec_dai,
  4216. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4217. if (ret < 0) {
  4218. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4219. __func__, ret);
  4220. goto err;
  4221. }
  4222. /* For <codec>_tx1 case */
  4223. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4224. user_set_tx_ch = slim_tx_cfg[0].channels;
  4225. /* For <codec>_tx3 case */
  4226. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4227. user_set_tx_ch = slim_tx_cfg[1].channels;
  4228. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4229. user_set_tx_ch = msm_vi_feed_tx_ch;
  4230. else
  4231. user_set_tx_ch = tx_ch_cnt;
  4232. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4233. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4234. tx_ch_cnt, dai_link->id);
  4235. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4236. user_set_tx_ch, tx_ch, 0, 0);
  4237. if (ret < 0)
  4238. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4239. __func__, ret);
  4240. }
  4241. err:
  4242. return ret;
  4243. }
  4244. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4245. struct snd_pcm_hw_params *params)
  4246. {
  4247. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4248. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4249. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4250. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4251. int ret = 0;
  4252. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4253. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4254. u32 user_set_tx_ch = 0;
  4255. u32 user_set_rx_ch = 0;
  4256. u32 ch_id;
  4257. ret = snd_soc_dai_get_channel_map(codec_dai,
  4258. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4259. &rx_ch_cdc_dma);
  4260. if (ret < 0) {
  4261. pr_err("%s: failed to get codec chan map, err:%d\n",
  4262. __func__, ret);
  4263. goto err;
  4264. }
  4265. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4266. switch (dai_link->id) {
  4267. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4268. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4269. {
  4270. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4271. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4272. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4273. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4274. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4275. user_set_rx_ch, &rx_ch_cdc_dma);
  4276. if (ret < 0) {
  4277. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4278. __func__, ret);
  4279. goto err;
  4280. }
  4281. }
  4282. break;
  4283. }
  4284. } else {
  4285. switch (dai_link->id) {
  4286. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4287. {
  4288. user_set_tx_ch = msm_vi_feed_tx_ch;
  4289. }
  4290. break;
  4291. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4292. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4293. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4294. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4295. {
  4296. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4297. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4298. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4299. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4300. }
  4301. break;
  4302. }
  4303. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4304. &tx_ch_cdc_dma, 0, 0);
  4305. if (ret < 0) {
  4306. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4307. __func__, ret);
  4308. goto err;
  4309. }
  4310. }
  4311. err:
  4312. return ret;
  4313. }
  4314. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4315. struct snd_pcm_hw_params *params)
  4316. {
  4317. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4318. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4319. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4320. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4321. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4322. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4323. int ret;
  4324. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4325. codec_dai->name, codec_dai->id);
  4326. ret = snd_soc_dai_get_channel_map(codec_dai,
  4327. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4328. if (ret) {
  4329. dev_err(rtd->dev,
  4330. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4331. __func__, ret);
  4332. goto err;
  4333. }
  4334. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4335. __func__, tx_ch_cnt, dai_link->id);
  4336. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4337. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4338. if (ret)
  4339. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4340. __func__, ret);
  4341. err:
  4342. return ret;
  4343. }
  4344. static int msm_get_port_id(int be_id)
  4345. {
  4346. int afe_port_id;
  4347. switch (be_id) {
  4348. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4349. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4350. break;
  4351. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4352. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4353. break;
  4354. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4355. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4356. break;
  4357. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4358. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4359. break;
  4360. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4361. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4362. break;
  4363. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4364. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4365. break;
  4366. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4367. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4368. break;
  4369. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4370. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4371. break;
  4372. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4373. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4374. break;
  4375. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4376. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4377. break;
  4378. default:
  4379. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4380. afe_port_id = -EINVAL;
  4381. }
  4382. return afe_port_id;
  4383. }
  4384. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4385. {
  4386. u32 bit_per_sample;
  4387. switch (bit_format) {
  4388. case SNDRV_PCM_FORMAT_S32_LE:
  4389. case SNDRV_PCM_FORMAT_S24_3LE:
  4390. case SNDRV_PCM_FORMAT_S24_LE:
  4391. bit_per_sample = 32;
  4392. break;
  4393. case SNDRV_PCM_FORMAT_S16_LE:
  4394. default:
  4395. bit_per_sample = 16;
  4396. break;
  4397. }
  4398. return bit_per_sample;
  4399. }
  4400. static void update_mi2s_clk_val(int dai_id, int stream)
  4401. {
  4402. u32 bit_per_sample;
  4403. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4404. bit_per_sample =
  4405. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4406. mi2s_clk[dai_id].clk_freq_in_hz =
  4407. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4408. } else {
  4409. bit_per_sample =
  4410. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4411. mi2s_clk[dai_id].clk_freq_in_hz =
  4412. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4413. }
  4414. }
  4415. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4416. {
  4417. int ret = 0;
  4418. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4419. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4420. int port_id = 0;
  4421. int index = cpu_dai->id;
  4422. port_id = msm_get_port_id(rtd->dai_link->id);
  4423. if (port_id < 0) {
  4424. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4425. ret = port_id;
  4426. goto err;
  4427. }
  4428. if (enable) {
  4429. update_mi2s_clk_val(index, substream->stream);
  4430. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4431. mi2s_clk[index].clk_freq_in_hz);
  4432. }
  4433. mi2s_clk[index].enable = enable;
  4434. ret = afe_set_lpass_clock_v2(port_id,
  4435. &mi2s_clk[index]);
  4436. if (ret < 0) {
  4437. dev_err(rtd->card->dev,
  4438. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4439. __func__, port_id, ret);
  4440. goto err;
  4441. }
  4442. err:
  4443. return ret;
  4444. }
  4445. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4446. enum pinctrl_pin_state new_state)
  4447. {
  4448. int ret = 0;
  4449. int curr_state = 0;
  4450. if (pinctrl_info == NULL) {
  4451. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4452. ret = -EINVAL;
  4453. goto err;
  4454. }
  4455. if (pinctrl_info->pinctrl == NULL) {
  4456. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4457. ret = -EINVAL;
  4458. goto err;
  4459. }
  4460. curr_state = pinctrl_info->curr_state;
  4461. pinctrl_info->curr_state = new_state;
  4462. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4463. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4464. if (curr_state == pinctrl_info->curr_state) {
  4465. pr_debug("%s: Already in same state\n", __func__);
  4466. goto err;
  4467. }
  4468. if (curr_state != STATE_DISABLE &&
  4469. pinctrl_info->curr_state != STATE_DISABLE) {
  4470. pr_debug("%s: state already active cannot switch\n", __func__);
  4471. ret = -EIO;
  4472. goto err;
  4473. }
  4474. switch (pinctrl_info->curr_state) {
  4475. case STATE_MI2S_ACTIVE:
  4476. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4477. pinctrl_info->mi2s_active);
  4478. if (ret) {
  4479. pr_err("%s: MI2S state select failed with %d\n",
  4480. __func__, ret);
  4481. ret = -EIO;
  4482. goto err;
  4483. }
  4484. break;
  4485. case STATE_TDM_ACTIVE:
  4486. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4487. pinctrl_info->tdm_active);
  4488. if (ret) {
  4489. pr_err("%s: TDM state select failed with %d\n",
  4490. __func__, ret);
  4491. ret = -EIO;
  4492. goto err;
  4493. }
  4494. break;
  4495. case STATE_DISABLE:
  4496. if (curr_state == STATE_MI2S_ACTIVE) {
  4497. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4498. pinctrl_info->mi2s_disable);
  4499. } else {
  4500. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4501. pinctrl_info->tdm_disable);
  4502. }
  4503. if (ret) {
  4504. pr_err("%s: state disable failed with %d\n",
  4505. __func__, ret);
  4506. ret = -EIO;
  4507. goto err;
  4508. }
  4509. break;
  4510. default:
  4511. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4512. return -EINVAL;
  4513. }
  4514. err:
  4515. return ret;
  4516. }
  4517. static void msm_release_pinctrl(struct platform_device *pdev)
  4518. {
  4519. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4520. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4521. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4522. if (pinctrl_info->pinctrl) {
  4523. devm_pinctrl_put(pinctrl_info->pinctrl);
  4524. pinctrl_info->pinctrl = NULL;
  4525. }
  4526. }
  4527. static int msm_get_pinctrl(struct platform_device *pdev)
  4528. {
  4529. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4530. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4531. struct msm_pinctrl_info *pinctrl_info = NULL;
  4532. struct pinctrl *pinctrl;
  4533. int ret;
  4534. pinctrl_info = &pdata->pinctrl_info;
  4535. if (pinctrl_info == NULL) {
  4536. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4537. return -EINVAL;
  4538. }
  4539. pinctrl = devm_pinctrl_get(&pdev->dev);
  4540. if (IS_ERR_OR_NULL(pinctrl)) {
  4541. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4542. return -EINVAL;
  4543. }
  4544. pinctrl_info->pinctrl = pinctrl;
  4545. /* get all the states handles from Device Tree */
  4546. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4547. "quat-mi2s-sleep");
  4548. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4549. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4550. goto err;
  4551. }
  4552. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4553. "quat-mi2s-active");
  4554. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4555. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4556. goto err;
  4557. }
  4558. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4559. "quat-tdm-sleep");
  4560. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4561. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4562. goto err;
  4563. }
  4564. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4565. "quat-tdm-active");
  4566. if (IS_ERR(pinctrl_info->tdm_active)) {
  4567. pr_err("%s: could not get tdm_active pinstate\n",
  4568. __func__);
  4569. goto err;
  4570. }
  4571. /* Reset the TLMM pins to a default state */
  4572. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4573. pinctrl_info->mi2s_disable);
  4574. if (ret != 0) {
  4575. pr_err("%s: Disable TLMM pins failed with %d\n",
  4576. __func__, ret);
  4577. ret = -EIO;
  4578. goto err;
  4579. }
  4580. pinctrl_info->curr_state = STATE_DISABLE;
  4581. return 0;
  4582. err:
  4583. devm_pinctrl_put(pinctrl);
  4584. pinctrl_info->pinctrl = NULL;
  4585. return -EINVAL;
  4586. }
  4587. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4588. struct snd_pcm_hw_params *params)
  4589. {
  4590. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4591. struct snd_interval *rate = hw_param_interval(params,
  4592. SNDRV_PCM_HW_PARAM_RATE);
  4593. struct snd_interval *channels = hw_param_interval(params,
  4594. SNDRV_PCM_HW_PARAM_CHANNELS);
  4595. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4596. channels->min = channels->max =
  4597. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4598. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4599. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4600. rate->min = rate->max =
  4601. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4602. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4603. channels->min = channels->max =
  4604. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4605. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4606. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4607. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4608. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4609. channels->min = channels->max =
  4610. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4611. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4612. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4613. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4614. } else {
  4615. pr_err("%s: dai id 0x%x not supported\n",
  4616. __func__, cpu_dai->id);
  4617. return -EINVAL;
  4618. }
  4619. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4620. __func__, cpu_dai->id, channels->max, rate->max,
  4621. params_format(params));
  4622. return 0;
  4623. }
  4624. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4625. struct snd_pcm_hw_params *params)
  4626. {
  4627. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4628. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4629. int ret = 0;
  4630. int slot_width = 32;
  4631. int channels, slots;
  4632. unsigned int slot_mask, rate, clk_freq;
  4633. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4634. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4635. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4636. switch (cpu_dai->id) {
  4637. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4638. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4639. break;
  4640. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4641. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4642. break;
  4643. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4644. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4645. break;
  4646. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4647. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4648. break;
  4649. case AFE_PORT_ID_QUINARY_TDM_RX:
  4650. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4651. break;
  4652. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4653. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4654. break;
  4655. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4656. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4657. break;
  4658. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4659. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4660. break;
  4661. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4662. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4663. break;
  4664. case AFE_PORT_ID_QUINARY_TDM_TX:
  4665. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4666. break;
  4667. default:
  4668. pr_err("%s: dai id 0x%x not supported\n",
  4669. __func__, cpu_dai->id);
  4670. return -EINVAL;
  4671. }
  4672. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4673. /*2 slot config - bits 0 and 1 set for the first two slots */
  4674. slot_mask = 0x0000FFFF >> (16-slots);
  4675. channels = slots;
  4676. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4677. __func__, slot_width, slots);
  4678. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4679. slots, slot_width);
  4680. if (ret < 0) {
  4681. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4682. __func__, ret);
  4683. goto end;
  4684. }
  4685. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4686. 0, NULL, channels, slot_offset);
  4687. if (ret < 0) {
  4688. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4689. __func__, ret);
  4690. goto end;
  4691. }
  4692. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4693. /*2 slot config - bits 0 and 1 set for the first two slots */
  4694. slot_mask = 0x0000FFFF >> (16-slots);
  4695. channels = slots;
  4696. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4697. __func__, slot_width, slots);
  4698. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4699. slots, slot_width);
  4700. if (ret < 0) {
  4701. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4702. __func__, ret);
  4703. goto end;
  4704. }
  4705. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4706. channels, slot_offset, 0, NULL);
  4707. if (ret < 0) {
  4708. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4709. __func__, ret);
  4710. goto end;
  4711. }
  4712. } else {
  4713. ret = -EINVAL;
  4714. pr_err("%s: invalid use case, err:%d\n",
  4715. __func__, ret);
  4716. goto end;
  4717. }
  4718. rate = params_rate(params);
  4719. clk_freq = rate * slot_width * slots;
  4720. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4721. if (ret < 0)
  4722. pr_err("%s: failed to set tdm clk, err:%d\n",
  4723. __func__, ret);
  4724. end:
  4725. return ret;
  4726. }
  4727. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4728. {
  4729. int ret = 0;
  4730. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4731. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4732. struct snd_soc_card *card = rtd->card;
  4733. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4734. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4735. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4736. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4737. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4738. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4739. if (ret)
  4740. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4741. __func__, ret);
  4742. }
  4743. return ret;
  4744. }
  4745. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4746. {
  4747. int ret = 0;
  4748. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4749. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4750. struct snd_soc_card *card = rtd->card;
  4751. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4752. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4753. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4754. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4755. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4756. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4757. if (ret)
  4758. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4759. __func__, ret);
  4760. }
  4761. }
  4762. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4763. .hw_params = qcs405_tdm_snd_hw_params,
  4764. .startup = qcs405_tdm_snd_startup,
  4765. .shutdown = qcs405_tdm_snd_shutdown
  4766. };
  4767. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4768. {
  4769. cpumask_t mask;
  4770. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4771. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4772. cpumask_clear(&mask);
  4773. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4774. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4775. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4776. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4777. pm_qos_add_request(&substream->latency_pm_qos_req,
  4778. PM_QOS_CPU_DMA_LATENCY,
  4779. MSM_LL_QOS_VALUE);
  4780. return 0;
  4781. }
  4782. static struct snd_soc_ops msm_fe_qos_ops = {
  4783. .prepare = msm_fe_qos_prepare,
  4784. };
  4785. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4786. {
  4787. int ret = 0;
  4788. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4789. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4790. int index = cpu_dai->id;
  4791. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4792. struct snd_soc_card *card = rtd->card;
  4793. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4794. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4795. int ret_pinctrl = 0;
  4796. dev_dbg(rtd->card->dev,
  4797. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4798. __func__, substream->name, substream->stream,
  4799. cpu_dai->name, cpu_dai->id);
  4800. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4801. ret = -EINVAL;
  4802. dev_err(rtd->card->dev,
  4803. "%s: CPU DAI id (%d) out of range\n",
  4804. __func__, cpu_dai->id);
  4805. goto err;
  4806. }
  4807. /*
  4808. * Mutex protection in case the same MI2S
  4809. * interface using for both TX and RX so
  4810. * that the same clock won't be enable twice.
  4811. */
  4812. mutex_lock(&mi2s_intf_conf[index].lock);
  4813. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4814. /* Check if msm needs to provide the clock to the interface */
  4815. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4816. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4817. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4818. }
  4819. ret = msm_mi2s_set_sclk(substream, true);
  4820. if (ret < 0) {
  4821. dev_err(rtd->card->dev,
  4822. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4823. __func__, ret);
  4824. goto clean_up;
  4825. }
  4826. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4827. if (ret < 0) {
  4828. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4829. __func__, index, ret);
  4830. goto clk_off;
  4831. }
  4832. if (index == QUAT_MI2S) {
  4833. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4834. STATE_MI2S_ACTIVE);
  4835. if (ret_pinctrl)
  4836. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4837. __func__, ret_pinctrl);
  4838. }
  4839. }
  4840. clk_off:
  4841. if (ret < 0)
  4842. msm_mi2s_set_sclk(substream, false);
  4843. clean_up:
  4844. if (ret < 0)
  4845. mi2s_intf_conf[index].ref_cnt--;
  4846. mutex_unlock(&mi2s_intf_conf[index].lock);
  4847. err:
  4848. return ret;
  4849. }
  4850. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4851. {
  4852. int ret;
  4853. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4854. int index = rtd->cpu_dai->id;
  4855. struct snd_soc_card *card = rtd->card;
  4856. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4857. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4858. int ret_pinctrl = 0;
  4859. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4860. substream->name, substream->stream);
  4861. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4862. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4863. return;
  4864. }
  4865. mutex_lock(&mi2s_intf_conf[index].lock);
  4866. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4867. ret = msm_mi2s_set_sclk(substream, false);
  4868. if (ret < 0)
  4869. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4870. __func__, index, ret);
  4871. if (index == QUAT_MI2S) {
  4872. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4873. STATE_DISABLE);
  4874. if (ret_pinctrl)
  4875. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4876. __func__, ret_pinctrl);
  4877. }
  4878. }
  4879. mutex_unlock(&mi2s_intf_conf[index].lock);
  4880. }
  4881. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4882. {
  4883. int ret = 0;
  4884. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4885. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4886. int port_id = cpu_dai->id;
  4887. struct afe_clk_set clk_cfg;
  4888. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4889. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4890. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4891. clk_cfg.enable = enable;
  4892. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4893. switch (port_id) {
  4894. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4895. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  4896. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  4897. clk_cfg.clk_freq_in_hz =
  4898. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4899. break;
  4900. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4901. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  4902. clk_cfg.clk_freq_in_hz =
  4903. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4904. break;
  4905. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  4906. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  4907. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4908. break;
  4909. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  4910. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  4911. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4912. break;
  4913. }
  4914. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4915. if (ret < 0) {
  4916. dev_err(rtd->card->dev,
  4917. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4918. __func__, port_id, ret);
  4919. goto err;
  4920. }
  4921. /* Set NPL clock for RX in addition */
  4922. switch (port_id) {
  4923. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4924. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  4925. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4926. if (ret < 0) {
  4927. dev_err(rtd->card->dev,
  4928. "%s: afe NPL failed port 0x%x, err:%d\n",
  4929. __func__, port_id, ret);
  4930. goto err;
  4931. }
  4932. break;
  4933. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4934. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  4935. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4936. if (ret < 0) {
  4937. dev_err(rtd->card->dev,
  4938. "%s: afe NPL failed for port 0x%x, err:%d\n",
  4939. __func__, port_id, ret);
  4940. goto err;
  4941. }
  4942. break;
  4943. }
  4944. if (enable) {
  4945. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4946. clk_cfg.clk_freq_in_hz);
  4947. }
  4948. err:
  4949. return ret;
  4950. }
  4951. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  4952. {
  4953. int ret = 0;
  4954. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4955. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4956. int port_id = cpu_dai->id;
  4957. dev_dbg(rtd->card->dev,
  4958. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4959. __func__, substream->name, substream->stream,
  4960. cpu_dai->name, cpu_dai->id);
  4961. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4962. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4963. ret = -EINVAL;
  4964. dev_err(rtd->card->dev,
  4965. "%s: CPU DAI id (%d) out of range\n",
  4966. __func__, cpu_dai->id);
  4967. goto err;
  4968. }
  4969. ret = msm_spdif_set_clk(substream, true);
  4970. if (ret < 0) {
  4971. dev_err(rtd->card->dev,
  4972. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  4973. __func__, port_id, ret);
  4974. }
  4975. err:
  4976. return ret;
  4977. }
  4978. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  4979. {
  4980. int ret;
  4981. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4982. int port_id = rtd->cpu_dai->id;
  4983. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4984. substream->name, substream->stream);
  4985. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4986. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4987. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  4988. return;
  4989. }
  4990. ret = msm_spdif_set_clk(substream, false);
  4991. if (ret < 0)
  4992. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  4993. __func__, port_id, ret);
  4994. }
  4995. static struct snd_soc_ops msm_mi2s_be_ops = {
  4996. .startup = msm_mi2s_snd_startup,
  4997. .shutdown = msm_mi2s_snd_shutdown,
  4998. };
  4999. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5000. .hw_params = msm_snd_cdc_dma_hw_params,
  5001. };
  5002. static struct snd_soc_ops msm_be_ops = {
  5003. .hw_params = msm_snd_hw_params,
  5004. };
  5005. static struct snd_soc_ops msm_wcn_ops = {
  5006. .hw_params = msm_wcn_hw_params,
  5007. };
  5008. static struct snd_soc_ops msm_spdif_be_ops = {
  5009. .startup = msm_spdif_snd_startup,
  5010. .shutdown = msm_spdif_snd_shutdown,
  5011. };
  5012. /* Digital audio interface glue - connects codec <---> CPU */
  5013. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5014. /* FrontEnd DAI Links */
  5015. {
  5016. .name = MSM_DAILINK_NAME(Media1),
  5017. .stream_name = "MultiMedia1",
  5018. .cpu_dai_name = "MultiMedia1",
  5019. .platform_name = "msm-pcm-dsp.0",
  5020. .dynamic = 1,
  5021. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5022. .dpcm_playback = 1,
  5023. .dpcm_capture = 1,
  5024. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5025. SND_SOC_DPCM_TRIGGER_POST},
  5026. .codec_dai_name = "snd-soc-dummy-dai",
  5027. .codec_name = "snd-soc-dummy",
  5028. .ignore_suspend = 1,
  5029. /* this dainlink has playback support */
  5030. .ignore_pmdown_time = 1,
  5031. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5032. },
  5033. {
  5034. .name = MSM_DAILINK_NAME(Media2),
  5035. .stream_name = "MultiMedia2",
  5036. .cpu_dai_name = "MultiMedia2",
  5037. .platform_name = "msm-pcm-dsp.0",
  5038. .dynamic = 1,
  5039. .dpcm_playback = 1,
  5040. .dpcm_capture = 1,
  5041. .codec_dai_name = "snd-soc-dummy-dai",
  5042. .codec_name = "snd-soc-dummy",
  5043. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5044. SND_SOC_DPCM_TRIGGER_POST},
  5045. .ignore_suspend = 1,
  5046. /* this dainlink has playback support */
  5047. .ignore_pmdown_time = 1,
  5048. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5049. },
  5050. {
  5051. .name = "VoiceMMode1",
  5052. .stream_name = "VoiceMMode1",
  5053. .cpu_dai_name = "VoiceMMode1",
  5054. .platform_name = "msm-pcm-voice",
  5055. .dynamic = 1,
  5056. .dpcm_playback = 1,
  5057. .dpcm_capture = 1,
  5058. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5059. SND_SOC_DPCM_TRIGGER_POST},
  5060. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5061. .ignore_suspend = 1,
  5062. .ignore_pmdown_time = 1,
  5063. .codec_dai_name = "snd-soc-dummy-dai",
  5064. .codec_name = "snd-soc-dummy",
  5065. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5066. },
  5067. {
  5068. .name = "MSM VoIP",
  5069. .stream_name = "VoIP",
  5070. .cpu_dai_name = "VoIP",
  5071. .platform_name = "msm-voip-dsp",
  5072. .dynamic = 1,
  5073. .dpcm_playback = 1,
  5074. .dpcm_capture = 1,
  5075. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5076. SND_SOC_DPCM_TRIGGER_POST},
  5077. .codec_dai_name = "snd-soc-dummy-dai",
  5078. .codec_name = "snd-soc-dummy",
  5079. .ignore_suspend = 1,
  5080. /* this dainlink has playback support */
  5081. .ignore_pmdown_time = 1,
  5082. .id = MSM_FRONTEND_DAI_VOIP,
  5083. },
  5084. {
  5085. .name = MSM_DAILINK_NAME(ULL),
  5086. .stream_name = "MultiMedia3",
  5087. .cpu_dai_name = "MultiMedia3",
  5088. .platform_name = "msm-pcm-dsp.2",
  5089. .dynamic = 1,
  5090. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5091. .dpcm_playback = 1,
  5092. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5093. SND_SOC_DPCM_TRIGGER_POST},
  5094. .codec_dai_name = "snd-soc-dummy-dai",
  5095. .codec_name = "snd-soc-dummy",
  5096. .ignore_suspend = 1,
  5097. /* this dainlink has playback support */
  5098. .ignore_pmdown_time = 1,
  5099. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5100. },
  5101. /* Hostless PCM purpose */
  5102. {
  5103. .name = "SLIMBUS_0 Hostless",
  5104. .stream_name = "SLIMBUS_0 Hostless",
  5105. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5106. .platform_name = "msm-pcm-hostless",
  5107. .dynamic = 1,
  5108. .dpcm_playback = 1,
  5109. .dpcm_capture = 1,
  5110. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5111. SND_SOC_DPCM_TRIGGER_POST},
  5112. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5113. .ignore_suspend = 1,
  5114. /* this dailink has playback support */
  5115. .ignore_pmdown_time = 1,
  5116. .codec_dai_name = "snd-soc-dummy-dai",
  5117. .codec_name = "snd-soc-dummy",
  5118. },
  5119. {
  5120. .name = "MSM AFE-PCM RX",
  5121. .stream_name = "AFE-PROXY RX",
  5122. .cpu_dai_name = "msm-dai-q6-dev.241",
  5123. .codec_name = "msm-stub-codec.1",
  5124. .codec_dai_name = "msm-stub-rx",
  5125. .platform_name = "msm-pcm-afe",
  5126. .dpcm_playback = 1,
  5127. .ignore_suspend = 1,
  5128. /* this dainlink has playback support */
  5129. .ignore_pmdown_time = 1,
  5130. },
  5131. {
  5132. .name = "MSM AFE-PCM TX",
  5133. .stream_name = "AFE-PROXY TX",
  5134. .cpu_dai_name = "msm-dai-q6-dev.240",
  5135. .codec_name = "msm-stub-codec.1",
  5136. .codec_dai_name = "msm-stub-tx",
  5137. .platform_name = "msm-pcm-afe",
  5138. .dpcm_capture = 1,
  5139. .ignore_suspend = 1,
  5140. },
  5141. {
  5142. .name = MSM_DAILINK_NAME(Compress1),
  5143. .stream_name = "Compress1",
  5144. .cpu_dai_name = "MultiMedia4",
  5145. .platform_name = "msm-compress-dsp",
  5146. .dynamic = 1,
  5147. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5148. .dpcm_playback = 1,
  5149. .dpcm_capture = 1,
  5150. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5151. SND_SOC_DPCM_TRIGGER_POST},
  5152. .codec_dai_name = "snd-soc-dummy-dai",
  5153. .codec_name = "snd-soc-dummy",
  5154. .ignore_suspend = 1,
  5155. .ignore_pmdown_time = 1,
  5156. /* this dainlink has playback support */
  5157. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5158. },
  5159. {
  5160. .name = "AUXPCM Hostless",
  5161. .stream_name = "AUXPCM Hostless",
  5162. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5163. .platform_name = "msm-pcm-hostless",
  5164. .dynamic = 1,
  5165. .dpcm_playback = 1,
  5166. .dpcm_capture = 1,
  5167. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5168. SND_SOC_DPCM_TRIGGER_POST},
  5169. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5170. .ignore_suspend = 1,
  5171. /* this dainlink has playback support */
  5172. .ignore_pmdown_time = 1,
  5173. .codec_dai_name = "snd-soc-dummy-dai",
  5174. .codec_name = "snd-soc-dummy",
  5175. },
  5176. {
  5177. .name = "SLIMBUS_1 Hostless",
  5178. .stream_name = "SLIMBUS_1 Hostless",
  5179. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5180. .platform_name = "msm-pcm-hostless",
  5181. .dynamic = 1,
  5182. .dpcm_playback = 1,
  5183. .dpcm_capture = 1,
  5184. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5185. SND_SOC_DPCM_TRIGGER_POST},
  5186. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5187. .ignore_suspend = 1,
  5188. /* this dailink has playback support */
  5189. .ignore_pmdown_time = 1,
  5190. .codec_dai_name = "snd-soc-dummy-dai",
  5191. .codec_name = "snd-soc-dummy",
  5192. },
  5193. {
  5194. .name = "SLIMBUS_3 Hostless",
  5195. .stream_name = "SLIMBUS_3 Hostless",
  5196. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5197. .platform_name = "msm-pcm-hostless",
  5198. .dynamic = 1,
  5199. .dpcm_playback = 1,
  5200. .dpcm_capture = 1,
  5201. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5202. SND_SOC_DPCM_TRIGGER_POST},
  5203. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5204. .ignore_suspend = 1,
  5205. /* this dailink has playback support */
  5206. .ignore_pmdown_time = 1,
  5207. .codec_dai_name = "snd-soc-dummy-dai",
  5208. .codec_name = "snd-soc-dummy",
  5209. },
  5210. {
  5211. .name = "SLIMBUS_4 Hostless",
  5212. .stream_name = "SLIMBUS_4 Hostless",
  5213. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5214. .platform_name = "msm-pcm-hostless",
  5215. .dynamic = 1,
  5216. .dpcm_playback = 1,
  5217. .dpcm_capture = 1,
  5218. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5219. SND_SOC_DPCM_TRIGGER_POST},
  5220. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5221. .ignore_suspend = 1,
  5222. /* this dailink has playback support */
  5223. .ignore_pmdown_time = 1,
  5224. .codec_dai_name = "snd-soc-dummy-dai",
  5225. .codec_name = "snd-soc-dummy",
  5226. },
  5227. {
  5228. .name = MSM_DAILINK_NAME(LowLatency),
  5229. .stream_name = "MultiMedia5",
  5230. .cpu_dai_name = "MultiMedia5",
  5231. .platform_name = "msm-pcm-dsp.1",
  5232. .dynamic = 1,
  5233. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5234. .dpcm_playback = 1,
  5235. .dpcm_capture = 1,
  5236. .codec_dai_name = "snd-soc-dummy-dai",
  5237. .codec_name = "snd-soc-dummy",
  5238. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5239. SND_SOC_DPCM_TRIGGER_POST},
  5240. .ignore_suspend = 1,
  5241. /* this dainlink has playback support */
  5242. .ignore_pmdown_time = 1,
  5243. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5244. .ops = &msm_fe_qos_ops,
  5245. },
  5246. {
  5247. .name = "Listen 1 Audio Service",
  5248. .stream_name = "Listen 1 Audio Service",
  5249. .cpu_dai_name = "LSM1",
  5250. .platform_name = "msm-lsm-client",
  5251. .dynamic = 1,
  5252. .dpcm_capture = 1,
  5253. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5254. SND_SOC_DPCM_TRIGGER_POST },
  5255. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5256. .ignore_suspend = 1,
  5257. .codec_dai_name = "snd-soc-dummy-dai",
  5258. .codec_name = "snd-soc-dummy",
  5259. .id = MSM_FRONTEND_DAI_LSM1,
  5260. },
  5261. /* Multiple Tunnel instances */
  5262. {
  5263. .name = MSM_DAILINK_NAME(Compress2),
  5264. .stream_name = "Compress2",
  5265. .cpu_dai_name = "MultiMedia7",
  5266. .platform_name = "msm-compress-dsp",
  5267. .dynamic = 1,
  5268. .dpcm_playback = 1,
  5269. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5270. SND_SOC_DPCM_TRIGGER_POST},
  5271. .codec_dai_name = "snd-soc-dummy-dai",
  5272. .codec_name = "snd-soc-dummy",
  5273. .ignore_suspend = 1,
  5274. .ignore_pmdown_time = 1,
  5275. /* this dainlink has playback support */
  5276. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5277. },
  5278. {
  5279. .name = MSM_DAILINK_NAME(MultiMedia10),
  5280. .stream_name = "MultiMedia10",
  5281. .cpu_dai_name = "MultiMedia10",
  5282. .platform_name = "msm-pcm-dsp.1",
  5283. .dynamic = 1,
  5284. .dpcm_playback = 1,
  5285. .dpcm_capture = 1,
  5286. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5287. SND_SOC_DPCM_TRIGGER_POST},
  5288. .codec_dai_name = "snd-soc-dummy-dai",
  5289. .codec_name = "snd-soc-dummy",
  5290. .ignore_suspend = 1,
  5291. .ignore_pmdown_time = 1,
  5292. /* this dainlink has playback support */
  5293. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5294. },
  5295. {
  5296. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5297. .stream_name = "MM_NOIRQ",
  5298. .cpu_dai_name = "MultiMedia8",
  5299. .platform_name = "msm-pcm-dsp-noirq",
  5300. .dynamic = 1,
  5301. .dpcm_playback = 1,
  5302. .dpcm_capture = 1,
  5303. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5304. SND_SOC_DPCM_TRIGGER_POST},
  5305. .codec_dai_name = "snd-soc-dummy-dai",
  5306. .codec_name = "snd-soc-dummy",
  5307. .ignore_suspend = 1,
  5308. .ignore_pmdown_time = 1,
  5309. /* this dainlink has playback support */
  5310. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5311. .ops = &msm_fe_qos_ops,
  5312. },
  5313. /* HDMI Hostless */
  5314. {
  5315. .name = "HDMI_RX_HOSTLESS",
  5316. .stream_name = "HDMI_RX_HOSTLESS",
  5317. .cpu_dai_name = "HDMI_HOSTLESS",
  5318. .platform_name = "msm-pcm-hostless",
  5319. .dynamic = 1,
  5320. .dpcm_playback = 1,
  5321. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5322. SND_SOC_DPCM_TRIGGER_POST},
  5323. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5324. .ignore_suspend = 1,
  5325. .ignore_pmdown_time = 1,
  5326. .codec_dai_name = "snd-soc-dummy-dai",
  5327. .codec_name = "snd-soc-dummy",
  5328. },
  5329. {
  5330. .name = "VoiceMMode2",
  5331. .stream_name = "VoiceMMode2",
  5332. .cpu_dai_name = "VoiceMMode2",
  5333. .platform_name = "msm-pcm-voice",
  5334. .dynamic = 1,
  5335. .dpcm_playback = 1,
  5336. .dpcm_capture = 1,
  5337. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5338. SND_SOC_DPCM_TRIGGER_POST},
  5339. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5340. .ignore_suspend = 1,
  5341. .ignore_pmdown_time = 1,
  5342. .codec_dai_name = "snd-soc-dummy-dai",
  5343. .codec_name = "snd-soc-dummy",
  5344. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5345. },
  5346. /* LSM FE */
  5347. {
  5348. .name = "Listen 2 Audio Service",
  5349. .stream_name = "Listen 2 Audio Service",
  5350. .cpu_dai_name = "LSM2",
  5351. .platform_name = "msm-lsm-client",
  5352. .dynamic = 1,
  5353. .dpcm_capture = 1,
  5354. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5355. SND_SOC_DPCM_TRIGGER_POST },
  5356. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5357. .ignore_suspend = 1,
  5358. .codec_dai_name = "snd-soc-dummy-dai",
  5359. .codec_name = "snd-soc-dummy",
  5360. .id = MSM_FRONTEND_DAI_LSM2,
  5361. },
  5362. {
  5363. .name = "Listen 3 Audio Service",
  5364. .stream_name = "Listen 3 Audio Service",
  5365. .cpu_dai_name = "LSM3",
  5366. .platform_name = "msm-lsm-client",
  5367. .dynamic = 1,
  5368. .dpcm_capture = 1,
  5369. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5370. SND_SOC_DPCM_TRIGGER_POST },
  5371. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5372. .ignore_suspend = 1,
  5373. .codec_dai_name = "snd-soc-dummy-dai",
  5374. .codec_name = "snd-soc-dummy",
  5375. .id = MSM_FRONTEND_DAI_LSM3,
  5376. },
  5377. {
  5378. .name = "Listen 4 Audio Service",
  5379. .stream_name = "Listen 4 Audio Service",
  5380. .cpu_dai_name = "LSM4",
  5381. .platform_name = "msm-lsm-client",
  5382. .dynamic = 1,
  5383. .dpcm_capture = 1,
  5384. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5385. SND_SOC_DPCM_TRIGGER_POST },
  5386. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5387. .ignore_suspend = 1,
  5388. .codec_dai_name = "snd-soc-dummy-dai",
  5389. .codec_name = "snd-soc-dummy",
  5390. .id = MSM_FRONTEND_DAI_LSM4,
  5391. },
  5392. {
  5393. .name = "Listen 5 Audio Service",
  5394. .stream_name = "Listen 5 Audio Service",
  5395. .cpu_dai_name = "LSM5",
  5396. .platform_name = "msm-lsm-client",
  5397. .dynamic = 1,
  5398. .dpcm_capture = 1,
  5399. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5400. SND_SOC_DPCM_TRIGGER_POST },
  5401. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5402. .ignore_suspend = 1,
  5403. .codec_dai_name = "snd-soc-dummy-dai",
  5404. .codec_name = "snd-soc-dummy",
  5405. .id = MSM_FRONTEND_DAI_LSM5,
  5406. },
  5407. {
  5408. .name = "Listen 6 Audio Service",
  5409. .stream_name = "Listen 6 Audio Service",
  5410. .cpu_dai_name = "LSM6",
  5411. .platform_name = "msm-lsm-client",
  5412. .dynamic = 1,
  5413. .dpcm_capture = 1,
  5414. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5415. SND_SOC_DPCM_TRIGGER_POST },
  5416. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5417. .ignore_suspend = 1,
  5418. .codec_dai_name = "snd-soc-dummy-dai",
  5419. .codec_name = "snd-soc-dummy",
  5420. .id = MSM_FRONTEND_DAI_LSM6,
  5421. },
  5422. {
  5423. .name = "Listen 7 Audio Service",
  5424. .stream_name = "Listen 7 Audio Service",
  5425. .cpu_dai_name = "LSM7",
  5426. .platform_name = "msm-lsm-client",
  5427. .dynamic = 1,
  5428. .dpcm_capture = 1,
  5429. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5430. SND_SOC_DPCM_TRIGGER_POST },
  5431. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5432. .ignore_suspend = 1,
  5433. .codec_dai_name = "snd-soc-dummy-dai",
  5434. .codec_name = "snd-soc-dummy",
  5435. .id = MSM_FRONTEND_DAI_LSM7,
  5436. },
  5437. {
  5438. .name = "Listen 8 Audio Service",
  5439. .stream_name = "Listen 8 Audio Service",
  5440. .cpu_dai_name = "LSM8",
  5441. .platform_name = "msm-lsm-client",
  5442. .dynamic = 1,
  5443. .dpcm_capture = 1,
  5444. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5445. SND_SOC_DPCM_TRIGGER_POST },
  5446. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5447. .ignore_suspend = 1,
  5448. .codec_dai_name = "snd-soc-dummy-dai",
  5449. .codec_name = "snd-soc-dummy",
  5450. .id = MSM_FRONTEND_DAI_LSM8,
  5451. },
  5452. {
  5453. .name = MSM_DAILINK_NAME(Media9),
  5454. .stream_name = "MultiMedia9",
  5455. .cpu_dai_name = "MultiMedia9",
  5456. .platform_name = "msm-pcm-dsp.0",
  5457. .dynamic = 1,
  5458. .dpcm_playback = 1,
  5459. .dpcm_capture = 1,
  5460. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5461. SND_SOC_DPCM_TRIGGER_POST},
  5462. .codec_dai_name = "snd-soc-dummy-dai",
  5463. .codec_name = "snd-soc-dummy",
  5464. .ignore_suspend = 1,
  5465. /* this dainlink has playback support */
  5466. .ignore_pmdown_time = 1,
  5467. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5468. },
  5469. {
  5470. .name = MSM_DAILINK_NAME(Compress4),
  5471. .stream_name = "Compress4",
  5472. .cpu_dai_name = "MultiMedia11",
  5473. .platform_name = "msm-compress-dsp",
  5474. .dynamic = 1,
  5475. .dpcm_playback = 1,
  5476. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5477. SND_SOC_DPCM_TRIGGER_POST},
  5478. .codec_dai_name = "snd-soc-dummy-dai",
  5479. .codec_name = "snd-soc-dummy",
  5480. .ignore_suspend = 1,
  5481. .ignore_pmdown_time = 1,
  5482. /* this dainlink has playback support */
  5483. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5484. },
  5485. {
  5486. .name = MSM_DAILINK_NAME(Compress5),
  5487. .stream_name = "Compress5",
  5488. .cpu_dai_name = "MultiMedia12",
  5489. .platform_name = "msm-compress-dsp",
  5490. .dynamic = 1,
  5491. .dpcm_playback = 1,
  5492. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5493. SND_SOC_DPCM_TRIGGER_POST},
  5494. .codec_dai_name = "snd-soc-dummy-dai",
  5495. .codec_name = "snd-soc-dummy",
  5496. .ignore_suspend = 1,
  5497. .ignore_pmdown_time = 1,
  5498. /* this dainlink has playback support */
  5499. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5500. },
  5501. {
  5502. .name = MSM_DAILINK_NAME(Compress6),
  5503. .stream_name = "Compress6",
  5504. .cpu_dai_name = "MultiMedia13",
  5505. .platform_name = "msm-compress-dsp",
  5506. .dynamic = 1,
  5507. .dpcm_playback = 1,
  5508. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5509. SND_SOC_DPCM_TRIGGER_POST},
  5510. .codec_dai_name = "snd-soc-dummy-dai",
  5511. .codec_name = "snd-soc-dummy",
  5512. .ignore_suspend = 1,
  5513. .ignore_pmdown_time = 1,
  5514. /* this dainlink has playback support */
  5515. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5516. },
  5517. {
  5518. .name = MSM_DAILINK_NAME(Compress7),
  5519. .stream_name = "Compress7",
  5520. .cpu_dai_name = "MultiMedia14",
  5521. .platform_name = "msm-compress-dsp",
  5522. .dynamic = 1,
  5523. .dpcm_playback = 1,
  5524. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5525. SND_SOC_DPCM_TRIGGER_POST},
  5526. .codec_dai_name = "snd-soc-dummy-dai",
  5527. .codec_name = "snd-soc-dummy",
  5528. .ignore_suspend = 1,
  5529. .ignore_pmdown_time = 1,
  5530. /* this dainlink has playback support */
  5531. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5532. },
  5533. {
  5534. .name = MSM_DAILINK_NAME(Compress8),
  5535. .stream_name = "Compress8",
  5536. .cpu_dai_name = "MultiMedia15",
  5537. .platform_name = "msm-compress-dsp",
  5538. .dynamic = 1,
  5539. .dpcm_playback = 1,
  5540. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5541. SND_SOC_DPCM_TRIGGER_POST},
  5542. .codec_dai_name = "snd-soc-dummy-dai",
  5543. .codec_name = "snd-soc-dummy",
  5544. .ignore_suspend = 1,
  5545. .ignore_pmdown_time = 1,
  5546. /* this dainlink has playback support */
  5547. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5548. },
  5549. {
  5550. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5551. .stream_name = "MM_NOIRQ_2",
  5552. .cpu_dai_name = "MultiMedia16",
  5553. .platform_name = "msm-pcm-dsp-noirq",
  5554. .dynamic = 1,
  5555. .dpcm_playback = 1,
  5556. .dpcm_capture = 1,
  5557. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5558. SND_SOC_DPCM_TRIGGER_POST},
  5559. .codec_dai_name = "snd-soc-dummy-dai",
  5560. .codec_name = "snd-soc-dummy",
  5561. .ignore_suspend = 1,
  5562. .ignore_pmdown_time = 1,
  5563. /* this dainlink has playback support */
  5564. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5565. },
  5566. {
  5567. .name = "SLIMBUS_8 Hostless",
  5568. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5569. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5570. .platform_name = "msm-pcm-hostless",
  5571. .dynamic = 1,
  5572. .dpcm_capture = 1,
  5573. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5574. SND_SOC_DPCM_TRIGGER_POST},
  5575. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5576. .ignore_suspend = 1,
  5577. .codec_dai_name = "snd-soc-dummy-dai",
  5578. .codec_name = "snd-soc-dummy",
  5579. },
  5580. /* Hostless PCM purpose */
  5581. {
  5582. .name = "CDC_DMA Hostless",
  5583. .stream_name = "CDC_DMA Hostless",
  5584. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5585. .platform_name = "msm-pcm-hostless",
  5586. .dynamic = 1,
  5587. .dpcm_playback = 1,
  5588. .dpcm_capture = 1,
  5589. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5590. SND_SOC_DPCM_TRIGGER_POST},
  5591. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5592. .ignore_suspend = 1,
  5593. /* this dailink has playback support */
  5594. .ignore_pmdown_time = 1,
  5595. .codec_dai_name = "snd-soc-dummy-dai",
  5596. .codec_name = "snd-soc-dummy",
  5597. },
  5598. };
  5599. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5600. {
  5601. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5602. .stream_name = "WSA CDC DMA0 Capture",
  5603. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5604. .platform_name = "msm-pcm-hostless",
  5605. .codec_name = "bolero_codec",
  5606. .codec_dai_name = "wsa_macro_vifeedback",
  5607. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5608. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5609. .ignore_suspend = 1,
  5610. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5611. .ops = &msm_cdc_dma_be_ops,
  5612. },
  5613. };
  5614. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5615. {
  5616. .name = MSM_DAILINK_NAME(ASM Loopback),
  5617. .stream_name = "MultiMedia6",
  5618. .cpu_dai_name = "MultiMedia6",
  5619. .platform_name = "msm-pcm-loopback",
  5620. .dynamic = 1,
  5621. .dpcm_playback = 1,
  5622. .dpcm_capture = 1,
  5623. .codec_dai_name = "snd-soc-dummy-dai",
  5624. .codec_name = "snd-soc-dummy",
  5625. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5626. SND_SOC_DPCM_TRIGGER_POST},
  5627. .ignore_suspend = 1,
  5628. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5629. .ignore_pmdown_time = 1,
  5630. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5631. },
  5632. {
  5633. .name = "USB Audio Hostless",
  5634. .stream_name = "USB Audio Hostless",
  5635. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5636. .platform_name = "msm-pcm-hostless",
  5637. .dynamic = 1,
  5638. .dpcm_playback = 1,
  5639. .dpcm_capture = 1,
  5640. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5641. SND_SOC_DPCM_TRIGGER_POST},
  5642. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5643. .ignore_suspend = 1,
  5644. .ignore_pmdown_time = 1,
  5645. .codec_dai_name = "snd-soc-dummy-dai",
  5646. .codec_name = "snd-soc-dummy",
  5647. },
  5648. {
  5649. .name = "SLIMBUS_7 Hostless",
  5650. .stream_name = "SLIMBUS_7 Hostless",
  5651. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5652. .platform_name = "msm-pcm-hostless",
  5653. .dynamic = 1,
  5654. .dpcm_capture = 1,
  5655. .dpcm_playback = 1,
  5656. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5657. SND_SOC_DPCM_TRIGGER_POST},
  5658. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5659. .ignore_suspend = 1,
  5660. .ignore_pmdown_time = 1,
  5661. .codec_dai_name = "snd-soc-dummy-dai",
  5662. .codec_name = "snd-soc-dummy",
  5663. },
  5664. {
  5665. .name = MSM_DAILINK_NAME(Compr Capture),
  5666. .stream_name = "Compr Capture",
  5667. .cpu_dai_name = "MultiMedia18",
  5668. .platform_name = "msm-compress-dsp",
  5669. .dynamic = 1,
  5670. .dpcm_capture = 1,
  5671. .codec_dai_name = "snd-soc-dummy-dai",
  5672. .codec_name = "snd-soc-dummy",
  5673. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5674. SND_SOC_DPCM_TRIGGER_POST},
  5675. .ignore_pmdown_time = 1,
  5676. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5677. },
  5678. };
  5679. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5680. /* Backend AFE DAI Links */
  5681. {
  5682. .name = LPASS_BE_AFE_PCM_RX,
  5683. .stream_name = "AFE Playback",
  5684. .cpu_dai_name = "msm-dai-q6-dev.224",
  5685. .platform_name = "msm-pcm-routing",
  5686. .codec_name = "msm-stub-codec.1",
  5687. .codec_dai_name = "msm-stub-rx",
  5688. .no_pcm = 1,
  5689. .dpcm_playback = 1,
  5690. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5691. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5692. /* this dainlink has playback support */
  5693. .ignore_pmdown_time = 1,
  5694. .ignore_suspend = 1,
  5695. },
  5696. {
  5697. .name = LPASS_BE_AFE_PCM_TX,
  5698. .stream_name = "AFE Capture",
  5699. .cpu_dai_name = "msm-dai-q6-dev.225",
  5700. .platform_name = "msm-pcm-routing",
  5701. .codec_name = "msm-stub-codec.1",
  5702. .codec_dai_name = "msm-stub-tx",
  5703. .no_pcm = 1,
  5704. .dpcm_capture = 1,
  5705. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5706. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5707. .ignore_suspend = 1,
  5708. },
  5709. /* Incall Record Uplink BACK END DAI Link */
  5710. {
  5711. .name = LPASS_BE_INCALL_RECORD_TX,
  5712. .stream_name = "Voice Uplink Capture",
  5713. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5714. .platform_name = "msm-pcm-routing",
  5715. .codec_name = "msm-stub-codec.1",
  5716. .codec_dai_name = "msm-stub-tx",
  5717. .no_pcm = 1,
  5718. .dpcm_capture = 1,
  5719. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5720. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5721. .ignore_suspend = 1,
  5722. },
  5723. /* Incall Record Downlink BACK END DAI Link */
  5724. {
  5725. .name = LPASS_BE_INCALL_RECORD_RX,
  5726. .stream_name = "Voice Downlink Capture",
  5727. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5728. .platform_name = "msm-pcm-routing",
  5729. .codec_name = "msm-stub-codec.1",
  5730. .codec_dai_name = "msm-stub-tx",
  5731. .no_pcm = 1,
  5732. .dpcm_capture = 1,
  5733. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5734. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5735. .ignore_suspend = 1,
  5736. },
  5737. /* Incall Music BACK END DAI Link */
  5738. {
  5739. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5740. .stream_name = "Voice Farend Playback",
  5741. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5742. .platform_name = "msm-pcm-routing",
  5743. .codec_name = "msm-stub-codec.1",
  5744. .codec_dai_name = "msm-stub-rx",
  5745. .no_pcm = 1,
  5746. .dpcm_playback = 1,
  5747. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5748. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5749. .ignore_suspend = 1,
  5750. .ignore_pmdown_time = 1,
  5751. },
  5752. /* Incall Music 2 BACK END DAI Link */
  5753. {
  5754. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5755. .stream_name = "Voice2 Farend Playback",
  5756. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5757. .platform_name = "msm-pcm-routing",
  5758. .codec_name = "msm-stub-codec.1",
  5759. .codec_dai_name = "msm-stub-rx",
  5760. .no_pcm = 1,
  5761. .dpcm_playback = 1,
  5762. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5763. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5764. .ignore_suspend = 1,
  5765. .ignore_pmdown_time = 1,
  5766. },
  5767. {
  5768. .name = LPASS_BE_USB_AUDIO_RX,
  5769. .stream_name = "USB Audio Playback",
  5770. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5771. .platform_name = "msm-pcm-routing",
  5772. .codec_name = "msm-stub-codec.1",
  5773. .codec_dai_name = "msm-stub-rx",
  5774. .no_pcm = 1,
  5775. .dpcm_playback = 1,
  5776. .id = MSM_BACKEND_DAI_USB_RX,
  5777. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5778. .ignore_pmdown_time = 1,
  5779. .ignore_suspend = 1,
  5780. },
  5781. {
  5782. .name = LPASS_BE_USB_AUDIO_TX,
  5783. .stream_name = "USB Audio Capture",
  5784. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5785. .platform_name = "msm-pcm-routing",
  5786. .codec_name = "msm-stub-codec.1",
  5787. .codec_dai_name = "msm-stub-tx",
  5788. .no_pcm = 1,
  5789. .dpcm_capture = 1,
  5790. .id = MSM_BACKEND_DAI_USB_TX,
  5791. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5792. .ignore_suspend = 1,
  5793. },
  5794. {
  5795. .name = LPASS_BE_PRI_TDM_RX_0,
  5796. .stream_name = "Primary TDM0 Playback",
  5797. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5798. .platform_name = "msm-pcm-routing",
  5799. .codec_name = "msm-stub-codec.1",
  5800. .codec_dai_name = "msm-stub-rx",
  5801. .no_pcm = 1,
  5802. .dpcm_playback = 1,
  5803. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5804. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5805. .ops = &qcs405_tdm_be_ops,
  5806. .ignore_suspend = 1,
  5807. .ignore_pmdown_time = 1,
  5808. },
  5809. {
  5810. .name = LPASS_BE_PRI_TDM_TX_0,
  5811. .stream_name = "Primary TDM0 Capture",
  5812. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5813. .platform_name = "msm-pcm-routing",
  5814. .codec_name = "msm-stub-codec.1",
  5815. .codec_dai_name = "msm-stub-tx",
  5816. .no_pcm = 1,
  5817. .dpcm_capture = 1,
  5818. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5819. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5820. .ops = &qcs405_tdm_be_ops,
  5821. .ignore_suspend = 1,
  5822. },
  5823. {
  5824. .name = LPASS_BE_SEC_TDM_RX_0,
  5825. .stream_name = "Secondary TDM0 Playback",
  5826. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5827. .platform_name = "msm-pcm-routing",
  5828. .codec_name = "msm-stub-codec.1",
  5829. .codec_dai_name = "msm-stub-rx",
  5830. .no_pcm = 1,
  5831. .dpcm_playback = 1,
  5832. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5833. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5834. .ops = &qcs405_tdm_be_ops,
  5835. .ignore_suspend = 1,
  5836. .ignore_pmdown_time = 1,
  5837. },
  5838. {
  5839. .name = LPASS_BE_SEC_TDM_TX_0,
  5840. .stream_name = "Secondary TDM0 Capture",
  5841. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5842. .platform_name = "msm-pcm-routing",
  5843. .codec_name = "msm-stub-codec.1",
  5844. .codec_dai_name = "msm-stub-tx",
  5845. .no_pcm = 1,
  5846. .dpcm_capture = 1,
  5847. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5848. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5849. .ops = &qcs405_tdm_be_ops,
  5850. .ignore_suspend = 1,
  5851. },
  5852. {
  5853. .name = LPASS_BE_TERT_TDM_RX_0,
  5854. .stream_name = "Tertiary TDM0 Playback",
  5855. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5856. .platform_name = "msm-pcm-routing",
  5857. .codec_name = "msm-stub-codec.1",
  5858. .codec_dai_name = "msm-stub-rx",
  5859. .no_pcm = 1,
  5860. .dpcm_playback = 1,
  5861. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5862. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5863. .ops = &qcs405_tdm_be_ops,
  5864. .ignore_suspend = 1,
  5865. .ignore_pmdown_time = 1,
  5866. },
  5867. {
  5868. .name = LPASS_BE_TERT_TDM_TX_0,
  5869. .stream_name = "Tertiary TDM0 Capture",
  5870. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5871. .platform_name = "msm-pcm-routing",
  5872. .codec_name = "msm-stub-codec.1",
  5873. .codec_dai_name = "msm-stub-tx",
  5874. .no_pcm = 1,
  5875. .dpcm_capture = 1,
  5876. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5877. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5878. .ops = &qcs405_tdm_be_ops,
  5879. .ignore_suspend = 1,
  5880. },
  5881. {
  5882. .name = LPASS_BE_QUAT_TDM_RX_0,
  5883. .stream_name = "Quaternary TDM0 Playback",
  5884. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5885. .platform_name = "msm-pcm-routing",
  5886. .codec_name = "msm-stub-codec.1",
  5887. .codec_dai_name = "msm-stub-rx",
  5888. .no_pcm = 1,
  5889. .dpcm_playback = 1,
  5890. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5891. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5892. .ops = &qcs405_tdm_be_ops,
  5893. .ignore_suspend = 1,
  5894. .ignore_pmdown_time = 1,
  5895. },
  5896. {
  5897. .name = LPASS_BE_QUAT_TDM_TX_0,
  5898. .stream_name = "Quaternary TDM0 Capture",
  5899. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5900. .platform_name = "msm-pcm-routing",
  5901. .codec_name = "msm-stub-codec.1",
  5902. .codec_dai_name = "msm-stub-tx",
  5903. .no_pcm = 1,
  5904. .dpcm_capture = 1,
  5905. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5906. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5907. .ops = &qcs405_tdm_be_ops,
  5908. .ignore_suspend = 1,
  5909. },
  5910. {
  5911. .name = LPASS_BE_QUIN_TDM_RX_0,
  5912. .stream_name = "Quinary TDM0 Playback",
  5913. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5914. .platform_name = "msm-pcm-routing",
  5915. .codec_name = "msm-stub-codec.1",
  5916. .codec_dai_name = "msm-stub-rx",
  5917. .no_pcm = 1,
  5918. .dpcm_playback = 1,
  5919. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5920. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5921. .ops = &qcs405_tdm_be_ops,
  5922. .ignore_suspend = 1,
  5923. .ignore_pmdown_time = 1,
  5924. },
  5925. {
  5926. .name = LPASS_BE_QUIN_TDM_TX_0,
  5927. .stream_name = "Quinary TDM0 Capture",
  5928. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5929. .platform_name = "msm-pcm-routing",
  5930. .codec_name = "msm-stub-codec.1",
  5931. .codec_dai_name = "msm-stub-tx",
  5932. .no_pcm = 1,
  5933. .dpcm_capture = 1,
  5934. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5935. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5936. .ops = &qcs405_tdm_be_ops,
  5937. .ignore_suspend = 1,
  5938. },
  5939. };
  5940. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5941. {
  5942. .name = LPASS_BE_SLIMBUS_0_RX,
  5943. .stream_name = "Slimbus Playback",
  5944. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5945. .platform_name = "msm-pcm-routing",
  5946. .codec_name = "tasha_codec",
  5947. .codec_dai_name = "tasha_mix_rx1",
  5948. .no_pcm = 1,
  5949. .dpcm_playback = 1,
  5950. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5951. .init = &msm_audrx_init,
  5952. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5953. /* this dainlink has playback support */
  5954. .ignore_pmdown_time = 1,
  5955. .ignore_suspend = 1,
  5956. .ops = &msm_be_ops,
  5957. },
  5958. {
  5959. .name = LPASS_BE_SLIMBUS_0_TX,
  5960. .stream_name = "Slimbus Capture",
  5961. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5962. .platform_name = "msm-pcm-routing",
  5963. .codec_name = "tasha_codec",
  5964. .codec_dai_name = "tasha_tx1",
  5965. .no_pcm = 1,
  5966. .dpcm_capture = 1,
  5967. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5968. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5969. .ignore_suspend = 1,
  5970. .ops = &msm_be_ops,
  5971. },
  5972. {
  5973. .name = LPASS_BE_SLIMBUS_1_RX,
  5974. .stream_name = "Slimbus1 Playback",
  5975. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5976. .platform_name = "msm-pcm-routing",
  5977. .codec_name = "tasha_codec",
  5978. .codec_dai_name = "tasha_mix_rx1",
  5979. .no_pcm = 1,
  5980. .dpcm_playback = 1,
  5981. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5982. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5983. .ops = &msm_be_ops,
  5984. /* dai link has playback support */
  5985. .ignore_pmdown_time = 1,
  5986. .ignore_suspend = 1,
  5987. },
  5988. {
  5989. .name = LPASS_BE_SLIMBUS_1_TX,
  5990. .stream_name = "Slimbus1 Capture",
  5991. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5992. .platform_name = "msm-pcm-routing",
  5993. .codec_name = "tasha_codec",
  5994. .codec_dai_name = "tasha_tx3",
  5995. .no_pcm = 1,
  5996. .dpcm_capture = 1,
  5997. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5998. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5999. .ops = &msm_be_ops,
  6000. .ignore_suspend = 1,
  6001. },
  6002. {
  6003. .name = LPASS_BE_SLIMBUS_2_RX,
  6004. .stream_name = "Slimbus2 Playback",
  6005. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6006. .platform_name = "msm-pcm-routing",
  6007. .codec_name = "tasha_codec",
  6008. .codec_dai_name = "tasha_rx2",
  6009. .no_pcm = 1,
  6010. .dpcm_playback = 1,
  6011. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6012. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6013. .ops = &msm_be_ops,
  6014. .ignore_pmdown_time = 1,
  6015. .ignore_suspend = 1,
  6016. },
  6017. {
  6018. .name = LPASS_BE_SLIMBUS_3_RX,
  6019. .stream_name = "Slimbus3 Playback",
  6020. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6021. .platform_name = "msm-pcm-routing",
  6022. .codec_name = "tasha_codec",
  6023. .codec_dai_name = "tasha_mix_rx1",
  6024. .no_pcm = 1,
  6025. .dpcm_playback = 1,
  6026. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6027. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6028. .ops = &msm_be_ops,
  6029. /* dai link has playback support */
  6030. .ignore_pmdown_time = 1,
  6031. .ignore_suspend = 1,
  6032. },
  6033. {
  6034. .name = LPASS_BE_SLIMBUS_3_TX,
  6035. .stream_name = "Slimbus3 Capture",
  6036. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6037. .platform_name = "msm-pcm-routing",
  6038. .codec_name = "tasha_codec",
  6039. .codec_dai_name = "tasha_tx1",
  6040. .no_pcm = 1,
  6041. .dpcm_capture = 1,
  6042. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6043. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6044. .ops = &msm_be_ops,
  6045. .ignore_suspend = 1,
  6046. },
  6047. {
  6048. .name = LPASS_BE_SLIMBUS_4_RX,
  6049. .stream_name = "Slimbus4 Playback",
  6050. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6051. .platform_name = "msm-pcm-routing",
  6052. .codec_name = "tasha_codec",
  6053. .codec_dai_name = "tasha_mix_rx1",
  6054. .no_pcm = 1,
  6055. .dpcm_playback = 1,
  6056. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6057. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6058. .ops = &msm_be_ops,
  6059. /* dai link has playback support */
  6060. .ignore_pmdown_time = 1,
  6061. .ignore_suspend = 1,
  6062. },
  6063. {
  6064. .name = LPASS_BE_SLIMBUS_5_RX,
  6065. .stream_name = "Slimbus5 Playback",
  6066. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6067. .platform_name = "msm-pcm-routing",
  6068. .codec_name = "tasha_codec",
  6069. .codec_dai_name = "tasha_rx3",
  6070. .no_pcm = 1,
  6071. .dpcm_playback = 1,
  6072. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6073. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6074. .ops = &msm_be_ops,
  6075. /* dai link has playback support */
  6076. .ignore_pmdown_time = 1,
  6077. .ignore_suspend = 1,
  6078. },
  6079. {
  6080. .name = LPASS_BE_SLIMBUS_6_RX,
  6081. .stream_name = "Slimbus6 Playback",
  6082. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6083. .platform_name = "msm-pcm-routing",
  6084. .codec_name = "tasha_codec",
  6085. .codec_dai_name = "tasha_rx4",
  6086. .no_pcm = 1,
  6087. .dpcm_playback = 1,
  6088. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6089. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6090. .ops = &msm_be_ops,
  6091. /* dai link has playback support */
  6092. .ignore_pmdown_time = 1,
  6093. .ignore_suspend = 1,
  6094. },
  6095. /* Slimbus VI Recording */
  6096. {
  6097. .name = LPASS_BE_SLIMBUS_TX_VI,
  6098. .stream_name = "Slimbus4 Capture",
  6099. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6100. .platform_name = "msm-pcm-routing",
  6101. .codec_name = "tasha_codec",
  6102. .codec_dai_name = "tasha_vifeedback",
  6103. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6104. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6105. .ops = &msm_be_ops,
  6106. .ignore_suspend = 1,
  6107. .no_pcm = 1,
  6108. .dpcm_capture = 1,
  6109. .ignore_pmdown_time = 1,
  6110. },
  6111. };
  6112. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6113. {
  6114. .name = LPASS_BE_SLIMBUS_7_RX,
  6115. .stream_name = "Slimbus7 Playback",
  6116. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6117. .platform_name = "msm-pcm-routing",
  6118. .codec_name = "btfmslim_slave",
  6119. /* BT codec driver determines capabilities based on
  6120. * dai name, bt codecdai name should always contains
  6121. * supported usecase information
  6122. */
  6123. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6124. .no_pcm = 1,
  6125. .dpcm_playback = 1,
  6126. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6127. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6128. .ops = &msm_wcn_ops,
  6129. /* dai link has playback support */
  6130. .ignore_pmdown_time = 1,
  6131. .ignore_suspend = 1,
  6132. },
  6133. {
  6134. .name = LPASS_BE_SLIMBUS_7_TX,
  6135. .stream_name = "Slimbus7 Capture",
  6136. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6137. .platform_name = "msm-pcm-routing",
  6138. .codec_name = "btfmslim_slave",
  6139. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6140. .no_pcm = 1,
  6141. .dpcm_capture = 1,
  6142. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6143. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6144. .ops = &msm_wcn_ops,
  6145. .ignore_suspend = 1,
  6146. },
  6147. {
  6148. .name = LPASS_BE_SLIMBUS_8_TX,
  6149. .stream_name = "Slimbus8 Capture",
  6150. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6151. .platform_name = "msm-pcm-routing",
  6152. .codec_name = "btfmslim_slave",
  6153. .codec_dai_name = "btfm_fm_slim_tx",
  6154. .no_pcm = 1,
  6155. .dpcm_capture = 1,
  6156. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6157. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6158. .init = &msm_wcn_init,
  6159. .ops = &msm_wcn_ops,
  6160. .ignore_suspend = 1,
  6161. },
  6162. };
  6163. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6164. {
  6165. .name = LPASS_BE_PRI_MI2S_RX,
  6166. .stream_name = "Primary MI2S Playback",
  6167. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6168. .platform_name = "msm-pcm-routing",
  6169. .codec_name = "msm-stub-codec.1",
  6170. .codec_dai_name = "msm-stub-rx",
  6171. .no_pcm = 1,
  6172. .dpcm_playback = 1,
  6173. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6174. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6175. .ops = &msm_mi2s_be_ops,
  6176. .ignore_suspend = 1,
  6177. .ignore_pmdown_time = 1,
  6178. },
  6179. {
  6180. .name = LPASS_BE_PRI_MI2S_TX,
  6181. .stream_name = "Primary MI2S Capture",
  6182. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6183. .platform_name = "msm-pcm-routing",
  6184. .codec_name = "msm-stub-codec.1",
  6185. .codec_dai_name = "msm-stub-tx",
  6186. .no_pcm = 1,
  6187. .dpcm_capture = 1,
  6188. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6189. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6190. .ops = &msm_mi2s_be_ops,
  6191. .ignore_suspend = 1,
  6192. },
  6193. {
  6194. .name = LPASS_BE_SEC_MI2S_RX,
  6195. .stream_name = "Secondary MI2S Playback",
  6196. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6197. .platform_name = "msm-pcm-routing",
  6198. .codec_name = "msm-stub-codec.1",
  6199. .codec_dai_name = "msm-stub-rx",
  6200. .no_pcm = 1,
  6201. .dpcm_playback = 1,
  6202. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6203. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6204. .ops = &msm_mi2s_be_ops,
  6205. .ignore_suspend = 1,
  6206. .ignore_pmdown_time = 1,
  6207. },
  6208. {
  6209. .name = LPASS_BE_SEC_MI2S_TX,
  6210. .stream_name = "Secondary MI2S Capture",
  6211. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6212. .platform_name = "msm-pcm-routing",
  6213. .codec_name = "msm-stub-codec.1",
  6214. .codec_dai_name = "msm-stub-tx",
  6215. .no_pcm = 1,
  6216. .dpcm_capture = 1,
  6217. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6218. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6219. .ops = &msm_mi2s_be_ops,
  6220. .ignore_suspend = 1,
  6221. },
  6222. {
  6223. .name = LPASS_BE_TERT_MI2S_RX,
  6224. .stream_name = "Tertiary MI2S Playback",
  6225. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6226. .platform_name = "msm-pcm-routing",
  6227. .codec_name = "msm-stub-codec.1",
  6228. .codec_dai_name = "msm-stub-rx",
  6229. .no_pcm = 1,
  6230. .dpcm_playback = 1,
  6231. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6232. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6233. .ops = &msm_mi2s_be_ops,
  6234. .ignore_suspend = 1,
  6235. .ignore_pmdown_time = 1,
  6236. },
  6237. {
  6238. .name = LPASS_BE_TERT_MI2S_TX,
  6239. .stream_name = "Tertiary MI2S Capture",
  6240. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6241. .platform_name = "msm-pcm-routing",
  6242. .codec_name = "msm-stub-codec.1",
  6243. .codec_dai_name = "msm-stub-tx",
  6244. .no_pcm = 1,
  6245. .dpcm_capture = 1,
  6246. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6247. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6248. .ops = &msm_mi2s_be_ops,
  6249. .ignore_suspend = 1,
  6250. },
  6251. {
  6252. .name = LPASS_BE_QUAT_MI2S_RX,
  6253. .stream_name = "Quaternary MI2S Playback",
  6254. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6255. .platform_name = "msm-pcm-routing",
  6256. .codec_name = "msm-stub-codec.1",
  6257. .codec_dai_name = "msm-stub-rx",
  6258. .no_pcm = 1,
  6259. .dpcm_playback = 1,
  6260. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6261. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6262. .ops = &msm_mi2s_be_ops,
  6263. .ignore_suspend = 1,
  6264. .ignore_pmdown_time = 1,
  6265. },
  6266. {
  6267. .name = LPASS_BE_QUAT_MI2S_TX,
  6268. .stream_name = "Quaternary MI2S Capture",
  6269. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6270. .platform_name = "msm-pcm-routing",
  6271. .codec_name = "msm-stub-codec.1",
  6272. .codec_dai_name = "msm-stub-tx",
  6273. .no_pcm = 1,
  6274. .dpcm_capture = 1,
  6275. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6276. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6277. .ops = &msm_mi2s_be_ops,
  6278. .ignore_suspend = 1,
  6279. },
  6280. {
  6281. .name = LPASS_BE_QUIN_MI2S_RX,
  6282. .stream_name = "Quinary MI2S Playback",
  6283. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6284. .platform_name = "msm-pcm-routing",
  6285. .codec_name = "msm-stub-codec.1",
  6286. .codec_dai_name = "msm-stub-rx",
  6287. .no_pcm = 1,
  6288. .dpcm_playback = 1,
  6289. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6290. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6291. .ops = &msm_mi2s_be_ops,
  6292. .ignore_suspend = 1,
  6293. .ignore_pmdown_time = 1,
  6294. },
  6295. {
  6296. .name = LPASS_BE_QUIN_MI2S_TX,
  6297. .stream_name = "Quinary MI2S Capture",
  6298. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6299. .platform_name = "msm-pcm-routing",
  6300. .codec_name = "msm-stub-codec.1",
  6301. .codec_dai_name = "msm-stub-tx",
  6302. .no_pcm = 1,
  6303. .dpcm_capture = 1,
  6304. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6305. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6306. .ops = &msm_mi2s_be_ops,
  6307. .ignore_suspend = 1,
  6308. },
  6309. };
  6310. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6311. /* Primary AUX PCM Backend DAI Links */
  6312. {
  6313. .name = LPASS_BE_AUXPCM_RX,
  6314. .stream_name = "AUX PCM Playback",
  6315. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6316. .platform_name = "msm-pcm-routing",
  6317. .codec_name = "msm-stub-codec.1",
  6318. .codec_dai_name = "msm-stub-rx",
  6319. .no_pcm = 1,
  6320. .dpcm_playback = 1,
  6321. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6322. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6323. .ignore_pmdown_time = 1,
  6324. .ignore_suspend = 1,
  6325. },
  6326. {
  6327. .name = LPASS_BE_AUXPCM_TX,
  6328. .stream_name = "AUX PCM Capture",
  6329. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6330. .platform_name = "msm-pcm-routing",
  6331. .codec_name = "msm-stub-codec.1",
  6332. .codec_dai_name = "msm-stub-tx",
  6333. .no_pcm = 1,
  6334. .dpcm_capture = 1,
  6335. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6336. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6337. .ignore_suspend = 1,
  6338. },
  6339. /* Secondary AUX PCM Backend DAI Links */
  6340. {
  6341. .name = LPASS_BE_SEC_AUXPCM_RX,
  6342. .stream_name = "Sec AUX PCM Playback",
  6343. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6344. .platform_name = "msm-pcm-routing",
  6345. .codec_name = "msm-stub-codec.1",
  6346. .codec_dai_name = "msm-stub-rx",
  6347. .no_pcm = 1,
  6348. .dpcm_playback = 1,
  6349. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6350. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6351. .ignore_pmdown_time = 1,
  6352. .ignore_suspend = 1,
  6353. },
  6354. {
  6355. .name = LPASS_BE_SEC_AUXPCM_TX,
  6356. .stream_name = "Sec AUX PCM Capture",
  6357. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6358. .platform_name = "msm-pcm-routing",
  6359. .codec_name = "msm-stub-codec.1",
  6360. .codec_dai_name = "msm-stub-tx",
  6361. .no_pcm = 1,
  6362. .dpcm_capture = 1,
  6363. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6364. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6365. .ignore_suspend = 1,
  6366. },
  6367. /* Tertiary AUX PCM Backend DAI Links */
  6368. {
  6369. .name = LPASS_BE_TERT_AUXPCM_RX,
  6370. .stream_name = "Tert AUX PCM Playback",
  6371. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6372. .platform_name = "msm-pcm-routing",
  6373. .codec_name = "msm-stub-codec.1",
  6374. .codec_dai_name = "msm-stub-rx",
  6375. .no_pcm = 1,
  6376. .dpcm_playback = 1,
  6377. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6378. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6379. .ignore_suspend = 1,
  6380. },
  6381. {
  6382. .name = LPASS_BE_TERT_AUXPCM_TX,
  6383. .stream_name = "Tert AUX PCM Capture",
  6384. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6385. .platform_name = "msm-pcm-routing",
  6386. .codec_name = "msm-stub-codec.1",
  6387. .codec_dai_name = "msm-stub-tx",
  6388. .no_pcm = 1,
  6389. .dpcm_capture = 1,
  6390. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6391. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6392. .ignore_suspend = 1,
  6393. },
  6394. /* Quaternary AUX PCM Backend DAI Links */
  6395. {
  6396. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6397. .stream_name = "Quat AUX PCM Playback",
  6398. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6399. .platform_name = "msm-pcm-routing",
  6400. .codec_name = "msm-stub-codec.1",
  6401. .codec_dai_name = "msm-stub-rx",
  6402. .no_pcm = 1,
  6403. .dpcm_playback = 1,
  6404. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6405. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6406. .ignore_pmdown_time = 1,
  6407. .ignore_suspend = 1,
  6408. },
  6409. {
  6410. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6411. .stream_name = "Quat AUX PCM Capture",
  6412. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6413. .platform_name = "msm-pcm-routing",
  6414. .codec_name = "msm-stub-codec.1",
  6415. .codec_dai_name = "msm-stub-tx",
  6416. .no_pcm = 1,
  6417. .dpcm_capture = 1,
  6418. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6419. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6420. .ignore_suspend = 1,
  6421. },
  6422. /* Quinary AUX PCM Backend DAI Links */
  6423. {
  6424. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6425. .stream_name = "Quin AUX PCM Playback",
  6426. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6427. .platform_name = "msm-pcm-routing",
  6428. .codec_name = "msm-stub-codec.1",
  6429. .codec_dai_name = "msm-stub-rx",
  6430. .no_pcm = 1,
  6431. .dpcm_playback = 1,
  6432. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6433. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6434. .ignore_pmdown_time = 1,
  6435. .ignore_suspend = 1,
  6436. },
  6437. {
  6438. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6439. .stream_name = "Quin AUX PCM Capture",
  6440. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6441. .platform_name = "msm-pcm-routing",
  6442. .codec_name = "msm-stub-codec.1",
  6443. .codec_dai_name = "msm-stub-tx",
  6444. .no_pcm = 1,
  6445. .dpcm_capture = 1,
  6446. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6447. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6448. .ignore_suspend = 1,
  6449. },
  6450. };
  6451. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6452. /* WSA CDC DMA Backend DAI Links */
  6453. {
  6454. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6455. .stream_name = "WSA CDC DMA0 Playback",
  6456. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6457. .platform_name = "msm-pcm-routing",
  6458. .codec_name = "bolero_codec",
  6459. .codec_dai_name = "wsa_macro_rx1",
  6460. .no_pcm = 1,
  6461. .dpcm_playback = 1,
  6462. .init = &msm_wsa_cdc_dma_init,
  6463. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6464. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6465. .ignore_pmdown_time = 1,
  6466. .ignore_suspend = 1,
  6467. .ops = &msm_cdc_dma_be_ops,
  6468. },
  6469. {
  6470. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6471. .stream_name = "WSA CDC DMA1 Playback",
  6472. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6473. .platform_name = "msm-pcm-routing",
  6474. .codec_name = "bolero_codec",
  6475. .codec_dai_name = "wsa_macro_rx_mix",
  6476. .no_pcm = 1,
  6477. .dpcm_playback = 1,
  6478. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6479. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6480. .ignore_pmdown_time = 1,
  6481. .ignore_suspend = 1,
  6482. .ops = &msm_cdc_dma_be_ops,
  6483. },
  6484. {
  6485. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6486. .stream_name = "WSA CDC DMA1 Capture",
  6487. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6488. .platform_name = "msm-pcm-routing",
  6489. .codec_name = "bolero_codec",
  6490. .codec_dai_name = "wsa_macro_echo",
  6491. .no_pcm = 1,
  6492. .dpcm_capture = 1,
  6493. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6494. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6495. .ignore_suspend = 1,
  6496. .ops = &msm_cdc_dma_be_ops,
  6497. },
  6498. };
  6499. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6500. {
  6501. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6502. .stream_name = "VA CDC DMA0 Capture",
  6503. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6504. .platform_name = "msm-pcm-routing",
  6505. .codec_name = "bolero_codec",
  6506. .codec_dai_name = "va_macro_tx1",
  6507. .no_pcm = 1,
  6508. .dpcm_capture = 1,
  6509. .init = &msm_va_cdc_dma_init,
  6510. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6511. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6512. .ignore_suspend = 1,
  6513. .ops = &msm_cdc_dma_be_ops,
  6514. },
  6515. {
  6516. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6517. .stream_name = "VA CDC DMA1 Capture",
  6518. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6519. .platform_name = "msm-pcm-routing",
  6520. .codec_name = "bolero_codec",
  6521. .codec_dai_name = "va_macro_tx2",
  6522. .no_pcm = 1,
  6523. .dpcm_capture = 1,
  6524. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6525. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6526. .ignore_suspend = 1,
  6527. .ops = &msm_cdc_dma_be_ops,
  6528. },
  6529. };
  6530. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6531. {
  6532. .name = LPASS_BE_PRI_SPDIF_RX,
  6533. .stream_name = "Primary SPDIF Playback",
  6534. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6535. .platform_name = "msm-pcm-routing",
  6536. .codec_name = "msm-stub-codec.1",
  6537. .codec_dai_name = "msm-stub-rx",
  6538. .no_pcm = 1,
  6539. .dpcm_playback = 1,
  6540. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6541. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6542. .ops = &msm_spdif_be_ops,
  6543. .ignore_suspend = 1,
  6544. .ignore_pmdown_time = 1,
  6545. },
  6546. {
  6547. .name = LPASS_BE_PRI_SPDIF_TX,
  6548. .stream_name = "Primary SPDIF Capture",
  6549. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6550. .platform_name = "msm-pcm-routing",
  6551. .codec_name = "msm-stub-codec.1",
  6552. .codec_dai_name = "msm-stub-tx",
  6553. .no_pcm = 1,
  6554. .dpcm_capture = 1,
  6555. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6556. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6557. .ops = &msm_spdif_be_ops,
  6558. .ignore_suspend = 1,
  6559. },
  6560. {
  6561. .name = LPASS_BE_SEC_SPDIF_RX,
  6562. .stream_name = "Secondary SPDIF Playback",
  6563. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6564. .platform_name = "msm-pcm-routing",
  6565. .codec_name = "msm-stub-codec.1",
  6566. .codec_dai_name = "msm-stub-rx",
  6567. .no_pcm = 1,
  6568. .dpcm_playback = 1,
  6569. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6570. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6571. .ops = &msm_spdif_be_ops,
  6572. .ignore_suspend = 1,
  6573. .ignore_pmdown_time = 1,
  6574. },
  6575. {
  6576. .name = LPASS_BE_SEC_SPDIF_TX,
  6577. .stream_name = "Secondary SPDIF Capture",
  6578. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6579. .platform_name = "msm-pcm-routing",
  6580. .codec_name = "msm-stub-codec.1",
  6581. .codec_dai_name = "msm-stub-tx",
  6582. .no_pcm = 1,
  6583. .dpcm_capture = 1,
  6584. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6585. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6586. .ops = &msm_spdif_be_ops,
  6587. .ignore_suspend = 1,
  6588. },
  6589. };
  6590. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6591. ARRAY_SIZE(msm_common_dai_links) +
  6592. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6593. ARRAY_SIZE(msm_common_be_dai_links) +
  6594. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6595. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6596. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6597. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6598. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6599. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6600. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6601. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6602. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6603. {
  6604. int ret = 0;
  6605. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6606. &service_nb);
  6607. if (ret < 0)
  6608. pr_err("%s: Audio notifier register failed ret = %d\n",
  6609. __func__, ret);
  6610. return ret;
  6611. }
  6612. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6613. struct snd_ctl_elem_value *ucontrol)
  6614. {
  6615. int ret = 0;
  6616. int port_id;
  6617. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6618. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6619. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6620. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6621. (vad_enable < 0) || (vad_enable > 1) ||
  6622. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6623. pr_err("%s: Invalid arguments\n", __func__);
  6624. ret = -EINVAL;
  6625. goto done;
  6626. }
  6627. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6628. vad_enable, preroll_config, vad_intf);
  6629. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6630. if (ret) {
  6631. pr_err("%s: Invalid vad interface\n", __func__);
  6632. goto done;
  6633. }
  6634. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6635. done:
  6636. return ret;
  6637. }
  6638. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6639. {
  6640. int ret = 0;
  6641. uint32_t tasha_codec = 0;
  6642. ret = afe_cal_init_hwdep(card);
  6643. if (ret) {
  6644. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6645. ret = 0;
  6646. }
  6647. /* tasha late probe when it is present */
  6648. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6649. &tasha_codec);
  6650. if (ret) {
  6651. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6652. ret = 0;
  6653. } else {
  6654. if (tasha_codec) {
  6655. ret = msm_snd_card_tasha_late_probe(card);
  6656. if (ret)
  6657. dev_err(card->dev, "%s: tasha late probe err\n",
  6658. __func__);
  6659. }
  6660. }
  6661. return ret;
  6662. }
  6663. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6664. .name = "qcs405-snd-card",
  6665. .controls = msm_snd_controls,
  6666. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6667. .late_probe = msm_snd_card_codec_late_probe,
  6668. };
  6669. static int msm_populate_dai_link_component_of_node(
  6670. struct snd_soc_card *card)
  6671. {
  6672. int i, index, ret = 0;
  6673. struct device *cdev = card->dev;
  6674. struct snd_soc_dai_link *dai_link = card->dai_link;
  6675. struct device_node *np;
  6676. if (!cdev) {
  6677. pr_err("%s: Sound card device memory NULL\n", __func__);
  6678. return -ENODEV;
  6679. }
  6680. for (i = 0; i < card->num_links; i++) {
  6681. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6682. continue;
  6683. /* populate platform_of_node for snd card dai links */
  6684. if (dai_link[i].platform_name &&
  6685. !dai_link[i].platform_of_node) {
  6686. index = of_property_match_string(cdev->of_node,
  6687. "asoc-platform-names",
  6688. dai_link[i].platform_name);
  6689. if (index < 0) {
  6690. pr_err("%s: No match found for platform name: %s\n",
  6691. __func__, dai_link[i].platform_name);
  6692. ret = index;
  6693. goto err;
  6694. }
  6695. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6696. index);
  6697. if (!np) {
  6698. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6699. __func__, dai_link[i].platform_name,
  6700. index);
  6701. ret = -ENODEV;
  6702. goto err;
  6703. }
  6704. dai_link[i].platform_of_node = np;
  6705. dai_link[i].platform_name = NULL;
  6706. }
  6707. /* populate cpu_of_node for snd card dai links */
  6708. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6709. index = of_property_match_string(cdev->of_node,
  6710. "asoc-cpu-names",
  6711. dai_link[i].cpu_dai_name);
  6712. if (index >= 0) {
  6713. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6714. index);
  6715. if (!np) {
  6716. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6717. __func__,
  6718. dai_link[i].cpu_dai_name);
  6719. ret = -ENODEV;
  6720. goto err;
  6721. }
  6722. dai_link[i].cpu_of_node = np;
  6723. dai_link[i].cpu_dai_name = NULL;
  6724. }
  6725. }
  6726. /* populate codec_of_node for snd card dai links */
  6727. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6728. index = of_property_match_string(cdev->of_node,
  6729. "asoc-codec-names",
  6730. dai_link[i].codec_name);
  6731. if (index < 0)
  6732. continue;
  6733. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6734. index);
  6735. if (!np) {
  6736. pr_err("%s: retrieving phandle for codec %s failed\n",
  6737. __func__, dai_link[i].codec_name);
  6738. ret = -ENODEV;
  6739. goto err;
  6740. }
  6741. dai_link[i].codec_of_node = np;
  6742. dai_link[i].codec_name = NULL;
  6743. }
  6744. }
  6745. err:
  6746. return ret;
  6747. }
  6748. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6749. /* FrontEnd DAI Links */
  6750. {
  6751. .name = "MSMSTUB Media1",
  6752. .stream_name = "MultiMedia1",
  6753. .cpu_dai_name = "MultiMedia1",
  6754. .platform_name = "msm-pcm-dsp.0",
  6755. .dynamic = 1,
  6756. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6757. .dpcm_playback = 1,
  6758. .dpcm_capture = 1,
  6759. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6760. SND_SOC_DPCM_TRIGGER_POST},
  6761. .codec_dai_name = "snd-soc-dummy-dai",
  6762. .codec_name = "snd-soc-dummy",
  6763. .ignore_suspend = 1,
  6764. /* this dainlink has playback support */
  6765. .ignore_pmdown_time = 1,
  6766. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6767. },
  6768. };
  6769. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6770. /* Backend DAI Links */
  6771. {
  6772. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6773. .stream_name = "VA CDC DMA0 Capture",
  6774. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6775. .platform_name = "msm-pcm-routing",
  6776. .codec_name = "bolero_codec",
  6777. .codec_dai_name = "va_macro_tx1",
  6778. .no_pcm = 1,
  6779. .dpcm_capture = 1,
  6780. .init = &msm_va_cdc_dma_init,
  6781. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6782. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6783. .ignore_suspend = 1,
  6784. .ops = &msm_cdc_dma_be_ops,
  6785. },
  6786. {
  6787. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6788. .stream_name = "VA CDC DMA1 Capture",
  6789. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6790. .platform_name = "msm-pcm-routing",
  6791. .codec_name = "bolero_codec",
  6792. .codec_dai_name = "va_macro_tx2",
  6793. .no_pcm = 1,
  6794. .dpcm_capture = 1,
  6795. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6796. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6797. .ignore_suspend = 1,
  6798. .ops = &msm_cdc_dma_be_ops,
  6799. },
  6800. };
  6801. static struct snd_soc_dai_link msm_stub_dai_links[
  6802. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6803. ARRAY_SIZE(msm_stub_be_dai_links)];
  6804. struct snd_soc_card snd_soc_card_stub_msm = {
  6805. .name = "qcs405-stub-snd-card",
  6806. };
  6807. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6808. { .compatible = "qcom,qcs405-asoc-snd",
  6809. .data = "codec"},
  6810. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6811. .data = "stub_codec"},
  6812. {},
  6813. };
  6814. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6815. {
  6816. struct snd_soc_card *card = NULL;
  6817. struct snd_soc_dai_link *dailink;
  6818. int total_links = 0;
  6819. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6820. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6821. uint32_t spdif_audio_intf = 0;
  6822. const struct of_device_id *match;
  6823. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6824. int rc = 0;
  6825. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6826. if (!match) {
  6827. dev_err(dev, "%s: No DT match found for sound card\n",
  6828. __func__);
  6829. return NULL;
  6830. }
  6831. if (!strcmp(match->data, "codec")) {
  6832. card = &snd_soc_card_qcs405_msm;
  6833. memcpy(msm_qcs405_dai_links + total_links,
  6834. msm_common_dai_links,
  6835. sizeof(msm_common_dai_links));
  6836. total_links += ARRAY_SIZE(msm_common_dai_links);
  6837. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6838. &wsa_bolero_codec);
  6839. if (rc) {
  6840. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6841. __func__);
  6842. } else {
  6843. if (wsa_bolero_codec) {
  6844. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6845. __func__);
  6846. memcpy(msm_qcs405_dai_links + total_links,
  6847. msm_bolero_fe_dai_links,
  6848. sizeof(msm_bolero_fe_dai_links));
  6849. total_links +=
  6850. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6851. }
  6852. }
  6853. memcpy(msm_qcs405_dai_links + total_links,
  6854. msm_common_misc_fe_dai_links,
  6855. sizeof(msm_common_misc_fe_dai_links));
  6856. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6857. memcpy(msm_qcs405_dai_links + total_links,
  6858. msm_common_be_dai_links,
  6859. sizeof(msm_common_be_dai_links));
  6860. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6861. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6862. &tasha_codec);
  6863. if (rc) {
  6864. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6865. __func__);
  6866. } else {
  6867. if (tasha_codec) {
  6868. memcpy(msm_qcs405_dai_links + total_links,
  6869. msm_tasha_be_dai_links,
  6870. sizeof(msm_tasha_be_dai_links));
  6871. total_links +=
  6872. ARRAY_SIZE(msm_tasha_be_dai_links);
  6873. }
  6874. }
  6875. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6876. &va_bolero_codec);
  6877. if (rc) {
  6878. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6879. __func__);
  6880. } else {
  6881. if (va_bolero_codec) {
  6882. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6883. __func__);
  6884. memcpy(msm_qcs405_dai_links + total_links,
  6885. msm_va_cdc_dma_be_dai_links,
  6886. sizeof(msm_va_cdc_dma_be_dai_links));
  6887. total_links +=
  6888. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6889. }
  6890. }
  6891. if (wsa_bolero_codec) {
  6892. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6893. __func__);
  6894. memcpy(msm_qcs405_dai_links + total_links,
  6895. msm_wsa_cdc_dma_be_dai_links,
  6896. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6897. total_links +=
  6898. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6899. }
  6900. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6901. &mi2s_audio_intf);
  6902. if (rc) {
  6903. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6904. __func__);
  6905. } else {
  6906. if (mi2s_audio_intf) {
  6907. memcpy(msm_qcs405_dai_links + total_links,
  6908. msm_mi2s_be_dai_links,
  6909. sizeof(msm_mi2s_be_dai_links));
  6910. total_links +=
  6911. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6912. }
  6913. }
  6914. rc = of_property_read_u32(dev->of_node,
  6915. "qcom,auxpcm-audio-intf",
  6916. &auxpcm_audio_intf);
  6917. if (rc) {
  6918. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6919. __func__);
  6920. } else {
  6921. if (auxpcm_audio_intf) {
  6922. memcpy(msm_qcs405_dai_links + total_links,
  6923. msm_auxpcm_be_dai_links,
  6924. sizeof(msm_auxpcm_be_dai_links));
  6925. total_links +=
  6926. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6927. }
  6928. }
  6929. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  6930. &spdif_audio_intf);
  6931. if (rc) {
  6932. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  6933. __func__);
  6934. } else {
  6935. if (spdif_audio_intf) {
  6936. memcpy(msm_qcs405_dai_links + total_links,
  6937. msm_spdif_be_dai_links,
  6938. sizeof(msm_spdif_be_dai_links));
  6939. total_links +=
  6940. ARRAY_SIZE(msm_spdif_be_dai_links);
  6941. /* enable spdif coax pins */
  6942. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  6943. spdif_pin_ctl =
  6944. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  6945. iowrite32(0xc0, spdif_cfg);
  6946. iowrite32(0x2220, spdif_pin_ctl);
  6947. }
  6948. }
  6949. dailink = msm_qcs405_dai_links;
  6950. } else if (!strcmp(match->data, "stub_codec")) {
  6951. card = &snd_soc_card_stub_msm;
  6952. memcpy(msm_stub_dai_links + total_links,
  6953. msm_stub_fe_dai_links,
  6954. sizeof(msm_stub_fe_dai_links));
  6955. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6956. memcpy(msm_stub_dai_links + total_links,
  6957. msm_stub_be_dai_links,
  6958. sizeof(msm_stub_be_dai_links));
  6959. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6960. dailink = msm_stub_dai_links;
  6961. }
  6962. if (card) {
  6963. card->dai_link = dailink;
  6964. card->num_links = total_links;
  6965. }
  6966. return card;
  6967. }
  6968. static int msm_wsa881x_init(struct snd_soc_component *component)
  6969. {
  6970. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6971. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6972. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6973. SPKR_L_BOOST, SPKR_L_VI};
  6974. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6975. SPKR_R_BOOST, SPKR_R_VI};
  6976. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6977. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6978. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6979. struct msm_asoc_mach_data *pdata;
  6980. struct snd_soc_dapm_context *dapm;
  6981. int ret = 0;
  6982. if (!codec) {
  6983. pr_err("%s codec is NULL\n", __func__);
  6984. return -EINVAL;
  6985. }
  6986. dapm = snd_soc_codec_get_dapm(codec);
  6987. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6988. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6989. __func__, codec->component.name);
  6990. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6991. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6992. &ch_rate[0], &spkleft_port_types[0]);
  6993. if (dapm->component) {
  6994. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6995. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6996. }
  6997. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6998. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6999. __func__, codec->component.name);
  7000. wsa881x_set_channel_map(codec, &spkright_ports[0],
  7001. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7002. &ch_rate[0], &spkright_port_types[0]);
  7003. if (dapm->component) {
  7004. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7005. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7006. }
  7007. } else {
  7008. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  7009. codec->component.name);
  7010. ret = -EINVAL;
  7011. goto err;
  7012. }
  7013. pdata = snd_soc_card_get_drvdata(component->card);
  7014. if (pdata && pdata->codec_root)
  7015. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7016. codec);
  7017. err:
  7018. return ret;
  7019. }
  7020. static int msm_init_wsa_dev(struct platform_device *pdev,
  7021. struct snd_soc_card *card)
  7022. {
  7023. struct device_node *wsa_of_node;
  7024. u32 wsa_max_devs;
  7025. u32 wsa_dev_cnt;
  7026. int i;
  7027. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7028. const char *wsa_auxdev_name_prefix[1];
  7029. char *dev_name_str = NULL;
  7030. int found = 0;
  7031. int ret = 0;
  7032. /* Get maximum WSA device count for this platform */
  7033. ret = of_property_read_u32(pdev->dev.of_node,
  7034. "qcom,wsa-max-devs", &wsa_max_devs);
  7035. if (ret) {
  7036. dev_info(&pdev->dev,
  7037. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7038. __func__, pdev->dev.of_node->full_name, ret);
  7039. card->num_aux_devs = 0;
  7040. return 0;
  7041. }
  7042. if (wsa_max_devs == 0) {
  7043. dev_warn(&pdev->dev,
  7044. "%s: Max WSA devices is 0 for this target?\n",
  7045. __func__);
  7046. card->num_aux_devs = 0;
  7047. return 0;
  7048. }
  7049. /* Get count of WSA device phandles for this platform */
  7050. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7051. "qcom,wsa-devs", NULL);
  7052. if (wsa_dev_cnt == -ENOENT) {
  7053. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7054. __func__);
  7055. goto err;
  7056. } else if (wsa_dev_cnt <= 0) {
  7057. dev_err(&pdev->dev,
  7058. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7059. __func__, wsa_dev_cnt);
  7060. ret = -EINVAL;
  7061. goto err;
  7062. }
  7063. /*
  7064. * Expect total phandles count to be NOT less than maximum possible
  7065. * WSA count. However, if it is less, then assign same value to
  7066. * max count as well.
  7067. */
  7068. if (wsa_dev_cnt < wsa_max_devs) {
  7069. dev_dbg(&pdev->dev,
  7070. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7071. __func__, wsa_max_devs, wsa_dev_cnt);
  7072. wsa_max_devs = wsa_dev_cnt;
  7073. }
  7074. /* Make sure prefix string passed for each WSA device */
  7075. ret = of_property_count_strings(pdev->dev.of_node,
  7076. "qcom,wsa-aux-dev-prefix");
  7077. if (ret != wsa_dev_cnt) {
  7078. dev_err(&pdev->dev,
  7079. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7080. __func__, wsa_dev_cnt, ret);
  7081. ret = -EINVAL;
  7082. goto err;
  7083. }
  7084. /*
  7085. * Alloc mem to store phandle and index info of WSA device, if already
  7086. * registered with ALSA core
  7087. */
  7088. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7089. sizeof(struct msm_wsa881x_dev_info),
  7090. GFP_KERNEL);
  7091. if (!wsa881x_dev_info) {
  7092. ret = -ENOMEM;
  7093. goto err;
  7094. }
  7095. /*
  7096. * search and check whether all WSA devices are already
  7097. * registered with ALSA core or not. If found a node, store
  7098. * the node and the index in a local array of struct for later
  7099. * use.
  7100. */
  7101. for (i = 0; i < wsa_dev_cnt; i++) {
  7102. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7103. "qcom,wsa-devs", i);
  7104. if (unlikely(!wsa_of_node)) {
  7105. /* we should not be here */
  7106. dev_err(&pdev->dev,
  7107. "%s: wsa dev node is not present\n",
  7108. __func__);
  7109. ret = -EINVAL;
  7110. goto err_free_dev_info;
  7111. }
  7112. if (soc_find_component(wsa_of_node, NULL)) {
  7113. /* WSA device registered with ALSA core */
  7114. wsa881x_dev_info[found].of_node = wsa_of_node;
  7115. wsa881x_dev_info[found].index = i;
  7116. found++;
  7117. if (found == wsa_max_devs)
  7118. break;
  7119. }
  7120. }
  7121. if (found < wsa_max_devs) {
  7122. dev_err(&pdev->dev,
  7123. "%s: failed to find %d components. Found only %d\n",
  7124. __func__, wsa_max_devs, found);
  7125. return -EPROBE_DEFER;
  7126. }
  7127. dev_info(&pdev->dev,
  7128. "%s: found %d wsa881x devices registered with ALSA core\n",
  7129. __func__, found);
  7130. card->num_aux_devs = wsa_max_devs;
  7131. card->num_configs = wsa_max_devs;
  7132. /* Alloc array of AUX devs struct */
  7133. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7134. sizeof(struct snd_soc_aux_dev),
  7135. GFP_KERNEL);
  7136. if (!msm_aux_dev) {
  7137. ret = -ENOMEM;
  7138. goto err_free_dev_info;
  7139. }
  7140. /* Alloc array of codec conf struct */
  7141. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7142. sizeof(struct snd_soc_codec_conf),
  7143. GFP_KERNEL);
  7144. if (!msm_codec_conf) {
  7145. ret = -ENOMEM;
  7146. goto err_free_aux_dev;
  7147. }
  7148. for (i = 0; i < card->num_aux_devs; i++) {
  7149. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7150. GFP_KERNEL);
  7151. if (!dev_name_str) {
  7152. ret = -ENOMEM;
  7153. goto err_free_cdc_conf;
  7154. }
  7155. ret = of_property_read_string_index(pdev->dev.of_node,
  7156. "qcom,wsa-aux-dev-prefix",
  7157. wsa881x_dev_info[i].index,
  7158. wsa_auxdev_name_prefix);
  7159. if (ret) {
  7160. dev_err(&pdev->dev,
  7161. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7162. __func__, ret);
  7163. ret = -EINVAL;
  7164. goto err_free_dev_name_str;
  7165. }
  7166. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7167. msm_aux_dev[i].name = dev_name_str;
  7168. msm_aux_dev[i].codec_name = NULL;
  7169. msm_aux_dev[i].codec_of_node =
  7170. wsa881x_dev_info[i].of_node;
  7171. msm_aux_dev[i].init = msm_wsa881x_init;
  7172. msm_codec_conf[i].dev_name = NULL;
  7173. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7174. msm_codec_conf[i].of_node =
  7175. wsa881x_dev_info[i].of_node;
  7176. }
  7177. card->codec_conf = msm_codec_conf;
  7178. card->aux_dev = msm_aux_dev;
  7179. return 0;
  7180. err_free_dev_name_str:
  7181. devm_kfree(&pdev->dev, dev_name_str);
  7182. err_free_cdc_conf:
  7183. devm_kfree(&pdev->dev, msm_codec_conf);
  7184. err_free_aux_dev:
  7185. devm_kfree(&pdev->dev, msm_aux_dev);
  7186. err_free_dev_info:
  7187. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7188. err:
  7189. return ret;
  7190. }
  7191. static int msm_csra66x0_init(struct snd_soc_component *component)
  7192. {
  7193. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7194. if (!codec) {
  7195. pr_err("%s codec is NULL\n", __func__);
  7196. return -EINVAL;
  7197. }
  7198. return 0;
  7199. }
  7200. static int msm_init_csra_dev(struct platform_device *pdev,
  7201. struct snd_soc_card *card)
  7202. {
  7203. struct device_node *csra_of_node;
  7204. u32 csra_max_devs;
  7205. u32 csra_dev_cnt;
  7206. char *dev_name_str = NULL;
  7207. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7208. const char *csra_auxdev_name_prefix[1];
  7209. int i;
  7210. int found = 0;
  7211. int ret = 0;
  7212. /* Get maximum CSRA device count for this platform */
  7213. ret = of_property_read_u32(pdev->dev.of_node,
  7214. "qcom,csra-max-devs", &csra_max_devs);
  7215. if (ret) {
  7216. dev_info(&pdev->dev,
  7217. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7218. __func__, pdev->dev.of_node->full_name, ret);
  7219. card->num_aux_devs = 0;
  7220. return 0;
  7221. }
  7222. if (csra_max_devs == 0) {
  7223. dev_warn(&pdev->dev,
  7224. "%s: Max CSRA devices is 0 for this target?\n",
  7225. __func__);
  7226. return 0;
  7227. }
  7228. /* Get count of CSRA device phandles for this platform */
  7229. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7230. "qcom,csra-devs", NULL);
  7231. if (csra_dev_cnt == -ENOENT) {
  7232. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7233. __func__);
  7234. goto err;
  7235. } else if (csra_dev_cnt <= 0) {
  7236. dev_err(&pdev->dev,
  7237. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7238. __func__, csra_dev_cnt);
  7239. ret = -EINVAL;
  7240. goto err;
  7241. }
  7242. /*
  7243. * Expect total phandles count to be NOT less than maximum possible
  7244. * CSRA count. However, if it is less, then assign same value to
  7245. * max count as well.
  7246. */
  7247. if (csra_dev_cnt < csra_max_devs) {
  7248. dev_dbg(&pdev->dev,
  7249. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7250. __func__, csra_max_devs, csra_dev_cnt);
  7251. csra_max_devs = csra_dev_cnt;
  7252. }
  7253. /* Make sure prefix string passed for each CSRA device */
  7254. ret = of_property_count_strings(pdev->dev.of_node,
  7255. "qcom,csra-aux-dev-prefix");
  7256. if (ret != csra_dev_cnt) {
  7257. dev_err(&pdev->dev,
  7258. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7259. __func__, csra_dev_cnt, ret);
  7260. ret = -EINVAL;
  7261. goto err;
  7262. }
  7263. /*
  7264. * Alloc mem to store phandle and index info of CSRA device, if already
  7265. * registered with ALSA core
  7266. */
  7267. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7268. sizeof(struct msm_csra66x0_dev_info),
  7269. GFP_KERNEL);
  7270. if (!csra66x0_dev_info) {
  7271. ret = -ENOMEM;
  7272. goto err;
  7273. }
  7274. /*
  7275. * search and check whether all CSRA devices are already
  7276. * registered with ALSA core or not. If found a node, store
  7277. * the node and the index in a local array of struct for later
  7278. * use.
  7279. */
  7280. for (i = 0; i < csra_dev_cnt; i++) {
  7281. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7282. "qcom,csra-devs", i);
  7283. if (unlikely(!csra_of_node)) {
  7284. /* we should not be here */
  7285. dev_err(&pdev->dev,
  7286. "%s: csra dev node is not present\n",
  7287. __func__);
  7288. ret = -EINVAL;
  7289. goto err_free_dev_info;
  7290. }
  7291. if (soc_find_component(csra_of_node, NULL)) {
  7292. /* CSRA device registered with ALSA core */
  7293. csra66x0_dev_info[found].of_node = csra_of_node;
  7294. csra66x0_dev_info[found].index = i;
  7295. found++;
  7296. if (found == csra_max_devs)
  7297. break;
  7298. }
  7299. }
  7300. if (found < csra_max_devs) {
  7301. dev_dbg(&pdev->dev,
  7302. "%s: failed to find %d components. Found only %d\n",
  7303. __func__, csra_max_devs, found);
  7304. return -EPROBE_DEFER;
  7305. }
  7306. dev_info(&pdev->dev,
  7307. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7308. __func__, found);
  7309. card->num_aux_devs = csra_max_devs;
  7310. card->num_configs = csra_max_devs;
  7311. /* Alloc array of AUX devs struct */
  7312. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7313. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7314. if (!msm_aux_dev) {
  7315. ret = -ENOMEM;
  7316. goto err_free_dev_info;
  7317. }
  7318. /* Alloc array of codec conf struct */
  7319. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7320. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7321. if (!msm_codec_conf) {
  7322. ret = -ENOMEM;
  7323. goto err_free_aux_dev;
  7324. }
  7325. for (i = 0; i < card->num_aux_devs; i++) {
  7326. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7327. GFP_KERNEL);
  7328. if (!dev_name_str) {
  7329. ret = -ENOMEM;
  7330. goto err_free_cdc_conf;
  7331. }
  7332. ret = of_property_read_string_index(pdev->dev.of_node,
  7333. "qcom,csra-aux-dev-prefix",
  7334. csra66x0_dev_info[i].index,
  7335. csra_auxdev_name_prefix);
  7336. if (ret) {
  7337. dev_err(&pdev->dev,
  7338. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7339. __func__, ret);
  7340. ret = -EINVAL;
  7341. goto err_free_dev_name_str;
  7342. }
  7343. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7344. msm_aux_dev[i].name = dev_name_str;
  7345. msm_aux_dev[i].codec_name = NULL;
  7346. msm_aux_dev[i].codec_of_node =
  7347. csra66x0_dev_info[i].of_node;
  7348. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7349. msm_codec_conf[i].dev_name = NULL;
  7350. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7351. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7352. }
  7353. card->codec_conf = msm_codec_conf;
  7354. card->aux_dev = msm_aux_dev;
  7355. return 0;
  7356. err_free_dev_name_str:
  7357. devm_kfree(&pdev->dev, dev_name_str);
  7358. err_free_cdc_conf:
  7359. devm_kfree(&pdev->dev, msm_codec_conf);
  7360. err_free_aux_dev:
  7361. devm_kfree(&pdev->dev, msm_aux_dev);
  7362. err_free_dev_info:
  7363. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7364. err:
  7365. return ret;
  7366. }
  7367. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7368. {
  7369. int count;
  7370. u32 mi2s_master_slave[MI2S_MAX];
  7371. int ret;
  7372. for (count = 0; count < MI2S_MAX; count++) {
  7373. mutex_init(&mi2s_intf_conf[count].lock);
  7374. mi2s_intf_conf[count].ref_cnt = 0;
  7375. }
  7376. ret = of_property_read_u32_array(pdev->dev.of_node,
  7377. "qcom,msm-mi2s-master",
  7378. mi2s_master_slave, MI2S_MAX);
  7379. if (ret) {
  7380. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7381. __func__);
  7382. } else {
  7383. for (count = 0; count < MI2S_MAX; count++) {
  7384. mi2s_intf_conf[count].msm_is_mi2s_master =
  7385. mi2s_master_slave[count];
  7386. }
  7387. }
  7388. }
  7389. static void msm_i2s_auxpcm_deinit(void)
  7390. {
  7391. int count;
  7392. for (count = 0; count < MI2S_MAX; count++) {
  7393. mutex_destroy(&mi2s_intf_conf[count].lock);
  7394. mi2s_intf_conf[count].ref_cnt = 0;
  7395. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7396. }
  7397. }
  7398. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7399. uint32_t busnum, uint32_t addr)
  7400. {
  7401. struct i2c_adapter *adap;
  7402. u8 rbuf;
  7403. struct i2c_msg msg;
  7404. int status = 0;
  7405. adap = i2c_get_adapter(busnum);
  7406. if (!adap) {
  7407. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7408. __func__, busnum);
  7409. return -EBUSY;
  7410. }
  7411. /* to test presence, read one byte from device */
  7412. msg.addr = addr;
  7413. msg.flags = I2C_M_RD;
  7414. msg.len = 1;
  7415. msg.buf = &rbuf;
  7416. status = i2c_transfer(adap, &msg, 1);
  7417. i2c_put_adapter(adap);
  7418. if (status != 1) {
  7419. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7420. __func__, addr);
  7421. return -ENODEV;
  7422. }
  7423. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7424. __func__, addr);
  7425. return 0;
  7426. }
  7427. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7428. struct snd_soc_card *card)
  7429. {
  7430. int i;
  7431. uint32_t ep92_busnum = 0;
  7432. uint32_t ep92_reg = 0;
  7433. const char *ep92_name = NULL;
  7434. struct snd_soc_dai_link *dai;
  7435. int rc = 0;
  7436. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7437. &ep92_busnum);
  7438. if (rc) {
  7439. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7440. return 0;
  7441. }
  7442. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7443. &ep92_reg);
  7444. if (rc) {
  7445. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7446. return 0;
  7447. }
  7448. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7449. &ep92_name);
  7450. if (rc) {
  7451. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7452. return 0;
  7453. }
  7454. /* check I2C bus for connected ep92 chip */
  7455. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7456. /* check a second time after a short delay */
  7457. msleep(20);
  7458. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7459. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7460. __func__);
  7461. /* continue with snd_card registration without ep92 */
  7462. return 0;
  7463. }
  7464. }
  7465. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7466. /* update codec info in MI2S dai link */
  7467. dai = &msm_mi2s_be_dai_links[0];
  7468. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7469. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7470. dev_dbg(&pdev->dev,
  7471. "%s: Set Sec MI2S dai to ep92 codec\n",
  7472. __func__);
  7473. dai->codec_name = ep92_name;
  7474. dai->codec_dai_name = "ep92-hdmi";
  7475. break;
  7476. }
  7477. dai++;
  7478. }
  7479. /* update codec info in SPDIF dai link */
  7480. dai = &msm_spdif_be_dai_links[0];
  7481. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7482. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7483. dev_dbg(&pdev->dev,
  7484. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7485. __func__);
  7486. dai->codec_name = ep92_name;
  7487. dai->codec_dai_name = "ep92-arc";
  7488. break;
  7489. }
  7490. dai++;
  7491. }
  7492. return 0;
  7493. }
  7494. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7495. {
  7496. struct snd_soc_card *card;
  7497. struct msm_asoc_mach_data *pdata;
  7498. int ret;
  7499. u32 val;
  7500. if (!pdev->dev.of_node) {
  7501. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7502. return -EINVAL;
  7503. }
  7504. pdata = devm_kzalloc(&pdev->dev,
  7505. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7506. if (!pdata)
  7507. return -ENOMEM;
  7508. /* test for ep92 HDMI bridge and update dai links accordingly */
  7509. ret = msm_detect_ep92_dev(pdev, card);
  7510. if (ret)
  7511. goto err;
  7512. card = populate_snd_card_dailinks(&pdev->dev);
  7513. if (!card) {
  7514. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7515. ret = -EINVAL;
  7516. goto err;
  7517. }
  7518. card->dev = &pdev->dev;
  7519. platform_set_drvdata(pdev, card);
  7520. snd_soc_card_set_drvdata(card, pdata);
  7521. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7522. if (ret) {
  7523. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7524. ret);
  7525. goto err;
  7526. }
  7527. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7528. if (ret) {
  7529. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7530. ret);
  7531. goto err;
  7532. }
  7533. ret = msm_populate_dai_link_component_of_node(card);
  7534. if (ret) {
  7535. ret = -EPROBE_DEFER;
  7536. goto err;
  7537. }
  7538. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7539. if (ret) {
  7540. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7541. val = 0;
  7542. }
  7543. if (val) {
  7544. ret = msm_init_csra_dev(pdev, card);
  7545. if (ret)
  7546. goto err;
  7547. } else {
  7548. ret = msm_init_wsa_dev(pdev, card);
  7549. if (ret)
  7550. goto err;
  7551. }
  7552. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7553. "qcom,cdc-dmic01-gpios",
  7554. 0);
  7555. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7556. "qcom,cdc-dmic23-gpios",
  7557. 0);
  7558. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7559. "qcom,cdc-dmic45-gpios",
  7560. 0);
  7561. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7562. "qcom,cdc-dmic67-gpios",
  7563. 0);
  7564. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7565. if (ret == -EPROBE_DEFER) {
  7566. if (codec_reg_done)
  7567. ret = -EINVAL;
  7568. goto err;
  7569. } else if (ret) {
  7570. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7571. ret);
  7572. goto err;
  7573. }
  7574. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7575. spdev = pdev;
  7576. /* Parse pinctrl info from devicetree */
  7577. ret = msm_get_pinctrl(pdev);
  7578. if (!ret) {
  7579. pr_debug("%s: pinctrl parsing successful\n", __func__);
  7580. } else {
  7581. dev_dbg(&pdev->dev,
  7582. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  7583. __func__, ret);
  7584. ret = 0;
  7585. }
  7586. msm_i2s_auxpcm_init(pdev);
  7587. is_initial_boot = true;
  7588. return 0;
  7589. err:
  7590. msm_release_pinctrl(pdev);
  7591. return ret;
  7592. }
  7593. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7594. {
  7595. audio_notifier_deregister("qcs405");
  7596. msm_i2s_auxpcm_deinit();
  7597. msm_release_pinctrl(pdev);
  7598. return 0;
  7599. }
  7600. static struct platform_driver qcs405_asoc_machine_driver = {
  7601. .driver = {
  7602. .name = DRV_NAME,
  7603. .owner = THIS_MODULE,
  7604. .pm = &snd_soc_pm_ops,
  7605. .of_match_table = qcs405_asoc_machine_of_match,
  7606. },
  7607. .probe = msm_asoc_machine_probe,
  7608. .remove = msm_asoc_machine_remove,
  7609. };
  7610. module_platform_driver(qcs405_asoc_machine_driver);
  7611. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7612. MODULE_LICENSE("GPL v2");
  7613. MODULE_ALIAS("platform:" DRV_NAME);
  7614. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);