sde_plane.c 142 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include <drm/drm_blend.h>
  26. #include "msm_prop.h"
  27. #include "msm_drv.h"
  28. #include "sde_kms.h"
  29. #include "sde_fence.h"
  30. #include "sde_formats.h"
  31. #include "sde_hw_sspp.h"
  32. #include "sde_hw_catalog_format.h"
  33. #include "sde_trace.h"
  34. #include "sde_crtc.h"
  35. #include "sde_vbif.h"
  36. #include "sde_plane.h"
  37. #include "sde_color_processing.h"
  38. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  39. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  40. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  41. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  42. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  43. #define PHASE_STEP_SHIFT 21
  44. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  45. #define PHASE_RESIDUAL 15
  46. #define SHARP_STRENGTH_DEFAULT 32
  47. #define SHARP_EDGE_THR_DEFAULT 112
  48. #define SHARP_SMOOTH_THR_DEFAULT 8
  49. #define SHARP_NOISE_THR_DEFAULT 2
  50. #define SDE_NAME_SIZE 12
  51. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  52. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  53. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  54. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  55. /**
  56. * enum sde_plane_qos - Different qos configurations for each pipe
  57. *
  58. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  59. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  60. * this configuration is mutually exclusive from VBLANK_CTRL.
  61. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  62. */
  63. enum sde_plane_qos {
  64. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  65. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  66. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  67. };
  68. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  69. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  70. {
  71. struct msm_drm_private *priv;
  72. if (!plane || !plane->dev)
  73. return NULL;
  74. priv = plane->dev->dev_private;
  75. if (!priv)
  76. return NULL;
  77. return to_sde_kms(priv->kms);
  78. }
  79. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  80. {
  81. struct drm_plane_state *pstate = NULL;
  82. struct drm_crtc *drm_crtc = NULL;
  83. struct sde_crtc *sde_crtc = NULL;
  84. struct sde_crtc_mixer *mixer = NULL;
  85. struct sde_hw_ctl *ctl = NULL;
  86. if (!plane) {
  87. DRM_ERROR("Invalid plane %pK\n", plane);
  88. return NULL;
  89. }
  90. pstate = plane->state;
  91. if (!pstate) {
  92. DRM_ERROR("Invalid plane state %pK\n", pstate);
  93. return NULL;
  94. }
  95. drm_crtc = pstate->crtc;
  96. if (!drm_crtc) {
  97. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  98. return NULL;
  99. }
  100. sde_crtc = to_sde_crtc(drm_crtc);
  101. if (!sde_crtc) {
  102. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  103. return NULL;
  104. }
  105. /* it will always return the first mixer and single CTL */
  106. mixer = sde_crtc->mixers;
  107. if (!mixer) {
  108. DRM_ERROR("invalid mixer %pK\n", mixer);
  109. return NULL;
  110. }
  111. ctl = mixer->hw_ctl;
  112. if (!mixer) {
  113. DRM_ERROR("invalid ctl %pK\n", ctl);
  114. return NULL;
  115. }
  116. return ctl;
  117. }
  118. static void _sde_plane_setup_panel_stacking(struct sde_plane *psde,
  119. struct sde_plane_state *pstate)
  120. {
  121. struct sde_hw_pipe_line_insertion_cfg *cfg;
  122. struct sde_crtc_state *cstate;
  123. u32 h_start = 0, h_total = 0, y_start = 0;
  124. struct drm_plane_state *dpstate = NULL;
  125. struct drm_crtc *drm_crtc = NULL;
  126. if (!psde || !psde->base.state || !psde->base.state->crtc) {
  127. SDE_ERROR("Invalid plane psde %p or drm plane state or drm crtc\n", psde);
  128. return;
  129. }
  130. dpstate = psde->base.state;
  131. drm_crtc = dpstate->crtc;
  132. cstate = to_sde_crtc_state(drm_crtc->state);
  133. pstate->lineinsertion_feature = cstate->line_insertion.panel_line_insertion_enable;
  134. if ((!test_bit(SDE_SSPP_LINE_INSERTION, (unsigned long *)&psde->features)) ||
  135. !cstate->line_insertion.panel_line_insertion_enable)
  136. return;
  137. cfg = &pstate->line_insertion_cfg;
  138. memset(cfg, 0, sizeof(*cfg));
  139. if (!cstate->line_insertion.padding_height)
  140. return;
  141. sde_crtc_calc_vpadding_param(psde->base.state->crtc->state,
  142. pstate->base.crtc_y, pstate->base.crtc_h,
  143. &y_start, &h_start, &h_total);
  144. cfg->enable = true;
  145. cfg->dummy_lines = cstate->line_insertion.padding_dummy;
  146. cfg->active_lines = cstate->line_insertion.padding_active;
  147. cfg->first_active_lines = h_start;
  148. cfg->dst_h = h_total;
  149. psde->pipe_cfg.dst_rect.y += y_start - pstate->base.crtc_y;
  150. }
  151. static bool sde_plane_enabled(const struct drm_plane_state *state)
  152. {
  153. return state && state->fb && state->crtc;
  154. }
  155. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  156. {
  157. struct sde_plane *psde;
  158. if (!plane)
  159. return false;
  160. psde = to_sde_plane(plane);
  161. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  162. }
  163. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  164. enum sde_sspp_multirect_index rect_mode, bool enable)
  165. {
  166. struct sde_plane *psde;
  167. if (!plane)
  168. return;
  169. psde = to_sde_plane(plane);
  170. if (psde->pipe_hw->ops.set_src_split_order)
  171. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  172. rect_mode, enable);
  173. }
  174. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  175. {
  176. struct sde_plane *psde;
  177. struct sde_kms *sde_kms;
  178. struct msm_drm_private *priv;
  179. if (!plane || !plane->dev) {
  180. SDE_ERROR("invalid plane\n");
  181. return;
  182. }
  183. priv = plane->dev->dev_private;
  184. if (!priv || !priv->kms) {
  185. SDE_ERROR("invalid KMS reference\n");
  186. return;
  187. }
  188. sde_kms = to_sde_kms(priv->kms);
  189. psde = to_sde_plane(plane);
  190. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm, sde_kms->catalog);
  191. }
  192. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  193. struct drm_crtc *crtc,
  194. struct drm_framebuffer *fb)
  195. {
  196. struct sde_plane *psde;
  197. const struct sde_format *fmt = NULL;
  198. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  199. struct sde_perf_cfg *perf;
  200. struct sde_plane_state *pstate;
  201. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  202. bool inline_rot = false, landscape = false;
  203. struct drm_display_mode *mode;
  204. u32 fl_require0 = 0;
  205. if (!plane || !fb) {
  206. SDE_ERROR("invalid arguments\n");
  207. return;
  208. }
  209. psde = to_sde_plane(plane);
  210. pstate = to_sde_plane_state(plane->state);
  211. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  212. SDE_ERROR("invalid arguments\n");
  213. return;
  214. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  215. return;
  216. }
  217. mode = &crtc->state->adjusted_mode;
  218. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  219. frame_rate = drm_mode_vrefresh(&crtc->mode);
  220. perf = &psde->catalog->perf;
  221. qos_count = perf->qos_refresh_count;
  222. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  223. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  224. (fps_index == qos_count - 1))
  225. break;
  226. fps_index++;
  227. }
  228. if (psde->is_rt_pipe) {
  229. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  230. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  231. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  232. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  233. else if (inline_rot)
  234. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  235. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  236. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  237. else
  238. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  239. } else {
  240. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  241. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  242. }
  243. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  244. if (psde->scaler3_cfg.enable)
  245. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  246. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  247. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  248. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  249. if (landscape) {
  250. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  251. fl_require0 = psde->catalog->qos_target_time_ns /
  252. (sde_crtc->line_time_in_ns * 2);
  253. if (!fl_require0 || fl_require0 < 4.5)
  254. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  255. }
  256. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  257. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  258. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  259. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  260. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  261. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  262. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  263. plane->base.id, psde->pipe - SSPP_VIG0,
  264. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  265. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  266. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  267. psde->is_rt_pipe, psde->wb_usage_type);
  268. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  269. }
  270. /**
  271. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  272. * @plane: Pointer to drm plane
  273. * @enable: true to enable QoS control
  274. * @flags: QoS control mode (enum sde_plane_qos)
  275. */
  276. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  277. bool enable, u32 flags)
  278. {
  279. struct sde_plane *psde;
  280. if (!plane) {
  281. SDE_ERROR("invalid arguments\n");
  282. return;
  283. }
  284. psde = to_sde_plane(plane);
  285. if (!psde->pipe_hw || !psde->pipe_sblk) {
  286. SDE_ERROR("invalid arguments\n");
  287. return;
  288. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  289. return;
  290. }
  291. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  292. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  293. psde->pipe_qos_cfg.danger_vblank =
  294. psde->pipe_sblk->danger_vblank;
  295. psde->pipe_qos_cfg.vblank_en = enable;
  296. }
  297. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  298. /* this feature overrules previous VBLANK_CTRL */
  299. psde->pipe_qos_cfg.vblank_en = false;
  300. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  301. psde->pipe_qos_cfg.danger_vblank = 0;
  302. }
  303. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  304. psde->pipe_qos_cfg.danger_safe_en = enable;
  305. if (!psde->is_rt_pipe) {
  306. psde->pipe_qos_cfg.vblank_en = false;
  307. psde->pipe_qos_cfg.danger_safe_en = false;
  308. }
  309. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  310. plane->base.id,
  311. psde->pipe - SSPP_VIG0,
  312. psde->pipe_qos_cfg.danger_safe_en,
  313. psde->pipe_qos_cfg.vblank_en,
  314. psde->pipe_qos_cfg.creq_vblank,
  315. psde->pipe_qos_cfg.danger_vblank,
  316. psde->is_rt_pipe);
  317. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  318. &psde->pipe_qos_cfg);
  319. }
  320. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  321. {
  322. struct sde_plane *psde;
  323. if (!plane)
  324. return;
  325. psde = to_sde_plane(plane);
  326. psde->revalidate = enable;
  327. }
  328. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  329. {
  330. struct sde_plane *psde;
  331. int rc;
  332. if (!plane) {
  333. SDE_ERROR("invalid arguments\n");
  334. return -EINVAL;
  335. }
  336. psde = to_sde_plane(plane);
  337. if (!psde->is_rt_pipe)
  338. goto end;
  339. rc = pm_runtime_resume_and_get(plane->dev->dev);
  340. if (rc < 0) {
  341. SDE_ERROR("failed to enable power resource %d\n", rc);
  342. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  343. return rc;
  344. }
  345. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  346. pm_runtime_put_sync(plane->dev->dev);
  347. end:
  348. return 0;
  349. }
  350. /**
  351. * _sde_plane_set_ot_limit - set OT limit for the given plane
  352. * @plane: Pointer to drm plane
  353. * @crtc: Pointer to drm crtc
  354. */
  355. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  356. struct drm_crtc *crtc)
  357. {
  358. struct sde_plane *psde;
  359. struct sde_vbif_set_ot_params ot_params;
  360. struct msm_drm_private *priv;
  361. struct sde_kms *sde_kms;
  362. if (!plane || !plane->dev || !crtc) {
  363. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  364. !plane, !crtc);
  365. return;
  366. }
  367. priv = plane->dev->dev_private;
  368. if (!priv || !priv->kms) {
  369. SDE_ERROR("invalid KMS reference\n");
  370. return;
  371. }
  372. sde_kms = to_sde_kms(priv->kms);
  373. psde = to_sde_plane(plane);
  374. if (!psde->pipe_hw) {
  375. SDE_ERROR("invalid pipe reference\n");
  376. return;
  377. }
  378. memset(&ot_params, 0, sizeof(ot_params));
  379. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  380. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  381. ot_params.width = psde->pipe_cfg.src_rect.w;
  382. ot_params.height = psde->pipe_cfg.src_rect.h;
  383. ot_params.is_wfd = ((psde->is_rt_pipe)
  384. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  385. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  386. ot_params.vbif_idx = VBIF_RT;
  387. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  388. ot_params.rd = true;
  389. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  390. }
  391. /**
  392. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  393. * @plane: Pointer to drm plane
  394. */
  395. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  396. {
  397. struct sde_plane *psde;
  398. struct sde_vbif_set_qos_params qos_params;
  399. struct msm_drm_private *priv;
  400. struct sde_kms *sde_kms;
  401. if (!plane || !plane->dev) {
  402. SDE_ERROR("invalid arguments\n");
  403. return;
  404. }
  405. priv = plane->dev->dev_private;
  406. if (!priv || !priv->kms) {
  407. SDE_ERROR("invalid KMS reference\n");
  408. return;
  409. }
  410. sde_kms = to_sde_kms(priv->kms);
  411. psde = to_sde_plane(plane);
  412. if (!psde->pipe_hw) {
  413. SDE_ERROR("invalid pipe reference\n");
  414. return;
  415. }
  416. memset(&qos_params, 0, sizeof(qos_params));
  417. qos_params.vbif_idx = VBIF_RT;
  418. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  419. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  420. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  421. if (psde->is_rt_pipe)
  422. qos_params.client_type = VBIF_RT_CLIENT;
  423. else
  424. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  425. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  426. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  427. plane->base.id, qos_params.num,
  428. qos_params.vbif_idx,
  429. qos_params.xin_id, qos_params.client_type,
  430. qos_params.clk_ctrl);
  431. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  432. }
  433. /**
  434. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  435. * @plane: Pointer to drm plane
  436. * @pstate: Pointer to sde plane state
  437. */
  438. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  439. struct sde_plane_state *pstate)
  440. {
  441. struct sde_plane *psde;
  442. struct sde_hw_pipe_ts_cfg cfg;
  443. struct msm_drm_private *priv;
  444. struct sde_kms *sde_kms;
  445. if (!plane || !plane->dev) {
  446. SDE_ERROR("invalid arguments");
  447. return;
  448. }
  449. priv = plane->dev->dev_private;
  450. if (!priv || !priv->kms) {
  451. SDE_ERROR("invalid KMS reference\n");
  452. return;
  453. }
  454. sde_kms = to_sde_kms(priv->kms);
  455. psde = to_sde_plane(plane);
  456. if (!psde->pipe_hw) {
  457. SDE_ERROR("invalid pipe reference\n");
  458. return;
  459. }
  460. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  461. return;
  462. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  463. memset(&cfg, 0, sizeof(cfg));
  464. cfg.size = sde_plane_get_property(pstate,
  465. PLANE_PROP_PREFILL_SIZE);
  466. cfg.time = sde_plane_get_property(pstate,
  467. PLANE_PROP_PREFILL_TIME);
  468. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  469. plane->base.id, cfg.size, cfg.time);
  470. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  471. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  472. pstate->multirect_index);
  473. }
  474. /* helper to update a state's input fence pointer from the property */
  475. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  476. struct sde_plane_state *pstate, uint64_t fd)
  477. {
  478. if (!psde || !pstate) {
  479. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  480. !psde, !pstate);
  481. return;
  482. }
  483. /* clear previous reference */
  484. if (pstate->input_fence)
  485. sde_sync_put(pstate->input_fence);
  486. /* get fence pointer for later */
  487. if (fd == 0)
  488. pstate->input_fence = NULL;
  489. else
  490. pstate->input_fence = sde_sync_get(fd);
  491. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  492. }
  493. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  494. {
  495. struct sde_plane *psde;
  496. struct sde_plane_state *pstate;
  497. uint32_t prefix;
  498. void *input_fence;
  499. int ret = -EINVAL;
  500. signed long rc;
  501. if (!plane) {
  502. SDE_ERROR("invalid plane\n");
  503. } else if (!plane->state) {
  504. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  505. } else {
  506. psde = to_sde_plane(plane);
  507. pstate = to_sde_plane_state(plane->state);
  508. input_fence = pstate->input_fence;
  509. if (input_fence) {
  510. prefix = sde_sync_get_name_prefix(input_fence);
  511. rc = sde_sync_wait(input_fence, wait_ms);
  512. switch (rc) {
  513. case 0:
  514. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  515. wait_ms, prefix, sde_plane_get_property(pstate,
  516. PLANE_PROP_INPUT_FENCE));
  517. psde->is_error = true;
  518. sde_kms_timeline_status(plane->dev);
  519. ret = -ETIMEDOUT;
  520. break;
  521. case -ERESTARTSYS:
  522. SDE_ERROR_PLANE(psde,
  523. "%ums wait interrupted on %08X\n",
  524. wait_ms, prefix);
  525. psde->is_error = true;
  526. ret = -ERESTARTSYS;
  527. break;
  528. case -EINVAL:
  529. SDE_ERROR_PLANE(psde,
  530. "invalid fence param for %08X\n",
  531. prefix);
  532. psde->is_error = true;
  533. ret = -EINVAL;
  534. break;
  535. case -EBADF:
  536. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  537. plane->base.id,
  538. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  539. psde->is_error = true;
  540. ret = 0;
  541. break;
  542. default:
  543. SDE_DEBUG_PLANE(psde, "signaled\n");
  544. ret = 0;
  545. break;
  546. }
  547. if (ret)
  548. SDE_EVT32(DRMID(plane), -ret, prefix, SDE_EVTLOG_ERROR);
  549. else
  550. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  551. } else {
  552. ret = 0;
  553. }
  554. }
  555. return ret;
  556. }
  557. /**
  558. * _sde_plane_get_aspace: gets the address space based on the
  559. * fb_translation mode property
  560. */
  561. static int _sde_plane_get_aspace(
  562. struct sde_plane *psde,
  563. struct sde_plane_state *pstate,
  564. struct msm_gem_address_space **aspace)
  565. {
  566. struct sde_kms *kms;
  567. int mode;
  568. if (!psde || !pstate || !aspace) {
  569. SDE_ERROR("invalid parameters\n");
  570. return -EINVAL;
  571. }
  572. kms = _sde_plane_get_kms(&psde->base);
  573. if (!kms) {
  574. SDE_ERROR("invalid kms\n");
  575. return -EINVAL;
  576. }
  577. mode = sde_plane_get_property(pstate,
  578. PLANE_PROP_FB_TRANSLATION_MODE);
  579. switch (mode) {
  580. case SDE_DRM_FB_NON_SEC:
  581. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  582. if (!aspace)
  583. return -EINVAL;
  584. break;
  585. case SDE_DRM_FB_SEC:
  586. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  587. if (!aspace)
  588. return -EINVAL;
  589. break;
  590. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  591. case SDE_DRM_FB_SEC_DIR_TRANS:
  592. *aspace = NULL;
  593. break;
  594. default:
  595. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  596. return -EFAULT;
  597. }
  598. return 0;
  599. }
  600. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  601. struct sde_plane_state *pstate,
  602. struct sde_hw_pipe_cfg *pipe_cfg,
  603. struct drm_framebuffer *fb)
  604. {
  605. struct sde_plane *psde;
  606. struct msm_gem_address_space *aspace = NULL;
  607. int ret, mode;
  608. bool secure = false;
  609. if (!plane || !pstate || !pipe_cfg || !fb) {
  610. SDE_ERROR(
  611. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  612. !plane, !pstate, !pipe_cfg, !fb);
  613. return;
  614. }
  615. psde = to_sde_plane(plane);
  616. if (!psde->pipe_hw) {
  617. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  618. return;
  619. }
  620. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  621. if (ret) {
  622. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  623. return;
  624. }
  625. /*
  626. * framebuffer prepare is deferred for prepare_fb calls that
  627. * happen during the transition from secure to non-secure.
  628. * Handle the prepare at this point for such cases. This can be
  629. * expected for one or two frames during the transition.
  630. */
  631. if (aspace && pstate->defer_prepare_fb) {
  632. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  633. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  634. if (ret) {
  635. SDE_ERROR_PLANE(psde,
  636. "failed to prepare framebuffer %d\n", ret);
  637. return;
  638. }
  639. pstate->defer_prepare_fb = false;
  640. }
  641. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  642. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  643. secure = true;
  644. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  645. if (ret == -EAGAIN)
  646. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  647. else if (ret) {
  648. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  649. /*
  650. * Force solid fill color on error. This is to prevent
  651. * smmu faults during secure session transition.
  652. */
  653. psde->is_error = true;
  654. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  655. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  656. pipe_cfg->layout.width,
  657. pipe_cfg->layout.height,
  658. pipe_cfg->layout.plane_addr[0],
  659. pipe_cfg->layout.plane_size[0],
  660. pipe_cfg->layout.plane_addr[1],
  661. pipe_cfg->layout.plane_size[1],
  662. pipe_cfg->layout.plane_addr[2],
  663. pipe_cfg->layout.plane_size[2],
  664. pipe_cfg->layout.plane_addr[3],
  665. pipe_cfg->layout.plane_size[3],
  666. pstate->multirect_index,
  667. secure);
  668. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  669. pstate->multirect_index);
  670. }
  671. }
  672. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  673. struct sde_plane_state *pstate)
  674. {
  675. struct sde_hw_scaler3_cfg *cfg;
  676. int ret = 0;
  677. if (!psde || !pstate) {
  678. SDE_ERROR("invalid args\n");
  679. return -EINVAL;
  680. }
  681. cfg = &psde->scaler3_cfg;
  682. cfg->dir_lut = msm_property_get_blob(
  683. &psde->property_info,
  684. &pstate->property_state, &cfg->dir_len,
  685. PLANE_PROP_SCALER_LUT_ED);
  686. cfg->cir_lut = msm_property_get_blob(
  687. &psde->property_info,
  688. &pstate->property_state, &cfg->cir_len,
  689. PLANE_PROP_SCALER_LUT_CIR);
  690. cfg->sep_lut = msm_property_get_blob(
  691. &psde->property_info,
  692. &pstate->property_state, &cfg->sep_len,
  693. PLANE_PROP_SCALER_LUT_SEP);
  694. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  695. ret = -ENODATA;
  696. return ret;
  697. }
  698. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  699. struct sde_plane_state *pstate)
  700. {
  701. struct sde_hw_scaler3_cfg *cfg;
  702. cfg = &psde->scaler3_cfg;
  703. cfg->sep_lut = msm_property_get_blob(
  704. &psde->property_info,
  705. &pstate->property_state, &cfg->sep_len,
  706. PLANE_PROP_SCALER_LUT_SEP);
  707. return cfg->sep_lut ? 0 : -ENODATA;
  708. }
  709. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  710. struct sde_plane_state *pstate, const struct sde_format *fmt,
  711. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  712. {
  713. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  714. struct sde_hw_scaler3_cfg *scale_cfg;
  715. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  716. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  717. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  718. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  719. chroma_subsmpl_h, chroma_subsmpl_v);
  720. return;
  721. }
  722. scale_cfg = &psde->scaler3_cfg;
  723. src_w = psde->pipe_cfg.src_rect.w;
  724. src_h = psde->pipe_cfg.src_rect.h;
  725. dst_w = psde->pipe_cfg.dst_rect.w;
  726. dst_h = psde->pipe_cfg.dst_rect.h;
  727. memset(scale_cfg, 0, sizeof(*scale_cfg));
  728. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  729. /*
  730. * For inline rotation cases, scaler config is post-rotation,
  731. * so swap the dimensions here. However, pixel extension will
  732. * need pre-rotation settings, this will be corrected below
  733. * when calculating pixel extension settings.
  734. */
  735. if (inline_rotation)
  736. swap(src_w, src_h);
  737. decimated = DECIMATED_DIMENSION(src_w,
  738. psde->pipe_cfg.horz_decimation);
  739. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  740. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  741. decimated = DECIMATED_DIMENSION(src_h,
  742. psde->pipe_cfg.vert_decimation);
  743. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  744. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  745. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  746. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  747. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  748. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  749. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  750. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  751. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  752. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  753. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  754. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  755. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  756. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  757. for (i = 0; i < SDE_MAX_PLANES; i++) {
  758. /*
  759. * For inline rotation cases with pre-downscaling enabled
  760. * set x pre-downscale value if required. Only x direction
  761. * is currently supported. Use src_h as values have been swapped
  762. * and x direction corresponds to height value.
  763. */
  764. src_h_pre_down = src_h;
  765. if (pre_down_supported && inline_rotation) {
  766. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  767. src_h_pre_down = src_h / 2;
  768. }
  769. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  770. psde->pipe_cfg.horz_decimation);
  771. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  772. psde->pipe_cfg.vert_decimation);
  773. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  774. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  775. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  776. }
  777. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  778. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  779. /* For pixel extension we need the pre-rotated orientation */
  780. if (inline_rotation) {
  781. psde->pixel_ext.num_ext_pxls_top[i] =
  782. scale_cfg->src_width[i];
  783. psde->pixel_ext.num_ext_pxls_left[i] =
  784. scale_cfg->src_height[i];
  785. } else {
  786. psde->pixel_ext.num_ext_pxls_top[i] =
  787. scale_cfg->src_height[i];
  788. psde->pixel_ext.num_ext_pxls_left[i] =
  789. scale_cfg->src_width[i];
  790. }
  791. }
  792. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  793. && (src_w == dst_w) && !inline_rotation) ||
  794. pstate->multirect_mode)
  795. return;
  796. SDE_DEBUG_PLANE(psde,
  797. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  798. src_w, src_h, dst_w, dst_h,
  799. chroma_subsmpl_v, chroma_subsmpl_h,
  800. fmt->base.pixel_format);
  801. scale_cfg->dst_width = dst_w;
  802. scale_cfg->dst_height = dst_h;
  803. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  804. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  805. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  806. scale_cfg->lut_flag = 0;
  807. scale_cfg->blend_cfg = 1;
  808. scale_cfg->enable = 1;
  809. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  810. }
  811. /**
  812. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  813. * @psde: Pointer to SDE plane object
  814. * @src: Source size
  815. * @dst: Destination size
  816. * @phase_steps: Pointer to output array for phase steps
  817. * @filter: Pointer to output array for filter type
  818. * @fmt: Pointer to format definition
  819. * @chroma_subsampling: Subsampling amount for chroma channel
  820. *
  821. * Returns: 0 on success
  822. */
  823. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  824. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  825. enum sde_hw_filter *filter, const struct sde_format *fmt,
  826. uint32_t chroma_subsampling)
  827. {
  828. if (!psde || !phase_steps || !filter || !fmt) {
  829. SDE_ERROR(
  830. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  831. !psde, !phase_steps, !filter, !fmt);
  832. return -EINVAL;
  833. }
  834. /* calculate phase steps, leave init phase as zero */
  835. phase_steps[SDE_SSPP_COMP_0] =
  836. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  837. phase_steps[SDE_SSPP_COMP_1_2] =
  838. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  839. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  840. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  841. /* calculate scaler config, if necessary */
  842. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  843. filter[SDE_SSPP_COMP_3] =
  844. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  845. SDE_SCALE_FILTER_PCMN;
  846. if (SDE_FORMAT_IS_YUV(fmt)) {
  847. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  848. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  849. } else {
  850. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  851. filter[SDE_SSPP_COMP_1_2] =
  852. SDE_SCALE_FILTER_NEAREST;
  853. }
  854. } else {
  855. /* disable scaler */
  856. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  857. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  858. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  859. }
  860. return 0;
  861. }
  862. /**
  863. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  864. * @psde: Pointer to SDE plane object
  865. * @src: Source size
  866. * @dst: Destination size
  867. * @decimated_src: Source size after decimation, if any
  868. * @phase_steps: Pointer to output array for phase steps
  869. * @out_src: Output array for pixel extension values
  870. * @out_edge1: Output array for pixel extension first edge
  871. * @out_edge2: Output array for pixel extension second edge
  872. * @filter: Pointer to array for filter type
  873. * @fmt: Pointer to format definition
  874. * @chroma_subsampling: Subsampling amount for chroma channel
  875. * @post_compare: Whether to chroma subsampled source size for comparisions
  876. */
  877. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  878. uint32_t src, uint32_t dst, uint32_t decimated_src,
  879. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  880. int *out_edge2, enum sde_hw_filter *filter,
  881. const struct sde_format *fmt, uint32_t chroma_subsampling,
  882. bool post_compare)
  883. {
  884. int64_t edge1, edge2, caf;
  885. uint32_t src_work;
  886. int i, tmp;
  887. if (psde && phase_steps && out_src && out_edge1 &&
  888. out_edge2 && filter && fmt) {
  889. /* handle CAF for YUV formats */
  890. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  891. caf = PHASE_STEP_UNIT_SCALE;
  892. else
  893. caf = 0;
  894. for (i = 0; i < SDE_MAX_PLANES; i++) {
  895. src_work = decimated_src;
  896. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  897. src_work /= chroma_subsampling;
  898. if (post_compare)
  899. src = src_work;
  900. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  901. /* unity */
  902. edge1 = 0;
  903. edge2 = 0;
  904. } else if (dst >= src) {
  905. /* upscale */
  906. edge1 = (1 << PHASE_RESIDUAL);
  907. edge1 -= caf;
  908. edge2 = (1 << PHASE_RESIDUAL);
  909. edge2 += (dst - 1) * *(phase_steps + i);
  910. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  911. edge2 += caf;
  912. edge2 = -(edge2);
  913. } else {
  914. /* downscale */
  915. edge1 = 0;
  916. edge2 = (dst - 1) * *(phase_steps + i);
  917. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  918. edge2 += *(phase_steps + i);
  919. edge2 = -(edge2);
  920. }
  921. /* only enable CAF for luma plane */
  922. caf = 0;
  923. /* populate output arrays */
  924. *(out_src + i) = src_work;
  925. /* edge updates taken from __pxl_extn_helper */
  926. if (edge1 >= 0) {
  927. tmp = (uint32_t)edge1;
  928. tmp >>= PHASE_STEP_SHIFT;
  929. *(out_edge1 + i) = -tmp;
  930. } else {
  931. tmp = (uint32_t)(-edge1);
  932. *(out_edge1 + i) =
  933. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  934. PHASE_STEP_SHIFT;
  935. }
  936. if (edge2 >= 0) {
  937. tmp = (uint32_t)edge2;
  938. tmp >>= PHASE_STEP_SHIFT;
  939. *(out_edge2 + i) = -tmp;
  940. } else {
  941. tmp = (uint32_t)(-edge2);
  942. *(out_edge2 + i) =
  943. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  944. PHASE_STEP_SHIFT;
  945. }
  946. }
  947. }
  948. }
  949. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  950. {
  951. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  952. {
  953. /* S15.16 format */
  954. 0x00012A00, 0x00000000, 0x00019880,
  955. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  956. 0x00012A00, 0x00020480, 0x00000000,
  957. },
  958. /* signed bias */
  959. { 0xfff0, 0xff80, 0xff80,},
  960. { 0x0, 0x0, 0x0,},
  961. /* unsigned clamp */
  962. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  963. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  964. };
  965. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  966. {
  967. /* S15.16 format */
  968. 0x00012A00, 0x00000000, 0x00019880,
  969. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  970. 0x00012A00, 0x00020480, 0x00000000,
  971. },
  972. /* signed bias */
  973. { 0xffc0, 0xfe00, 0xfe00,},
  974. { 0x0, 0x0, 0x0,},
  975. /* unsigned clamp */
  976. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  977. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  978. };
  979. if (!psde) {
  980. SDE_ERROR("invalid plane\n");
  981. return;
  982. }
  983. /* revert to kernel default if override not available */
  984. if (psde->csc_usr_ptr)
  985. psde->csc_ptr = psde->csc_usr_ptr;
  986. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  987. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  988. else
  989. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  990. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  991. psde->csc_ptr->csc_mv[0],
  992. psde->csc_ptr->csc_mv[1],
  993. psde->csc_ptr->csc_mv[2]);
  994. }
  995. static void sde_color_process_plane_setup(struct drm_plane *plane)
  996. {
  997. struct sde_plane *psde;
  998. struct sde_plane_state *pstate;
  999. uint32_t hue, saturation, value, contrast;
  1000. struct drm_msm_memcol *memcol = NULL;
  1001. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1002. struct drm_msm_igc_lut *igc = NULL;
  1003. struct drm_msm_pgc_lut *gc = NULL;
  1004. size_t memcol_sz = 0, size = 0;
  1005. struct sde_hw_cp_cfg hw_cfg = {};
  1006. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1007. bool fp16_igc, fp16_unmult;
  1008. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1009. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1010. psde = to_sde_plane(plane);
  1011. pstate = to_sde_plane_state(plane->state);
  1012. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1013. if (psde->pipe_hw->ops.setup_pa_hue)
  1014. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1015. saturation = (uint32_t) sde_plane_get_property(pstate,
  1016. PLANE_PROP_SATURATION_ADJUST);
  1017. if (psde->pipe_hw->ops.setup_pa_sat)
  1018. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1019. value = (uint32_t) sde_plane_get_property(pstate,
  1020. PLANE_PROP_VALUE_ADJUST);
  1021. if (psde->pipe_hw->ops.setup_pa_val)
  1022. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1023. contrast = (uint32_t) sde_plane_get_property(pstate,
  1024. PLANE_PROP_CONTRAST_ADJUST);
  1025. if (psde->pipe_hw->ops.setup_pa_cont)
  1026. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1027. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1028. /* Skin memory color setup */
  1029. memcol = msm_property_get_blob(&psde->property_info,
  1030. &pstate->property_state,
  1031. &memcol_sz,
  1032. PLANE_PROP_SKIN_COLOR);
  1033. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1034. MEMCOLOR_SKIN, memcol);
  1035. /* Sky memory color setup */
  1036. memcol = msm_property_get_blob(&psde->property_info,
  1037. &pstate->property_state,
  1038. &memcol_sz,
  1039. PLANE_PROP_SKY_COLOR);
  1040. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1041. MEMCOLOR_SKY, memcol);
  1042. /* Foliage memory color setup */
  1043. memcol = msm_property_get_blob(&psde->property_info,
  1044. &pstate->property_state,
  1045. &memcol_sz,
  1046. PLANE_PROP_FOLIAGE_COLOR);
  1047. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1048. MEMCOLOR_FOLIAGE, memcol);
  1049. }
  1050. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1051. psde->pipe_hw->ops.setup_vig_gamut) {
  1052. vig_gamut = msm_property_get_blob(&psde->property_info,
  1053. &pstate->property_state,
  1054. &size,
  1055. PLANE_PROP_VIG_GAMUT);
  1056. hw_cfg.last_feature = 0;
  1057. hw_cfg.ctl = ctl;
  1058. hw_cfg.len = size;
  1059. hw_cfg.payload = vig_gamut;
  1060. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1061. }
  1062. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1063. psde->pipe_hw->ops.setup_vig_igc) {
  1064. igc = msm_property_get_blob(&psde->property_info,
  1065. &pstate->property_state,
  1066. &size,
  1067. PLANE_PROP_VIG_IGC);
  1068. hw_cfg.last_feature = 0;
  1069. hw_cfg.ctl = ctl;
  1070. hw_cfg.len = size;
  1071. hw_cfg.payload = igc;
  1072. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1073. }
  1074. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1075. psde->pipe_hw->ops.setup_dma_igc) {
  1076. igc = msm_property_get_blob(&psde->property_info,
  1077. &pstate->property_state,
  1078. &size,
  1079. PLANE_PROP_DMA_IGC);
  1080. hw_cfg.last_feature = 0;
  1081. hw_cfg.ctl = ctl;
  1082. hw_cfg.len = size;
  1083. hw_cfg.payload = igc;
  1084. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1085. pstate->multirect_index);
  1086. }
  1087. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1088. psde->pipe_hw->ops.setup_dma_gc) {
  1089. gc = msm_property_get_blob(&psde->property_info,
  1090. &pstate->property_state,
  1091. &size,
  1092. PLANE_PROP_DMA_GC);
  1093. hw_cfg.last_feature = 0;
  1094. hw_cfg.ctl = ctl;
  1095. hw_cfg.len = size;
  1096. hw_cfg.payload = gc;
  1097. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1098. pstate->multirect_index);
  1099. }
  1100. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1101. psde->pipe_hw->ops.setup_fp16_igc) {
  1102. fp16_igc = !!sde_plane_get_property(pstate,
  1103. PLANE_PROP_FP16_IGC);
  1104. hw_cfg.last_feature = 0;
  1105. hw_cfg.ctl = ctl;
  1106. hw_cfg.len = sizeof(bool);
  1107. hw_cfg.payload = &fp16_igc;
  1108. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1109. pstate->multirect_index, &hw_cfg);
  1110. }
  1111. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1112. psde->pipe_hw->ops.setup_fp16_gc) {
  1113. fp16_gc = msm_property_get_blob(&psde->property_info,
  1114. &pstate->property_state,
  1115. &size,
  1116. PLANE_PROP_FP16_GC);
  1117. hw_cfg.last_feature = 0;
  1118. hw_cfg.ctl = ctl;
  1119. hw_cfg.len = size;
  1120. hw_cfg.payload = fp16_gc;
  1121. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1122. pstate->multirect_index, &hw_cfg);
  1123. }
  1124. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1125. psde->pipe_hw->ops.setup_fp16_csc) {
  1126. fp16_csc = msm_property_get_blob(&psde->property_info,
  1127. &pstate->property_state,
  1128. &size,
  1129. PLANE_PROP_FP16_CSC);
  1130. hw_cfg.last_feature = 0;
  1131. hw_cfg.ctl = ctl;
  1132. hw_cfg.len = size;
  1133. hw_cfg.payload = fp16_csc;
  1134. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1135. pstate->multirect_index, &hw_cfg);
  1136. }
  1137. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1138. psde->pipe_hw->ops.setup_fp16_unmult) {
  1139. fp16_unmult = !!sde_plane_get_property(pstate,
  1140. PLANE_PROP_FP16_UNMULT);
  1141. hw_cfg.last_feature = 0;
  1142. hw_cfg.ctl = ctl;
  1143. hw_cfg.len = sizeof(bool);
  1144. hw_cfg.payload = &fp16_unmult;
  1145. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1146. pstate->multirect_index, &hw_cfg);
  1147. }
  1148. }
  1149. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1150. struct sde_plane_state *pstate,
  1151. const struct sde_format *fmt, bool color_fill)
  1152. {
  1153. struct sde_hw_pixel_ext *pe;
  1154. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1155. const struct drm_format_info *info = NULL;
  1156. if (!psde || !fmt || !pstate) {
  1157. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1158. !psde, !fmt, !pstate);
  1159. return;
  1160. }
  1161. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1162. sizeof(psde->scaler3_cfg));
  1163. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1164. sizeof(psde->pixel_ext));
  1165. info = drm_format_info(fmt->base.pixel_format);
  1166. pe = &psde->pixel_ext;
  1167. psde->pipe_cfg.horz_decimation =
  1168. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1169. psde->pipe_cfg.vert_decimation =
  1170. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1171. /* don't chroma subsample if decimating */
  1172. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1173. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1174. /* update scaler */
  1175. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1176. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1177. int rc = -EINVAL;
  1178. if (!color_fill && !psde->debugfs_default_scale)
  1179. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1180. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1181. _sde_plane_setup_scaler3_lut(psde, pstate);
  1182. if (rc || pstate->scaler_check_state !=
  1183. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1184. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1185. pstate->scaler_check_state,
  1186. psde->debugfs_default_scale, rc,
  1187. psde->pipe_cfg.src_rect.w,
  1188. psde->pipe_cfg.src_rect.h,
  1189. psde->pipe_cfg.dst_rect.w,
  1190. psde->pipe_cfg.dst_rect.h,
  1191. pstate->multirect_mode);
  1192. /* calculate default config for QSEED3 */
  1193. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1194. chroma_subsmpl_h, chroma_subsmpl_v);
  1195. }
  1196. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1197. color_fill || psde->debugfs_default_scale) {
  1198. uint32_t deci_dim, i;
  1199. /* calculate default configuration for QSEED2 */
  1200. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1201. SDE_DEBUG_PLANE(psde, "default config\n");
  1202. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1203. psde->pipe_cfg.horz_decimation);
  1204. _sde_plane_setup_scaler2(psde,
  1205. deci_dim,
  1206. psde->pipe_cfg.dst_rect.w,
  1207. pe->phase_step_x,
  1208. pe->horz_filter, fmt, chroma_subsmpl_h);
  1209. if (SDE_FORMAT_IS_YUV(fmt))
  1210. deci_dim &= ~0x1;
  1211. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1212. psde->pipe_cfg.dst_rect.w, deci_dim,
  1213. pe->phase_step_x,
  1214. pe->roi_w,
  1215. pe->num_ext_pxls_left,
  1216. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1217. chroma_subsmpl_h, 0);
  1218. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1219. psde->pipe_cfg.vert_decimation);
  1220. _sde_plane_setup_scaler2(psde,
  1221. deci_dim,
  1222. psde->pipe_cfg.dst_rect.h,
  1223. pe->phase_step_y,
  1224. pe->vert_filter, fmt, chroma_subsmpl_v);
  1225. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1226. psde->pipe_cfg.dst_rect.h, deci_dim,
  1227. pe->phase_step_y,
  1228. pe->roi_h,
  1229. pe->num_ext_pxls_top,
  1230. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1231. chroma_subsmpl_v, 1);
  1232. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1233. if (pe->num_ext_pxls_left[i] >= 0)
  1234. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1235. else
  1236. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1237. if (pe->num_ext_pxls_right[i] >= 0)
  1238. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1239. else
  1240. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1241. if (pe->num_ext_pxls_top[i] >= 0)
  1242. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1243. else
  1244. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1245. if (pe->num_ext_pxls_btm[i] >= 0)
  1246. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1247. else
  1248. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1249. }
  1250. }
  1251. if (psde->pipe_hw->ops.setup_pre_downscale)
  1252. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1253. &pstate->pre_down);
  1254. }
  1255. /**
  1256. * _sde_plane_color_fill - enables color fill on plane
  1257. * @psde: Pointer to SDE plane object
  1258. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1259. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1260. * Returns: 0 on success
  1261. */
  1262. static int _sde_plane_color_fill(struct sde_plane *psde,
  1263. uint32_t color, uint32_t alpha)
  1264. {
  1265. const struct sde_format *fmt;
  1266. const struct drm_plane *plane;
  1267. struct sde_plane_state *pstate;
  1268. bool blend_enable = true;
  1269. if (!psde || !psde->base.state) {
  1270. SDE_ERROR("invalid plane\n");
  1271. return -EINVAL;
  1272. }
  1273. if (!psde->pipe_hw) {
  1274. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1275. return -EINVAL;
  1276. }
  1277. plane = &psde->base;
  1278. pstate = to_sde_plane_state(plane->state);
  1279. SDE_DEBUG_PLANE(psde, "\n");
  1280. /*
  1281. * select fill format to match user property expectation,
  1282. * h/w only supports RGB variants
  1283. */
  1284. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1285. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1286. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1287. /* update sspp */
  1288. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1289. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1290. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1291. pstate->multirect_index);
  1292. /* override scaler/decimation if solid fill */
  1293. psde->pipe_cfg.src_rect.x = 0;
  1294. psde->pipe_cfg.src_rect.y = 0;
  1295. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1296. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1297. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1298. if (psde->pipe_hw->ops.setup_format)
  1299. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1300. fmt, blend_enable,
  1301. SDE_SSPP_SOLID_FILL,
  1302. pstate->multirect_index);
  1303. if (psde->pipe_hw->ops.setup_rects)
  1304. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1305. &psde->pipe_cfg,
  1306. pstate->multirect_index);
  1307. if (psde->pipe_hw->ops.setup_pe)
  1308. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1309. &psde->pixel_ext);
  1310. if (psde->pipe_hw->ops.setup_scaler &&
  1311. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1312. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1313. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1314. &psde->pipe_cfg, &psde->pixel_ext,
  1315. &psde->scaler3_cfg);
  1316. }
  1317. }
  1318. return 0;
  1319. }
  1320. /**
  1321. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1322. * @plane: Pointer to drm plane
  1323. * @state: Pointer to drm plane state to be validated
  1324. * return: 0 if success; error code otherwise
  1325. */
  1326. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1327. struct drm_plane_state *state)
  1328. {
  1329. struct sde_plane *psde;
  1330. struct sde_plane_state *pstate, *old_pstate;
  1331. int ret = 0;
  1332. u32 rotation;
  1333. if (!plane || !state) {
  1334. SDE_ERROR("invalid plane/state\n");
  1335. return -EINVAL;
  1336. }
  1337. psde = to_sde_plane(plane);
  1338. pstate = to_sde_plane_state(state);
  1339. old_pstate = to_sde_plane_state(plane->state);
  1340. /* check inline rotation and simplify the transform */
  1341. rotation = drm_rotation_simplify(
  1342. state->rotation,
  1343. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1344. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1345. if ((rotation & DRM_MODE_ROTATE_180) ||
  1346. (rotation & DRM_MODE_ROTATE_270)) {
  1347. SDE_ERROR_PLANE(psde,
  1348. "invalid rotation transform must be simplified 0x%x\n",
  1349. rotation);
  1350. ret = -EINVAL;
  1351. goto exit;
  1352. }
  1353. if (rotation & DRM_MODE_ROTATE_90) {
  1354. struct msm_drm_private *priv = plane->dev->dev_private;
  1355. struct sde_kms *sde_kms;
  1356. const struct msm_format *msm_fmt;
  1357. const struct sde_format *fmt;
  1358. struct sde_rect src;
  1359. bool q16_data = true;
  1360. POPULATE_RECT(&src, state->src_x, state->src_y,
  1361. state->src_w, state->src_h, q16_data);
  1362. /*
  1363. * DRM framework expects rotation flag in counter-clockwise
  1364. * direction and the HW expects in clockwise direction.
  1365. * Flip the flags to match with HW.
  1366. */
  1367. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1368. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1369. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1370. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1371. !psde->pipe_sblk->in_rot_maxheight ||
  1372. !psde->pipe_sblk->in_rot_format_list ||
  1373. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1374. SDE_ERROR_PLANE(psde,
  1375. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1376. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1377. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1378. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1379. !psde->pipe_sblk->in_rot_format_list,
  1380. !psde->pipe_sblk->in_rot_maxheight,
  1381. psde->features);
  1382. ret = -EINVAL;
  1383. goto exit;
  1384. }
  1385. /* check for valid height */
  1386. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1387. SDE_ERROR_PLANE(psde,
  1388. "invalid height for inline rot:%d max:%d\n",
  1389. src.h, psde->pipe_sblk->in_rot_maxheight);
  1390. ret = -EINVAL;
  1391. goto exit;
  1392. }
  1393. if (!sde_plane_enabled(state))
  1394. goto exit;
  1395. /* check for valid formats supported by inline rot */
  1396. sde_kms = to_sde_kms(priv->kms);
  1397. msm_fmt = msm_framebuffer_format(state->fb);
  1398. fmt = to_sde_format(msm_fmt);
  1399. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1400. psde->pipe_sblk->in_rot_format_list);
  1401. }
  1402. exit:
  1403. pstate->rotation = rotation;
  1404. return ret;
  1405. }
  1406. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1407. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1408. {
  1409. struct sde_plane *psde;
  1410. struct msm_drm_private *priv;
  1411. struct sde_vbif_set_xin_halt_params halt_params;
  1412. if (!plane || !plane->dev) {
  1413. SDE_ERROR("invalid arguments\n");
  1414. return false;
  1415. }
  1416. psde = to_sde_plane(plane);
  1417. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1418. SDE_ERROR("invalid pipe reference\n");
  1419. return false;
  1420. }
  1421. priv = plane->dev->dev_private;
  1422. if (!priv || !priv->kms) {
  1423. SDE_ERROR("invalid KMS reference\n");
  1424. return false;
  1425. }
  1426. memset(&halt_params, 0, sizeof(halt_params));
  1427. halt_params.vbif_idx = VBIF_RT;
  1428. halt_params.xin_id = xin_id;
  1429. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1430. halt_params.forced_on = halt_forced_clk;
  1431. halt_params.enable = enable;
  1432. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1433. }
  1434. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1435. {
  1436. struct sde_plane *psde;
  1437. if (!plane) {
  1438. SDE_ERROR("invalid plane\n");
  1439. return;
  1440. }
  1441. psde = to_sde_plane(plane);
  1442. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1443. SDE_ERROR("invalid pipe reference\n");
  1444. return;
  1445. }
  1446. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1447. psde->xin_halt_forced_clk =
  1448. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1449. psde->xin_halt_forced_clk, enable);
  1450. }
  1451. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1452. struct drm_crtc *crtc)
  1453. {
  1454. struct sde_plane *psde;
  1455. if (!plane || !crtc) {
  1456. SDE_ERROR("invalid plane/crtc\n");
  1457. return;
  1458. }
  1459. psde = to_sde_plane(plane);
  1460. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1461. return;
  1462. /* do all VBIF programming for the sec-ui allowed SSPP */
  1463. _sde_plane_set_qos_remap(plane);
  1464. _sde_plane_set_ot_limit(plane, crtc);
  1465. }
  1466. /**
  1467. * sde_plane_rot_install_properties - install plane rotator properties
  1468. * @plane: Pointer to drm plane
  1469. * @catalog: Pointer to mdss configuration
  1470. * return: none
  1471. */
  1472. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1473. struct sde_mdss_cfg *catalog)
  1474. {
  1475. struct sde_plane *psde = to_sde_plane(plane);
  1476. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1477. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1478. int ret = 0;
  1479. if (!plane || !psde) {
  1480. SDE_ERROR("invalid plane\n");
  1481. return;
  1482. } else if (!catalog) {
  1483. SDE_ERROR("invalid catalog\n");
  1484. return;
  1485. }
  1486. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1487. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1488. ret = drm_plane_create_rotation_property(plane,
  1489. DRM_MODE_ROTATE_0, supported_rotations);
  1490. if (ret) {
  1491. DRM_ERROR("create rotation property failed: %d\n", ret);
  1492. return;
  1493. }
  1494. }
  1495. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1496. {
  1497. struct sde_plane_state *pstate;
  1498. if (!drm_state)
  1499. return;
  1500. pstate = to_sde_plane_state(drm_state);
  1501. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1502. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1503. }
  1504. /**
  1505. * multi_rect validate API allows to validate only R0 and R1 RECT
  1506. * passing for each plane. Client of this API must not pass multiple
  1507. * plane which are not sharing same XIN client. Such calls will fail
  1508. * even though kernel client is passing valid multirect configuration.
  1509. */
  1510. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1511. {
  1512. struct sde_plane_state *pstate[R_MAX];
  1513. const struct drm_plane_state *drm_state[R_MAX];
  1514. struct sde_rect src[R_MAX], dst[R_MAX];
  1515. struct sde_plane *sde_plane[R_MAX];
  1516. const struct sde_format *fmt[R_MAX];
  1517. int xin_id[R_MAX];
  1518. bool q16_data = true;
  1519. int i, j, buffer_lines, width_threshold[R_MAX];
  1520. unsigned int max_tile_height = 1;
  1521. bool parallel_fetch_qualified = true;
  1522. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1523. const struct msm_format *msm_fmt;
  1524. bool const_alpha_enable = true;
  1525. for (i = 0; i < R_MAX; i++) {
  1526. drm_state[i] = i ? plane->r1 : plane->r0;
  1527. if (!drm_state[i]) {
  1528. SDE_ERROR("drm plane state is NULL\n");
  1529. return -EINVAL;
  1530. }
  1531. pstate[i] = to_sde_plane_state(drm_state[i]);
  1532. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1533. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1534. for (j = 0; j < i; j++) {
  1535. if (xin_id[i] != xin_id[j]) {
  1536. SDE_ERROR_PLANE(sde_plane[i],
  1537. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1538. j, xin_id[j], i, xin_id[i]);
  1539. return -EINVAL;
  1540. }
  1541. }
  1542. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1543. if (!msm_fmt) {
  1544. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1545. return -EINVAL;
  1546. }
  1547. fmt[i] = to_sde_format(msm_fmt);
  1548. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1549. (fmt[i]->tile_height > max_tile_height))
  1550. max_tile_height = fmt[i]->tile_height;
  1551. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1552. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1553. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1554. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1555. drm_state[i]->crtc_h, !q16_data);
  1556. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1557. SDE_ERROR_PLANE(sde_plane[i],
  1558. "scaling is not supported in multirect mode\n");
  1559. return -EINVAL;
  1560. }
  1561. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1562. SDE_ERROR_PLANE(sde_plane[i],
  1563. "inline rotation is not supported in mulirect mode\n");
  1564. return -EINVAL;
  1565. }
  1566. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1567. SDE_ERROR_PLANE(sde_plane[i],
  1568. "Unsupported format for multirect mode\n");
  1569. return -EINVAL;
  1570. }
  1571. /**
  1572. * SSPP PD_MEM is split half - one for each RECT.
  1573. * Tiled formats need 5 lines of buffering while fetching
  1574. * whereas linear formats need only 2 lines.
  1575. * So we cannot support more than half of the supported SSPP
  1576. * width for tiled formats.
  1577. */
  1578. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1579. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1580. width_threshold[i] /= 2;
  1581. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1582. parallel_fetch_qualified = false;
  1583. if (sde_plane[i]->is_virtual)
  1584. mode = sde_plane_get_property(pstate[i],
  1585. PLANE_PROP_MULTIRECT_MODE);
  1586. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1587. const_alpha_enable = false;
  1588. }
  1589. buffer_lines = 2 * max_tile_height;
  1590. /**
  1591. * fallback to driver mode selection logic if client is using
  1592. * multirect plane without setting property.
  1593. *
  1594. * validate multirect mode configuration based on rectangle
  1595. */
  1596. switch (mode) {
  1597. case SDE_SSPP_MULTIRECT_NONE:
  1598. if (parallel_fetch_qualified)
  1599. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1600. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1601. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1602. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1603. else
  1604. SDE_ERROR(
  1605. "planes(%d - %d) multirect mode selection fail\n",
  1606. drm_state[R0]->plane->base.id,
  1607. drm_state[R1]->plane->base.id);
  1608. break;
  1609. case SDE_SSPP_MULTIRECT_PARALLEL:
  1610. if (!parallel_fetch_qualified) {
  1611. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1612. drm_state[R0]->plane->base.id,
  1613. width_threshold[R0], src[R0].w);
  1614. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1615. drm_state[R1]->plane->base.id,
  1616. width_threshold[R1], src[R1].w);
  1617. SDE_ERROR("parallel fetch not qualified\n");
  1618. mode = SDE_SSPP_MULTIRECT_NONE;
  1619. }
  1620. break;
  1621. case SDE_SSPP_MULTIRECT_TIME_MX:
  1622. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1623. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1624. SDE_ERROR(
  1625. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1626. buffer_lines, drm_state[R0]->plane->base.id,
  1627. dst[R0].y, dst[R0].h);
  1628. SDE_ERROR(
  1629. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1630. buffer_lines, drm_state[R1]->plane->base.id,
  1631. dst[R1].y, dst[R1].h);
  1632. SDE_ERROR("time multiplexed fetch not qualified\n");
  1633. mode = SDE_SSPP_MULTIRECT_NONE;
  1634. }
  1635. break;
  1636. default:
  1637. SDE_ERROR("bad mode:%d selection\n", mode);
  1638. mode = SDE_SSPP_MULTIRECT_NONE;
  1639. break;
  1640. }
  1641. for (i = 0; i < R_MAX; i++) {
  1642. pstate[i]->multirect_mode = mode;
  1643. pstate[i]->const_alpha_en = const_alpha_enable;
  1644. }
  1645. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1646. return -EINVAL;
  1647. if (sde_plane[R0]->is_virtual) {
  1648. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1649. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1650. } else {
  1651. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1652. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1653. }
  1654. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1655. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1656. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1657. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1658. return 0;
  1659. }
  1660. /**
  1661. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1662. * @plane: Pointer to drm plane structure
  1663. * @ctl: Pointer to hardware control driver
  1664. * @set: set if true else clear
  1665. */
  1666. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1667. bool set)
  1668. {
  1669. if (!plane || !ctl) {
  1670. SDE_ERROR("invalid parameters\n");
  1671. return;
  1672. }
  1673. if (!ctl->ops.update_bitmask_sspp) {
  1674. SDE_ERROR("invalid ops\n");
  1675. return;
  1676. }
  1677. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1678. }
  1679. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1680. struct drm_plane_state *new_state)
  1681. {
  1682. struct drm_framebuffer *fb = new_state->fb;
  1683. struct sde_plane *psde = to_sde_plane(plane);
  1684. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1685. struct sde_hw_fmt_layout layout;
  1686. struct msm_gem_address_space *aspace;
  1687. int ret;
  1688. if (!fb)
  1689. return 0;
  1690. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1691. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1692. if (ret) {
  1693. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1694. return ret;
  1695. }
  1696. /* cache aspace */
  1697. pstate->aspace = aspace;
  1698. /*
  1699. * when transitioning from secure to non-secure,
  1700. * plane->prepare_fb happens before the commit. In such case,
  1701. * defer the prepare_fb and handled it late, during the commit
  1702. * after attaching the domains as part of the transition
  1703. */
  1704. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1705. true : false;
  1706. if (pstate->defer_prepare_fb) {
  1707. SDE_EVT32(DRMID(plane), psde->pipe);
  1708. SDE_DEBUG_PLANE(psde,
  1709. "domain not attached, prepare_fb handled later\n");
  1710. return 0;
  1711. }
  1712. if (pstate->aspace && fb) {
  1713. ret = msm_framebuffer_prepare(fb,
  1714. pstate->aspace);
  1715. if (ret) {
  1716. SDE_ERROR("failed to prepare framebuffer fb:%d plane:%d pipe:%d ret:%d\n",
  1717. fb->base.id, plane->base.id, psde->pipe, ret);
  1718. SDE_EVT32(fb->base.id, plane->base.id, psde->pipe, ret, SDE_EVTLOG_ERROR);
  1719. return ret;
  1720. }
  1721. }
  1722. /* validate framebuffer layout before commit */
  1723. ret = sde_format_populate_layout(pstate->aspace,
  1724. fb, &layout);
  1725. if (ret) {
  1726. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1727. return ret;
  1728. }
  1729. return 0;
  1730. }
  1731. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1732. struct drm_plane_state *old_state)
  1733. {
  1734. struct sde_plane *psde = to_sde_plane(plane);
  1735. struct sde_plane_state *old_pstate;
  1736. if (!old_state || !old_state->fb || !plane)
  1737. return;
  1738. old_pstate = to_sde_plane_state(old_state);
  1739. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1740. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1741. }
  1742. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1743. struct drm_plane_state *state,
  1744. struct drm_plane_state *old_state)
  1745. {
  1746. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1747. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1748. struct drm_framebuffer *fb, *old_fb;
  1749. /* no need to check it again */
  1750. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1751. return;
  1752. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1753. || psde->is_error) {
  1754. SDE_DEBUG_PLANE(psde,
  1755. "enabling/disabling full modeset required\n");
  1756. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1757. } else if (to_sde_plane_state(old_state)->pending) {
  1758. SDE_DEBUG_PLANE(psde, "still pending\n");
  1759. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1760. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1761. pstate->multirect_mode != old_pstate->multirect_mode) {
  1762. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1763. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1764. } else if (state->src_w != old_state->src_w ||
  1765. state->src_h != old_state->src_h ||
  1766. state->src_x != old_state->src_x ||
  1767. state->src_y != old_state->src_y) {
  1768. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1769. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1770. } else if (state->crtc_w != old_state->crtc_w ||
  1771. state->crtc_h != old_state->crtc_h ||
  1772. state->crtc_x != old_state->crtc_x ||
  1773. state->crtc_y != old_state->crtc_y) {
  1774. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1775. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1776. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1777. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1778. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1779. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1780. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1781. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1782. } else if (pstate->rotation != old_pstate->rotation) {
  1783. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1784. pstate->rotation, old_pstate->rotation);
  1785. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1786. }
  1787. fb = state->fb;
  1788. old_fb = old_state->fb;
  1789. if (!fb || !old_fb) {
  1790. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1791. } else if ((fb->format->format != old_fb->format->format) ||
  1792. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1793. SDE_DEBUG_PLANE(psde, "format change\n");
  1794. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1795. } else {
  1796. uint64_t new_mod = fb->modifier;
  1797. uint64_t old_mod = old_fb->modifier;
  1798. uint32_t *new_pitches = fb->pitches;
  1799. uint32_t *old_pitches = old_fb->pitches;
  1800. uint32_t *new_offset = fb->offsets;
  1801. uint32_t *old_offset = old_fb->offsets;
  1802. int i;
  1803. if (new_mod != old_mod) {
  1804. SDE_DEBUG_PLANE(psde,
  1805. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1806. new_mod, old_mod);
  1807. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1808. SDE_PLANE_DIRTY_RECTS;
  1809. }
  1810. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1811. if (new_pitches[i] != old_pitches[i]) {
  1812. SDE_DEBUG_PLANE(psde,
  1813. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1814. i, old_pitches[i], new_pitches[i]);
  1815. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1816. break;
  1817. }
  1818. }
  1819. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1820. if (new_offset[i] != old_offset[i]) {
  1821. SDE_DEBUG_PLANE(psde,
  1822. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1823. i, old_offset[i], new_offset[i]);
  1824. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1825. SDE_PLANE_DIRTY_RECTS;
  1826. break;
  1827. }
  1828. }
  1829. }
  1830. }
  1831. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1832. unsigned long base_addr, u32 size)
  1833. {
  1834. int ret = -EINVAL;
  1835. u32 addr;
  1836. struct sde_plane *psde = to_sde_plane(plane);
  1837. if (!psde || !base_addr || !size) {
  1838. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1839. return ret;
  1840. }
  1841. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1842. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1843. is_sde_plane_virtual(plane));
  1844. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1845. ret = 0;
  1846. }
  1847. return ret;
  1848. }
  1849. static inline bool _sde_plane_is_pre_downscale_enabled(
  1850. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1851. {
  1852. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1853. }
  1854. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1855. struct sde_plane_state *pstate,
  1856. const struct sde_format *fmt,
  1857. uint32_t img_w, uint32_t img_h,
  1858. uint32_t src_w, uint32_t src_h,
  1859. uint32_t deci_w, uint32_t deci_h)
  1860. {
  1861. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1862. bool pre_down_en;
  1863. int i;
  1864. if (!psde || !pstate || !fmt) {
  1865. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1866. return -EINVAL;
  1867. }
  1868. if (psde->debugfs_default_scale ||
  1869. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1870. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1871. return 0;
  1872. pd_cfg = &pstate->pre_down;
  1873. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1874. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1875. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1876. uint32_t hor_req_pixels, hor_fetch_pixels;
  1877. uint32_t vert_req_pixels, vert_fetch_pixels;
  1878. uint32_t src_w_tmp, src_h_tmp;
  1879. uint32_t scaler_w, scaler_h;
  1880. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1881. bool rot;
  1882. /* re-use color plane 1's config for plane 2 */
  1883. if (i == 2)
  1884. continue;
  1885. if (pre_down_en) {
  1886. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1887. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1888. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1889. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1890. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1891. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1892. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1893. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1894. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1895. i, pre_down_ratio_x, pre_down_ratio_y);
  1896. }
  1897. src_w_tmp = src_w;
  1898. src_h_tmp = src_h;
  1899. /*
  1900. * For chroma plane, width is half for the following sub sampled
  1901. * formats. Except in case of decimation, where hardware avoids
  1902. * 1 line of decimation instead of downsampling.
  1903. */
  1904. if (i == 1) {
  1905. if (!deci_w &&
  1906. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1907. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1908. src_w_tmp >>= 1;
  1909. if (!deci_h &&
  1910. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1911. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1912. src_h_tmp >>= 1;
  1913. }
  1914. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1915. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1916. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1917. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1918. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1919. deci_w);
  1920. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1921. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1922. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1923. deci_h);
  1924. if ((hor_req_pixels != hor_fetch_pixels) ||
  1925. (hor_fetch_pixels > img_w) ||
  1926. (vert_req_pixels != vert_fetch_pixels) ||
  1927. (vert_fetch_pixels > img_h)) {
  1928. SDE_ERROR_PLANE(psde,
  1929. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1930. hor_req_pixels, vert_req_pixels,
  1931. hor_fetch_pixels, vert_fetch_pixels,
  1932. img_w, img_h);
  1933. return -EINVAL;
  1934. }
  1935. /*
  1936. * swap the scaler src width & height for inline-rotation 90
  1937. * comparison with Pixel-Extension, as PE is based on
  1938. * pre-rotation and QSEED is based on post-rotation
  1939. */
  1940. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1941. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1942. : pstate->scaler3_cfg.src_width[i];
  1943. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1944. : pstate->scaler3_cfg.src_height[i];
  1945. /*
  1946. * Alpha plane can only be scaled using bilinear or pixel
  1947. * repeat/drop, src_width and src_height are only specified
  1948. * for Y and UV plane
  1949. */
  1950. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1951. vert_req_pixels / pre_down_ratio_y !=
  1952. scaler_h)) {
  1953. SDE_ERROR_PLANE(psde,
  1954. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1955. i, pstate->pixel_ext.roi_w[i],
  1956. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1957. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1958. return -EINVAL;
  1959. }
  1960. /*
  1961. * SSPP fetch , unpack output and QSEED3 input lines need
  1962. * to match for Y plane
  1963. */
  1964. if (i == 0 &&
  1965. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1966. BIT(SDE_DRM_DEINTERLACE)) &&
  1967. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1968. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1969. SDE_ERROR_PLANE(psde,
  1970. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1971. i, pstate->pixel_ext.roi_w[i],
  1972. pstate->pixel_ext.roi_h[i],
  1973. pstate->scaler3_cfg.src_width[i],
  1974. pstate->scaler3_cfg.src_height[i],
  1975. src_w, src_h);
  1976. return -EINVAL;
  1977. }
  1978. }
  1979. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1980. return 0;
  1981. }
  1982. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1983. {
  1984. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1985. }
  1986. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1987. struct sde_plane_state *pstate, struct sde_rect *dst,
  1988. u32 src_w, u32 src_h)
  1989. {
  1990. int ret = 0;
  1991. u32 min_ratio_numer, min_ratio_denom;
  1992. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1993. bool pd_x;
  1994. bool pd_y;
  1995. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1996. return ret;
  1997. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1998. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1999. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  2000. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2001. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2002. SDE_ERROR_PLANE(psde,
  2003. "hw does not support pre-downscale X: 0x%x\n",
  2004. psde->features);
  2005. ret = -EINVAL;
  2006. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2007. SDE_ERROR_PLANE(psde,
  2008. "hw does not support pre-downscale Y: 0x%x\n",
  2009. psde->features);
  2010. ret = -EINVAL;
  2011. } else if (!min_ratio_numer || !min_ratio_denom) {
  2012. SDE_ERROR_PLANE(psde,
  2013. "min downscale ratio not set! %u / %u\n",
  2014. min_ratio_numer, min_ratio_denom);
  2015. ret = -EINVAL;
  2016. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2017. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2018. min_ratio_denom))) {
  2019. SDE_ERROR_PLANE(psde,
  2020. "failed min downscale-x check %u->%u, %u/%u\n",
  2021. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2022. ret = -EINVAL;
  2023. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2024. min_ratio_denom))) {
  2025. SDE_ERROR_PLANE(psde,
  2026. "failed min downscale-y check %u->%u, %u/%u\n",
  2027. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2028. ret = -EINVAL;
  2029. }
  2030. return ret;
  2031. }
  2032. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2033. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2034. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2035. u32 *max_numer_h, u32 *max_denom_h)
  2036. {
  2037. bool rotated, has_predown, default_scale;
  2038. const struct sde_sspp_sub_blks *sblk;
  2039. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2040. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2041. sblk = psde->pipe_sblk;
  2042. *max_numer_w = sblk->maxdwnscale;
  2043. *max_denom_w = 1;
  2044. *max_numer_h = sblk->maxdwnscale;
  2045. *max_denom_h = 1;
  2046. has_predown = _sde_plane_has_pre_downscale(psde);
  2047. if (has_predown)
  2048. pd = &pstate->pre_down;
  2049. default_scale = psde->debugfs_default_scale ||
  2050. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2051. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2052. /**
  2053. * Inline rotation has different max vertical downscaling limits since
  2054. * the source-width becomes the scaler's pre-downscaled source-height.
  2055. **/
  2056. if (rotated) {
  2057. if (pd != NULL && rt_client && has_predown) {
  2058. if (default_scale)
  2059. pd->pre_downscale_x_0 = (src_h >
  2060. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2061. *max_numer_h = pd->pre_downscale_x_0 ?
  2062. sblk->in_rot_maxdwnscale_rt_num :
  2063. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2064. *max_denom_h = pd->pre_downscale_x_0 ?
  2065. sblk->in_rot_maxdwnscale_rt_denom :
  2066. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2067. } else if (rt_client) {
  2068. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2069. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2070. } else {
  2071. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2072. }
  2073. }
  2074. }
  2075. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2076. struct sde_plane *psde, const struct sde_format *fmt,
  2077. struct sde_plane_state *pstate, struct sde_rect *src,
  2078. struct sde_rect *dst, u32 width, u32 height)
  2079. {
  2080. int ret = 0;
  2081. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2082. uint32_t scaler_src_w, scaler_src_h;
  2083. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2084. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2085. uint32_t max_upscale, max_linewidth;
  2086. bool inline_rotation, rt_client;
  2087. struct drm_crtc *crtc;
  2088. struct drm_crtc_state *new_cstate;
  2089. const struct sde_sspp_sub_blks *sblk;
  2090. if (!state || !state->state || !state->crtc) {
  2091. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2092. return -EINVAL;
  2093. }
  2094. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2095. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2096. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2097. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2098. /* with inline rotator, the source of the scaler is post-rotated */
  2099. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2100. if (inline_rotation) {
  2101. scaler_src_w = src_deci_h;
  2102. scaler_src_h = src_deci_w;
  2103. } else {
  2104. scaler_src_w = src_deci_w;
  2105. scaler_src_h = src_deci_h;
  2106. }
  2107. sblk = psde->pipe_sblk;
  2108. max_upscale = sblk->maxupscale;
  2109. if (inline_rotation)
  2110. max_linewidth = sblk->in_rot_maxheight;
  2111. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2112. max_linewidth = sblk->scaling_linewidth;
  2113. else
  2114. max_linewidth = sblk->maxlinewidth;
  2115. crtc = state->crtc;
  2116. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2117. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2118. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2119. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2120. &max_downscale_num_h, &max_downscale_denom_h);
  2121. /* decimation validation */
  2122. if ((deci_w || deci_h)
  2123. && ((deci_w > sblk->maxhdeciexp)
  2124. || (deci_h > sblk->maxvdeciexp))) {
  2125. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2126. ret = -EINVAL;
  2127. } else if ((deci_w || deci_h)
  2128. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2129. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2130. ret = -EINVAL;
  2131. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2132. ((src->w != dst->w) || (src->h != dst->h))) {
  2133. SDE_ERROR_PLANE(psde,
  2134. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2135. src->w, src->h, dst->w, dst->h);
  2136. ret = -EINVAL;
  2137. /* check scaler source width */
  2138. } else if (scaler_src_w > max_linewidth) {
  2139. SDE_ERROR_PLANE(psde,
  2140. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2141. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2142. ret = -E2BIG;
  2143. /* check max scaler capability */
  2144. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2145. ((scaler_src_h * max_upscale) < dst->h) ||
  2146. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2147. < scaler_src_w) ||
  2148. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2149. < scaler_src_h)) {
  2150. SDE_ERROR_PLANE(psde,
  2151. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2152. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2153. inline_rotation, max_downscale_num_w,
  2154. max_downscale_denom_w, max_downscale_num_h,
  2155. max_downscale_denom_h);
  2156. ret = -E2BIG;
  2157. /* check inline pre-downscale support */
  2158. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2159. pstate, dst, src_deci_w, src_deci_h)) {
  2160. ret = -EINVAL;
  2161. /* QSEED validation */
  2162. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2163. width, height, src->w, src->h,
  2164. deci_w, deci_h)) {
  2165. ret = -EINVAL;
  2166. }
  2167. return ret;
  2168. }
  2169. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2170. struct sde_plane_state *pstate, struct sde_rect *src,
  2171. const struct sde_format *fmt, int ret)
  2172. {
  2173. /* check excl rect configs */
  2174. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2175. struct sde_rect intersect;
  2176. /*
  2177. * Check exclusion rect against src rect.
  2178. * it must intersect with source rect.
  2179. */
  2180. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2181. if (intersect.w != pstate->excl_rect.w ||
  2182. intersect.h != pstate->excl_rect.h ||
  2183. SDE_FORMAT_IS_YUV(fmt)) {
  2184. SDE_ERROR_PLANE(psde,
  2185. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2186. pstate->excl_rect.x, pstate->excl_rect.y,
  2187. pstate->excl_rect.w, pstate->excl_rect.h,
  2188. src->x, src->y, src->w, src->h,
  2189. (char *)&fmt->base.pixel_format);
  2190. ret = -EINVAL;
  2191. }
  2192. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2193. pstate->excl_rect.x, pstate->excl_rect.y,
  2194. pstate->excl_rect.w, pstate->excl_rect.h);
  2195. }
  2196. return ret;
  2197. }
  2198. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2199. struct drm_plane_state *state)
  2200. {
  2201. struct sde_kms *sde_kms;
  2202. struct sde_splash_display *splash_display;
  2203. int i;
  2204. sde_kms = _sde_plane_get_kms(&psde->base);
  2205. if (!sde_kms || !state->crtc)
  2206. return 0;
  2207. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2208. splash_display = &sde_kms->splash_data.splash_display[i];
  2209. if (splash_display && splash_display->cont_splash_enabled &&
  2210. splash_display->encoder &&
  2211. state->crtc != splash_display->encoder->crtc) {
  2212. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2213. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2214. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2215. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2216. psde->pipe,
  2217. splash_display->encoder->crtc->base.id);
  2218. return -EINVAL;
  2219. }
  2220. }
  2221. }
  2222. return 0;
  2223. }
  2224. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2225. const struct sde_format *fmt,
  2226. struct sde_rect src, struct sde_rect dst,
  2227. u32 width, u32 height)
  2228. {
  2229. int ret = 0;
  2230. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2231. if (SDE_FORMAT_IS_YUV(fmt) &&
  2232. (!(psde->features & SDE_SSPP_SCALER) ||
  2233. !(psde->features & (BIT(SDE_SSPP_CSC)
  2234. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2235. SDE_ERROR_PLANE(psde,
  2236. "plane doesn't have scaler/csc for yuv\n");
  2237. ret = -EINVAL;
  2238. /* check src bounds */
  2239. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2240. src.w < min_src_size || src.h < min_src_size ||
  2241. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2242. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2243. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2244. src.x, src.y, src.w, src.h);
  2245. ret = -E2BIG;
  2246. /* valid yuv image */
  2247. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2248. (src.w & 0x1) || (src.h & 0x1))) {
  2249. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2250. src.x, src.y, src.w, src.h);
  2251. ret = -EINVAL;
  2252. /* min dst support */
  2253. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2254. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2255. dst.x, dst.y, dst.w, dst.h);
  2256. ret = -EINVAL;
  2257. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2258. !psde->catalog->ubwc_rev) {
  2259. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2260. ret = -EINVAL;
  2261. }
  2262. return ret;
  2263. }
  2264. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2265. struct drm_plane_state *state)
  2266. {
  2267. int ret = 0;
  2268. struct sde_plane *psde;
  2269. struct sde_plane_state *pstate;
  2270. const struct msm_format *msm_fmt;
  2271. const struct sde_format *fmt;
  2272. struct sde_rect src, dst;
  2273. bool q16_data = true;
  2274. struct drm_framebuffer *fb;
  2275. u32 width;
  2276. u32 height;
  2277. psde = to_sde_plane(plane);
  2278. pstate = to_sde_plane_state(state);
  2279. if (!psde->pipe_sblk) {
  2280. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2281. return -EINVAL;
  2282. }
  2283. /* src values are in Q16 fixed point, convert to integer */
  2284. POPULATE_RECT(&src, state->src_x, state->src_y,
  2285. state->src_w, state->src_h, q16_data);
  2286. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2287. state->crtc_h, !q16_data);
  2288. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2289. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2290. if (!sde_plane_enabled(state))
  2291. goto modeset_update;
  2292. fb = state->fb;
  2293. width = fb ? state->fb->width : 0x0;
  2294. height = fb ? state->fb->height : 0x0;
  2295. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2296. plane->base.id,
  2297. pstate->rotation,
  2298. width, height,
  2299. fb ? (char *) &state->fb->format->format : 0x0,
  2300. fb ? state->fb->modifier : 0x0);
  2301. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2302. state->src_w >> 16, state->src_h >> 16,
  2303. state->src_x >> 16, state->src_y >> 16,
  2304. state->crtc_w, state->crtc_h,
  2305. state->crtc_x, state->crtc_y);
  2306. msm_fmt = msm_framebuffer_format(fb);
  2307. fmt = to_sde_format(msm_fmt);
  2308. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2309. height);
  2310. if (ret)
  2311. return ret;
  2312. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2313. &src, &dst, width, height);
  2314. if (ret)
  2315. return ret;
  2316. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2317. &src, fmt, ret);
  2318. if (ret)
  2319. return ret;
  2320. ret = _sde_plane_validate_shared_crtc(psde, state);
  2321. if (ret)
  2322. return ret;
  2323. pstate->const_alpha_en = fmt->alpha_enable &&
  2324. (SDE_DRM_BLEND_OP_OPAQUE !=
  2325. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2326. (pstate->stage != SDE_STAGE_0);
  2327. modeset_update:
  2328. if (!ret)
  2329. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2330. state, plane->state);
  2331. return ret;
  2332. }
  2333. static int _sde_plane_atomic_check(struct drm_plane *plane,
  2334. struct drm_plane_state *state)
  2335. {
  2336. int ret = 0;
  2337. struct sde_plane *psde;
  2338. struct sde_plane_state *pstate;
  2339. psde = to_sde_plane(plane);
  2340. pstate = to_sde_plane_state(state);
  2341. SDE_DEBUG_PLANE(psde, "\n");
  2342. ret = sde_plane_rot_atomic_check(plane, state);
  2343. if (ret)
  2344. goto exit;
  2345. ret = sde_plane_sspp_atomic_check(plane, state);
  2346. exit:
  2347. return ret;
  2348. }
  2349. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2350. static int sde_plane_atomic_check(struct drm_plane *plane,
  2351. struct drm_atomic_state *atomic_state)
  2352. {
  2353. struct drm_plane_state *state = NULL;
  2354. if (!plane || !atomic_state) {
  2355. SDE_ERROR("invalid arg(s), plane %d atomic_state %d\n",
  2356. !plane, !atomic_state);
  2357. return -EINVAL;
  2358. }
  2359. state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2360. return _sde_plane_atomic_check(plane, state);
  2361. }
  2362. #else
  2363. static int sde_plane_atomic_check(struct drm_plane *plane,
  2364. struct drm_plane_state *state)
  2365. {
  2366. if (!plane || !state) {
  2367. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2368. !plane, !state);
  2369. return -EINVAL;
  2370. }
  2371. return _sde_plane_atomic_check(plane, state);
  2372. }
  2373. #endif
  2374. void sde_plane_flush(struct drm_plane *plane)
  2375. {
  2376. struct sde_plane *psde;
  2377. struct sde_plane_state *pstate;
  2378. if (!plane || !plane->state) {
  2379. SDE_ERROR("invalid plane\n");
  2380. return;
  2381. }
  2382. psde = to_sde_plane(plane);
  2383. pstate = to_sde_plane_state(plane->state);
  2384. /*
  2385. * These updates have to be done immediately before the plane flush
  2386. * timing, and may not be moved to the atomic_update/mode_set functions.
  2387. */
  2388. if (psde->is_error)
  2389. /* force white frame with 100% alpha pipe output on error */
  2390. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2391. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2392. /* force 100% alpha */
  2393. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2394. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2395. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2396. /* flag h/w flush complete */
  2397. if (plane->state)
  2398. pstate->pending = false;
  2399. }
  2400. /**
  2401. * sde_plane_set_error: enable/disable error condition
  2402. * @plane: pointer to drm_plane structure
  2403. */
  2404. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2405. {
  2406. struct sde_plane *psde;
  2407. if (!plane)
  2408. return;
  2409. psde = to_sde_plane(plane);
  2410. psde->is_error = error;
  2411. }
  2412. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2413. struct sde_plane_state *pstate)
  2414. {
  2415. struct drm_plane_state *state = psde->base.state;
  2416. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2417. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2418. bool prev_rd_en = cfg->rd_en;
  2419. u32 cache_flag, cache_rd_type, cache_wr_type;
  2420. enum sde_sys_cache_state cache_state;
  2421. if (!state->fb) {
  2422. SDE_ERROR("invalid fb on plane %d\n", DRMID(&psde->base));
  2423. return;
  2424. }
  2425. cache_state = pstate->static_cache_state;
  2426. msm_framebuffer_get_cache_hint(state->fb, &cache_flag, &cache_rd_type, &cache_wr_type);
  2427. cfg->rd_en = false;
  2428. cfg->rd_scid = 0x0;
  2429. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2430. /*
  2431. * if condition handles static display legacy path, where internal state machine is
  2432. * transitioning the "cache_state" variable to program the LLCC cache through
  2433. * SSPP hardware using SDE_SYS_CACHE_DISP SCID.
  2434. * else condition handles static display and IWE path, were the frame is programmed to
  2435. * LLCC cache through WB/CWB path and read back by SSPP hardware. The FB cache hints are
  2436. * used to pass information on which SCID to use during read path and LLCC cache to
  2437. * keep active.
  2438. */
  2439. if (test_bit(SDE_SYS_CACHE_DISP, psde->catalog->sde_sys_cache_type_map)
  2440. && ((cache_state == CACHE_STATE_FRAME_WRITE)
  2441. || (cache_state == CACHE_STATE_FRAME_READ))) {
  2442. cfg->type = pstate->static_cache_type;
  2443. cfg->rd_en = true;
  2444. cfg->rd_scid = sc_cfg[cfg->type].llcc_scid;
  2445. if (test_bit(SDE_FEATURE_SYS_CACHE_NSE, psde->catalog->features)) {
  2446. cfg->rd_noallocate = false;
  2447. pstate->static_cache_state = CACHE_STATE_NORMAL;
  2448. } else {
  2449. cfg->rd_noallocate = (cache_state == CACHE_STATE_FRAME_READ);
  2450. }
  2451. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2452. } else if (test_bit(cache_rd_type, psde->catalog->sde_sys_cache_type_map) && cache_flag) {
  2453. cfg->rd_en = true;
  2454. cfg->type = cache_rd_type;
  2455. cfg->rd_scid = sc_cfg[cache_rd_type].llcc_scid;
  2456. cfg->rd_noallocate = false;
  2457. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2458. cache_flag = MSM_FB_CACHE_READ_EN;
  2459. msm_framebuffer_set_cache_hint(state->fb, cache_flag, cache_rd_type, cache_wr_type);
  2460. }
  2461. if (!cfg->rd_en && !prev_rd_en)
  2462. return;
  2463. SDE_EVT32(DRMID(&psde->base), cfg->type, cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate,
  2464. cfg->flags, cache_state, cache_flag, cache_rd_type, cache_wr_type,
  2465. state->fb->base.id);
  2466. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2467. }
  2468. void sde_plane_static_img_control(struct drm_plane *plane,
  2469. enum sde_sys_cache_state state, enum sde_sys_cache_type type)
  2470. {
  2471. struct sde_plane *psde;
  2472. struct sde_plane_state *pstate;
  2473. if (!plane || !plane->state) {
  2474. SDE_ERROR("invalid plane\n");
  2475. return;
  2476. }
  2477. psde = to_sde_plane(plane);
  2478. pstate = to_sde_plane_state(plane->state);
  2479. pstate->static_cache_state = state;
  2480. pstate->static_cache_type = type;
  2481. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2482. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2483. }
  2484. static void _sde_plane_map_prop_to_dirty_bits(void)
  2485. {
  2486. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2487. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2488. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2489. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2490. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2491. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2492. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2493. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2494. plane_prop_array[PLANE_PROP_ZPOS] =
  2495. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2496. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2497. SDE_PLANE_DIRTY_RECTS;
  2498. plane_prop_array[PLANE_PROP_CSC_V1] =
  2499. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2500. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2501. SDE_PLANE_DIRTY_FORMAT;
  2502. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2503. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2504. SDE_PLANE_DIRTY_ALL;
  2505. /* no special action required */
  2506. plane_prop_array[PLANE_PROP_INFO] =
  2507. plane_prop_array[PLANE_PROP_ALPHA] =
  2508. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2509. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2510. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2511. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2512. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2513. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2514. SDE_PLANE_DIRTY_PERF;
  2515. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2516. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2517. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2518. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2519. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2520. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2521. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2522. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2523. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2524. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2525. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2526. SDE_PLANE_DIRTY_ALL;
  2527. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2528. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2529. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2530. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2531. }
  2532. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2533. struct sde_rect *src, struct sde_rect *dst)
  2534. {
  2535. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2536. u32 downscale = (src->h * 1000)/dst->h;
  2537. return (downscale > max_downscale) ? false : true;
  2538. }
  2539. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2540. struct sde_plane *psde, struct sde_plane_state *pstate,
  2541. struct sde_rect *src, struct sde_rect *dst)
  2542. {
  2543. struct sde_hw_pipe_uidle_cfg cfg;
  2544. u32 line_time = sde_crtc_get_line_time(crtc);
  2545. u32 fal1_target_idle_time_ns =
  2546. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2547. u32 fal10_target_idle_time_ns =
  2548. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2549. u32 fal10_threshold =
  2550. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2551. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2552. fal1_target_idle_time_ns) {
  2553. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2554. cfg.fal10_threshold = fal10_threshold;
  2555. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2556. cfg.fal1_threshold = min(1 +
  2557. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2558. psde->catalog->uidle_cfg.fal1_max_threshold);
  2559. cfg.fal_allowed_threshold = fal10_threshold +
  2560. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2561. cfg.fill_level_scale = 0;
  2562. /*
  2563. * if uidle fill scale is supported, determing the scale value
  2564. * and adjust fal10 thresholds to their scaled values.
  2565. * fal1 thresholds and fal_allowed are not scaled.
  2566. */
  2567. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2568. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2569. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2570. u32 fl_scale = fl_require / fal10_threshold;
  2571. u32 fal10_threshold_noscale;
  2572. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2573. if (cfg.fill_level_scale) {
  2574. fal10_threshold_noscale = fal10_threshold *
  2575. 32/cfg.fill_level_scale;
  2576. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2577. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2578. }
  2579. }
  2580. } else {
  2581. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2582. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2583. fal1_target_idle_time_ns);
  2584. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2585. }
  2586. SDE_DEBUG_PLANE(psde,
  2587. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2588. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2589. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2590. cfg.fill_level_scale);
  2591. SDE_DEBUG_PLANE(psde,
  2592. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2593. line_time, fal1_target_idle_time_ns,
  2594. fal10_target_idle_time_ns,
  2595. psde->catalog->uidle_cfg.max_dwnscale);
  2596. SDE_EVT32_VERBOSE(cfg.enable,
  2597. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2598. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2599. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2600. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2601. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2602. psde->pipe_hw->ops.setup_uidle(
  2603. psde->pipe_hw, &cfg,
  2604. pstate->multirect_index);
  2605. }
  2606. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2607. struct sde_plane_state *pstate)
  2608. {
  2609. bool enable = false;
  2610. int mode = sde_plane_get_property(pstate,
  2611. PLANE_PROP_FB_TRANSLATION_MODE);
  2612. if ((mode == SDE_DRM_FB_SEC) ||
  2613. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2614. enable = true;
  2615. /* update secure session flag */
  2616. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2617. pstate->multirect_index,
  2618. enable);
  2619. }
  2620. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2621. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2622. {
  2623. const struct sde_format *fmt;
  2624. const struct msm_format *msm_fmt;
  2625. struct sde_plane *psde;
  2626. struct drm_plane_state *state;
  2627. struct sde_plane_state *pstate;
  2628. struct sde_rect src, dst;
  2629. const struct sde_rect *crtc_roi;
  2630. bool q16_data = true;
  2631. int idx;
  2632. psde = to_sde_plane(plane);
  2633. state = plane->state;
  2634. pstate = to_sde_plane_state(state);
  2635. msm_fmt = msm_framebuffer_format(fb);
  2636. if (!msm_fmt) {
  2637. SDE_ERROR("crtc%d plane%d: null format\n",
  2638. DRMID(crtc), DRMID(plane));
  2639. return;
  2640. }
  2641. fmt = to_sde_format(msm_fmt);
  2642. POPULATE_RECT(&src, state->src_x, state->src_y,
  2643. state->src_w, state->src_h, q16_data);
  2644. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2645. state->crtc_w, state->crtc_h, !q16_data);
  2646. SDE_DEBUG_PLANE(psde,
  2647. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2648. fb->base.id, src.x, src.y, src.w, src.h,
  2649. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2650. (char *)&fmt->base.pixel_format,
  2651. SDE_FORMAT_IS_UBWC(fmt));
  2652. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2653. BIT(SDE_DRM_DEINTERLACE)) {
  2654. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2655. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2656. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2657. src.h /= 2;
  2658. src.y = DIV_ROUND_UP(src.y, 2);
  2659. src.y &= ~0x1;
  2660. }
  2661. /*
  2662. * adjust layer mixer position of the sspp in the presence
  2663. * of a partial update to the active lm origin
  2664. */
  2665. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2666. dst.x -= crtc_roi->x;
  2667. dst.y -= crtc_roi->y;
  2668. /* check for UIDLE */
  2669. if (psde->pipe_hw->ops.setup_uidle)
  2670. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2671. psde->pipe_cfg.src_rect = src;
  2672. psde->pipe_cfg.dst_rect = dst;
  2673. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2674. _sde_plane_setup_panel_stacking(psde, pstate);
  2675. /* check for color fill */
  2676. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2677. PLANE_PROP_COLOR_FILL);
  2678. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2679. /* skip remaining processing on color fill */
  2680. pstate->dirty = 0x0;
  2681. } else if (psde->pipe_hw->ops.setup_rects) {
  2682. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2683. &psde->pipe_cfg,
  2684. pstate->multirect_index);
  2685. }
  2686. if (psde->pipe_hw->ops.setup_pe &&
  2687. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2688. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2689. &psde->pixel_ext);
  2690. /**
  2691. * when programmed in multirect mode, scalar block will be
  2692. * bypassed. Still we need to update alpha and bitwidth
  2693. * ONLY for RECT0
  2694. */
  2695. if (psde->pipe_hw->ops.setup_scaler &&
  2696. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2697. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2698. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2699. &psde->pipe_cfg, &psde->pixel_ext,
  2700. &psde->scaler3_cfg);
  2701. }
  2702. /* update excl rect */
  2703. if (psde->pipe_hw->ops.setup_excl_rect)
  2704. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2705. &pstate->excl_rect,
  2706. pstate->multirect_index);
  2707. /* enable multirect config of corresponding rect */
  2708. if (psde->pipe_hw->ops.update_multirect)
  2709. psde->pipe_hw->ops.update_multirect(
  2710. psde->pipe_hw,
  2711. true,
  2712. pstate->multirect_index,
  2713. pstate->multirect_mode);
  2714. /* update line insertion */
  2715. if (pstate->lineinsertion_feature && psde->pipe_hw->ops.setup_line_insertion)
  2716. psde->pipe_hw->ops.setup_line_insertion(psde->pipe_hw,
  2717. pstate->multirect_index,
  2718. &pstate->line_insertion_cfg);
  2719. }
  2720. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2721. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2722. {
  2723. uint32_t src_flags = 0;
  2724. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2725. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2726. src_flags |= SDE_SSPP_FLIP_LR;
  2727. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2728. src_flags |= SDE_SSPP_FLIP_UD;
  2729. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2730. src_flags |= SDE_SSPP_ROT_90;
  2731. /* update format */
  2732. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2733. pstate->const_alpha_en, src_flags,
  2734. pstate->multirect_index);
  2735. if (psde->pipe_hw->ops.setup_cdp) {
  2736. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2737. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2738. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2739. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2740. cdp_cfg->ubwc_meta_enable =
  2741. SDE_FORMAT_IS_UBWC(fmt);
  2742. cdp_cfg->tile_amortize_enable =
  2743. SDE_FORMAT_IS_UBWC(fmt) ||
  2744. SDE_FORMAT_IS_TILE(fmt);
  2745. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2746. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2747. pstate->multirect_index);
  2748. }
  2749. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2750. /* update csc */
  2751. if (SDE_FORMAT_IS_YUV(fmt))
  2752. _sde_plane_setup_csc(psde);
  2753. else
  2754. psde->csc_ptr = 0;
  2755. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2756. uint32_t pma_mode = 0;
  2757. if (fmt->alpha_enable)
  2758. pma_mode = (uint32_t) sde_plane_get_property(
  2759. pstate, PLANE_PROP_INVERSE_PMA);
  2760. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2761. pstate->multirect_index, pma_mode);
  2762. }
  2763. if (psde->pipe_hw->ops.setup_dgm_csc)
  2764. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2765. pstate->multirect_index, psde->csc_usr_ptr);
  2766. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2767. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2768. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2769. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2770. else
  2771. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2772. pstate->multirect_index, NULL);
  2773. }
  2774. }
  2775. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2776. {
  2777. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2778. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2779. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2780. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2781. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2782. &psde->sharp_cfg);
  2783. }
  2784. static void _sde_plane_update_properties(struct drm_plane *plane,
  2785. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2786. {
  2787. uint32_t nplanes;
  2788. const struct msm_format *msm_fmt;
  2789. const struct sde_format *fmt;
  2790. struct sde_plane *psde;
  2791. struct drm_plane_state *state;
  2792. struct sde_plane_state *pstate;
  2793. psde = to_sde_plane(plane);
  2794. state = plane->state;
  2795. pstate = to_sde_plane_state(state);
  2796. if (!pstate) {
  2797. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2798. return;
  2799. }
  2800. msm_fmt = msm_framebuffer_format(fb);
  2801. if (!msm_fmt) {
  2802. SDE_ERROR("crtc%d plane%d: null format\n",
  2803. DRMID(crtc), DRMID(plane));
  2804. return;
  2805. }
  2806. fmt = to_sde_format(msm_fmt);
  2807. nplanes = fmt->num_planes;
  2808. /* update secure session flag */
  2809. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2810. _sde_plane_update_secure_session(psde, pstate);
  2811. /* update roi config */
  2812. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2813. _sde_plane_update_roi_config(plane, crtc, fb);
  2814. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2815. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2816. psde->pipe_hw->ops.setup_format)
  2817. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2818. sde_color_process_plane_setup(plane);
  2819. /* update sharpening */
  2820. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2821. psde->pipe_hw->ops.setup_sharpening)
  2822. _sde_plane_update_sharpening(psde);
  2823. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2824. SDE_PLANE_DIRTY_FORMAT))
  2825. _sde_plane_set_qos_lut(plane, crtc, fb);
  2826. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2827. _sde_plane_set_ot_limit(plane, crtc);
  2828. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2829. _sde_plane_set_ts_prefill(plane, pstate);
  2830. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2831. _sde_plane_set_qos_remap(plane);
  2832. /* clear dirty */
  2833. pstate->dirty = 0x0;
  2834. }
  2835. static void _sde_plane_check_lut_dirty(struct sde_plane *psde,
  2836. struct sde_plane_state *pstate)
  2837. {
  2838. /**
  2839. * Valid configuration if scaler is not enabled or
  2840. * lut flag is set
  2841. */
  2842. if (pstate->scaler3_cfg.lut_flag || !pstate->scaler3_cfg.enable)
  2843. return;
  2844. pstate->scaler3_cfg.lut_flag = psde->cached_lut_flag;
  2845. SDE_EVT32(DRMID(&psde->base), pstate->scaler3_cfg.lut_flag, SDE_EVTLOG_ERROR);
  2846. }
  2847. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2848. struct drm_plane_state *old_state)
  2849. {
  2850. struct sde_plane *psde;
  2851. struct drm_plane_state *state;
  2852. struct sde_plane_state *pstate;
  2853. struct sde_plane_state *old_pstate;
  2854. struct drm_crtc *crtc;
  2855. struct drm_framebuffer *fb;
  2856. int idx;
  2857. int dirty_prop_flag;
  2858. bool is_rt;
  2859. if (!plane) {
  2860. SDE_ERROR("invalid plane\n");
  2861. return -EINVAL;
  2862. } else if (!plane->state) {
  2863. SDE_ERROR("invalid plane state\n");
  2864. return -EINVAL;
  2865. } else if (!old_state) {
  2866. SDE_ERROR("invalid old state\n");
  2867. return -EINVAL;
  2868. }
  2869. psde = to_sde_plane(plane);
  2870. state = plane->state;
  2871. pstate = to_sde_plane_state(state);
  2872. old_pstate = to_sde_plane_state(old_state);
  2873. crtc = state->crtc;
  2874. fb = state->fb;
  2875. if (!crtc || !fb) {
  2876. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2877. !crtc, !fb);
  2878. return -EINVAL;
  2879. }
  2880. SDE_DEBUG(
  2881. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2882. plane->base.id,
  2883. state->fb->width, state->fb->height,
  2884. (char *) &state->fb->format->format,
  2885. state->fb->modifier,
  2886. state->src_w >> 16, state->src_h >> 16,
  2887. state->src_x >> 16, state->src_y >> 16,
  2888. pstate->rotation,
  2889. state->crtc_w, state->crtc_h,
  2890. state->crtc_x, state->crtc_y);
  2891. /* Caching the valid lut flag in sde plane */
  2892. if (pstate->scaler3_cfg.enable && pstate->scaler3_cfg.lut_flag)
  2893. psde->cached_lut_flag = pstate->scaler3_cfg.lut_flag;
  2894. /* force reprogramming of all the parameters, if the flag is set */
  2895. if (psde->revalidate) {
  2896. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2897. plane->base.id);
  2898. _sde_plane_check_lut_dirty(psde, pstate);
  2899. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2900. psde->revalidate = false;
  2901. }
  2902. /* determine what needs to be refreshed */
  2903. mutex_lock(&psde->property_info.property_lock);
  2904. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2905. &pstate->property_state)) >= 0) {
  2906. dirty_prop_flag = plane_prop_array[idx];
  2907. pstate->dirty |= dirty_prop_flag;
  2908. }
  2909. mutex_unlock(&psde->property_info.property_lock);
  2910. /**
  2911. * since plane_atomic_check is invoked before crtc_atomic_check
  2912. * in the commit sequence, all the parameters for updating the
  2913. * plane dirty flag will not be available during
  2914. * plane_atomic_check as some features params are updated
  2915. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2916. * before sspp update.
  2917. */
  2918. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2919. old_state);
  2920. /* re-program the output rects always if partial update roi changed */
  2921. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2922. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2923. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2924. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2925. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2926. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2927. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  2928. psde->is_rt_pipe = is_rt;
  2929. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  2930. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2931. }
  2932. /* early out if nothing dirty */
  2933. if (!pstate->dirty)
  2934. return 0;
  2935. pstate->pending = true;
  2936. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2937. _sde_plane_update_properties(plane, crtc, fb);
  2938. return 0;
  2939. }
  2940. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2941. struct drm_plane_state *old_state)
  2942. {
  2943. struct sde_plane *psde;
  2944. struct drm_plane_state *state;
  2945. struct sde_plane_state *pstate;
  2946. u32 multirect_index = SDE_SSPP_RECT_0;
  2947. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2948. u32 blend_type;
  2949. if (!plane) {
  2950. SDE_ERROR("invalid plane\n");
  2951. return;
  2952. } else if (!plane->state) {
  2953. SDE_ERROR("invalid plane state\n");
  2954. return;
  2955. } else if (!old_state) {
  2956. SDE_ERROR("invalid old state\n");
  2957. return;
  2958. }
  2959. psde = to_sde_plane(plane);
  2960. state = plane->state;
  2961. pstate = to_sde_plane_state(state);
  2962. blend_type = sde_plane_get_property(pstate,
  2963. PLANE_PROP_BLEND_OP);
  2964. /* some of the color features are dependent on plane with skip blend.
  2965. * if skip blend plane is being disabled, we need to disable color properties.
  2966. */
  2967. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2968. skip_blend_plane.valid_plane = false;
  2969. skip_blend_plane.plane = SSPP_NONE;
  2970. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2971. sde_crtc_disable_cp_features(old_state->crtc);
  2972. }
  2973. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2974. pstate->multirect_mode);
  2975. pstate->pending = true;
  2976. pstate->static_cache_state = CACHE_STATE_DISABLED;
  2977. if (is_sde_plane_virtual(plane))
  2978. multirect_index = SDE_SSPP_RECT_1;
  2979. /* disable multirect config of corresponding rect */
  2980. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2981. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2982. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2983. }
  2984. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2985. static void _sde_plane_atomic_update(struct drm_plane *plane,
  2986. struct drm_plane_state *old_state)
  2987. #else
  2988. static void sde_plane_atomic_update(struct drm_plane *plane,
  2989. struct drm_plane_state *old_state)
  2990. #endif
  2991. {
  2992. struct sde_plane *psde;
  2993. struct drm_plane_state *state;
  2994. if (!plane) {
  2995. SDE_ERROR("invalid plane\n");
  2996. return;
  2997. } else if (!plane->state) {
  2998. SDE_ERROR("invalid plane state\n");
  2999. return;
  3000. }
  3001. psde = to_sde_plane(plane);
  3002. psde->is_error = false;
  3003. state = plane->state;
  3004. SDE_DEBUG_PLANE(psde, "\n");
  3005. if (!sde_plane_enabled(state)) {
  3006. _sde_plane_atomic_disable(plane, old_state);
  3007. } else {
  3008. int ret;
  3009. ret = sde_plane_sspp_atomic_update(plane, old_state);
  3010. /* atomic_check should have ensured that this doesn't fail */
  3011. WARN_ON(ret < 0);
  3012. }
  3013. }
  3014. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3015. static void sde_plane_atomic_update(struct drm_plane *plane,
  3016. struct drm_atomic_state *atomic_state)
  3017. {
  3018. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  3019. _sde_plane_atomic_update(plane, old_state);
  3020. }
  3021. #endif
  3022. void sde_plane_restore(struct drm_plane *plane)
  3023. {
  3024. struct sde_plane *psde;
  3025. if (!plane || !plane->state) {
  3026. SDE_ERROR("invalid plane\n");
  3027. return;
  3028. }
  3029. psde = to_sde_plane(plane);
  3030. /*
  3031. * Revalidate is only true here if idle PC occurred and
  3032. * there is no plane state update in current commit cycle.
  3033. */
  3034. if (!psde->revalidate)
  3035. return;
  3036. SDE_DEBUG_PLANE(psde, "\n");
  3037. /* last plane state is same as current state */
  3038. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3039. _sde_plane_atomic_update(plane, plane->state);
  3040. #else
  3041. sde_plane_atomic_update(plane, plane->state);
  3042. #endif
  3043. }
  3044. bool sde_plane_is_cache_required(struct drm_plane *plane,
  3045. enum sde_sys_cache_type type)
  3046. {
  3047. struct sde_plane_state *pstate;
  3048. u32 cache_flag, cache_rd_type, cache_wr_type;
  3049. if (!plane || !plane->state) {
  3050. SDE_ERROR("invalid plane\n");
  3051. return false;
  3052. }
  3053. pstate = to_sde_plane_state(plane->state);
  3054. msm_framebuffer_get_cache_hint(plane->state->fb, &cache_flag, &cache_rd_type,
  3055. &cache_wr_type);
  3056. /* check if llcc is required for the plane */
  3057. if (pstate->sc_cfg.rd_en && ((pstate->sc_cfg.type == type)
  3058. || (cache_flag && (cache_rd_type == type))
  3059. || (cache_flag && (cache_wr_type == type)))) {
  3060. SDE_EVT32_VERBOSE(DRMID(plane), type, pstate->sc_cfg.rd_en, pstate->sc_cfg.type,
  3061. cache_flag, cache_rd_type, cache_wr_type,
  3062. plane->state->fb->base.id);
  3063. return true;
  3064. }
  3065. return false;
  3066. }
  3067. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3068. {
  3069. char feature_name[256];
  3070. if (psde->pipe_sblk->maxhdeciexp) {
  3071. msm_property_install_range(&psde->property_info,
  3072. "h_decimate", 0x0, 0,
  3073. psde->pipe_sblk->maxhdeciexp, 0,
  3074. PLANE_PROP_H_DECIMATE);
  3075. }
  3076. if (psde->pipe_sblk->maxvdeciexp) {
  3077. msm_property_install_range(&psde->property_info,
  3078. "v_decimate", 0x0, 0,
  3079. psde->pipe_sblk->maxvdeciexp, 0,
  3080. PLANE_PROP_V_DECIMATE);
  3081. }
  3082. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3083. msm_property_install_range(
  3084. &psde->property_info, "scaler_v2",
  3085. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3086. msm_property_install_blob(&psde->property_info,
  3087. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3088. msm_property_install_blob(&psde->property_info,
  3089. "lut_cir", 0,
  3090. PLANE_PROP_SCALER_LUT_CIR);
  3091. msm_property_install_blob(&psde->property_info,
  3092. "lut_sep", 0,
  3093. PLANE_PROP_SCALER_LUT_SEP);
  3094. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3095. msm_property_install_range(
  3096. &psde->property_info, "scaler_v2",
  3097. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3098. msm_property_install_blob(&psde->property_info,
  3099. "lut_sep", 0,
  3100. PLANE_PROP_SCALER_LUT_SEP);
  3101. } else if (psde->features & SDE_SSPP_SCALER) {
  3102. msm_property_install_range(
  3103. &psde->property_info, "scaler_v1", 0x0,
  3104. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3105. }
  3106. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3107. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3108. msm_property_install_volatile_range(
  3109. &psde->property_info, "csc_v1", 0x0,
  3110. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3111. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3112. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3113. "SDE_SSPP_HUE_V",
  3114. psde->pipe_sblk->hsic_blk.version >> 16);
  3115. msm_property_install_range(&psde->property_info,
  3116. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3117. PLANE_PROP_HUE_ADJUST);
  3118. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3119. "SDE_SSPP_SATURATION_V",
  3120. psde->pipe_sblk->hsic_blk.version >> 16);
  3121. msm_property_install_range(&psde->property_info,
  3122. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3123. PLANE_PROP_SATURATION_ADJUST);
  3124. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3125. "SDE_SSPP_VALUE_V",
  3126. psde->pipe_sblk->hsic_blk.version >> 16);
  3127. msm_property_install_range(&psde->property_info,
  3128. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3129. PLANE_PROP_VALUE_ADJUST);
  3130. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3131. "SDE_SSPP_CONTRAST_V",
  3132. psde->pipe_sblk->hsic_blk.version >> 16);
  3133. msm_property_install_range(&psde->property_info,
  3134. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3135. PLANE_PROP_CONTRAST_ADJUST);
  3136. }
  3137. }
  3138. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3139. struct sde_kms_info *info)
  3140. {
  3141. char feature_name[256];
  3142. bool is_master = !psde->is_virtual;
  3143. if ((is_master &&
  3144. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3145. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3146. msm_property_install_range(&psde->property_info,
  3147. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3148. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3149. }
  3150. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3151. msm_property_install_volatile_range(
  3152. &psde->property_info, "csc_dma_v1", 0x0,
  3153. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3154. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3155. }
  3156. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3157. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3158. "SDE_SSPP_SKIN_COLOR_V",
  3159. psde->pipe_sblk->memcolor_blk.version >> 16);
  3160. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3161. PLANE_PROP_SKIN_COLOR);
  3162. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3163. "SDE_SSPP_SKY_COLOR_V",
  3164. psde->pipe_sblk->memcolor_blk.version >> 16);
  3165. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3166. PLANE_PROP_SKY_COLOR);
  3167. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3168. "SDE_SSPP_FOLIAGE_COLOR_V",
  3169. psde->pipe_sblk->memcolor_blk.version >> 16);
  3170. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3171. PLANE_PROP_FOLIAGE_COLOR);
  3172. }
  3173. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3174. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3175. "SDE_VIG_3D_LUT_GAMUT_V",
  3176. psde->pipe_sblk->gamut_blk.version >> 16);
  3177. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3178. PLANE_PROP_VIG_GAMUT);
  3179. }
  3180. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3181. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3182. "SDE_VIG_1D_LUT_IGC_V",
  3183. psde->pipe_sblk->igc_blk[0].version >> 16);
  3184. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3185. PLANE_PROP_VIG_IGC);
  3186. }
  3187. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3188. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3189. "SDE_DGM_1D_LUT_IGC_V",
  3190. psde->pipe_sblk->igc_blk[0].version >> 16);
  3191. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3192. PLANE_PROP_DMA_IGC);
  3193. }
  3194. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3195. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3196. "SDE_DGM_1D_LUT_GC_V",
  3197. psde->pipe_sblk->gc_blk[0].version >> 16);
  3198. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3199. PLANE_PROP_DMA_GC);
  3200. }
  3201. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3202. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3203. "SDE_SSPP_FP16_IGC_V",
  3204. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3205. msm_property_install_range(&psde->property_info, feature_name,
  3206. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3207. }
  3208. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3209. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3210. "SDE_SSPP_FP16_GC_V",
  3211. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3212. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3213. PLANE_PROP_FP16_GC);
  3214. }
  3215. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3216. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3217. "SDE_SSPP_FP16_CSC_V",
  3218. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3219. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3220. PLANE_PROP_FP16_CSC);
  3221. }
  3222. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3223. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3224. "SDE_SSPP_FP16_UNMULT_V",
  3225. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3226. msm_property_install_range(&psde->property_info, feature_name,
  3227. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3228. }
  3229. }
  3230. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3231. u32 master_plane_id, struct sde_kms_info *info,
  3232. struct sde_mdss_cfg *catalog)
  3233. {
  3234. bool is_master = !psde->is_virtual;
  3235. const struct sde_format_extended *format_list;
  3236. u32 index;
  3237. int pipe_id;
  3238. if (is_master) {
  3239. format_list = psde->pipe_sblk->format_list;
  3240. } else {
  3241. format_list = psde->pipe_sblk->virt_format_list;
  3242. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3243. master_plane_id);
  3244. }
  3245. if (format_list) {
  3246. sde_kms_info_start(info, "pixel_formats");
  3247. while (format_list->fourcc_format) {
  3248. sde_kms_info_append_format(info,
  3249. format_list->fourcc_format,
  3250. format_list->modifier);
  3251. ++format_list;
  3252. }
  3253. sde_kms_info_stop(info);
  3254. }
  3255. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3256. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3257. sde_kms_info_add_keyint(info, "max_linewidth",
  3258. psde->pipe_sblk->maxlinewidth);
  3259. sde_kms_info_add_keyint(info, "max_upscale",
  3260. psde->pipe_sblk->maxupscale);
  3261. sde_kms_info_add_keyint(info, "max_downscale",
  3262. psde->pipe_sblk->maxdwnscale);
  3263. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3264. psde->pipe_sblk->maxhdeciexp);
  3265. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3266. psde->pipe_sblk->maxvdeciexp);
  3267. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3268. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3269. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3270. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3271. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3272. pipe_id = psde->pipe - SSPP_VIG0;
  3273. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3274. pipe_id = psde->pipe - SSPP_DMA0;
  3275. else
  3276. pipe_id = -1;
  3277. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3278. index = (master_plane_id == 0) ? 0 : 1;
  3279. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3280. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3281. sde_kms_info_add_keyint(info, "demura_block", index);
  3282. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3283. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3284. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3285. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3286. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3287. const struct sde_format_extended *inline_rot_fmt_list;
  3288. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3289. catalog->true_inline_rot_rev);
  3290. sde_kms_info_add_keyint(info,
  3291. "true_inline_dwnscale_rt",
  3292. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3293. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3294. sde_kms_info_add_keyint(info,
  3295. "true_inline_dwnscale_rt_numerator",
  3296. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3297. sde_kms_info_add_keyint(info,
  3298. "true_inline_dwnscale_rt_denominator",
  3299. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3300. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3301. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3302. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3303. psde->pipe_sblk->in_rot_maxheight);
  3304. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3305. if (inline_rot_fmt_list) {
  3306. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3307. while (inline_rot_fmt_list->fourcc_format) {
  3308. sde_kms_info_append_format(info,
  3309. inline_rot_fmt_list->fourcc_format,
  3310. inline_rot_fmt_list->modifier);
  3311. ++inline_rot_fmt_list;
  3312. }
  3313. sde_kms_info_stop(info);
  3314. }
  3315. }
  3316. }
  3317. /* helper to install properties which are common to planes and crtcs */
  3318. static void _sde_plane_install_properties(struct drm_plane *plane,
  3319. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3320. {
  3321. static const struct drm_prop_enum_list e_blend_op[] = {
  3322. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3323. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3324. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3325. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3326. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3327. };
  3328. static const struct drm_prop_enum_list e_src_config[] = {
  3329. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3330. };
  3331. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3332. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3333. {SDE_DRM_FB_SEC, "sec"},
  3334. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3335. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3336. };
  3337. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3338. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3339. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3340. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3341. };
  3342. struct sde_kms_info *info;
  3343. struct sde_plane *psde = to_sde_plane(plane);
  3344. bool is_master;
  3345. int zpos_max = 255;
  3346. int zpos_def = 0;
  3347. if (!plane || !psde) {
  3348. SDE_ERROR("invalid plane\n");
  3349. return;
  3350. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3351. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3352. !psde->pipe_hw, !psde->pipe_sblk);
  3353. return;
  3354. } else if (!catalog) {
  3355. SDE_ERROR("invalid catalog\n");
  3356. return;
  3357. }
  3358. psde->catalog = catalog;
  3359. is_master = !psde->is_virtual;
  3360. info = vzalloc(sizeof(struct sde_kms_info));
  3361. if (!info) {
  3362. SDE_ERROR("failed to allocate info memory\n");
  3363. return;
  3364. }
  3365. if (sde_is_custom_client()) {
  3366. if (catalog->mixer_count &&
  3367. catalog->mixer[0].sblk->maxblendstages) {
  3368. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3369. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3370. (zpos_max > SDE_STAGE_MAX - 1))
  3371. zpos_max = SDE_STAGE_MAX - 1;
  3372. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3373. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3374. }
  3375. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3376. /* reserve zpos == 0 for primary planes */
  3377. zpos_def = drm_plane_index(plane) + 1;
  3378. }
  3379. msm_property_install_range(&psde->property_info, "zpos",
  3380. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3381. msm_property_install_range(&psde->property_info, "alpha",
  3382. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3383. /* linux default file descriptor range on each process */
  3384. msm_property_install_range(&psde->property_info, "input_fence",
  3385. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3386. if (is_master)
  3387. _sde_plane_install_master_only_properties(psde);
  3388. else
  3389. msm_property_install_enum(&psde->property_info,
  3390. "multirect_mode", 0x0, 0, e_multirect_mode,
  3391. ARRAY_SIZE(e_multirect_mode), 0,
  3392. PLANE_PROP_MULTIRECT_MODE);
  3393. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3394. msm_property_install_volatile_range(&psde->property_info,
  3395. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3396. sde_plane_rot_install_properties(plane, catalog);
  3397. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3398. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3399. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3400. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3401. PLANE_PROP_SRC_CONFIG);
  3402. if (psde->pipe_hw->ops.setup_solidfill)
  3403. msm_property_install_range(&psde->property_info, "color_fill",
  3404. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3405. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3406. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3407. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3408. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3409. msm_property_install_blob(&psde->property_info, "capabilities",
  3410. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3411. sde_kms_info_reset(info);
  3412. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3413. catalog);
  3414. _sde_plane_install_colorproc_properties(psde, info);
  3415. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3416. info->data, SDE_KMS_INFO_DATALEN(info),
  3417. PLANE_PROP_INFO);
  3418. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3419. 0x0, 0, e_fb_translation_mode,
  3420. ARRAY_SIZE(e_fb_translation_mode), 0,
  3421. PLANE_PROP_FB_TRANSLATION_MODE);
  3422. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3423. msm_property_install_volatile_range(&psde->property_info, "ubwc_stats_roi",
  3424. 0, 0, ~0, 0, PLANE_PROP_UBWC_STATS_ROI);
  3425. vfree(info);
  3426. }
  3427. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3428. void __user *usr_ptr)
  3429. {
  3430. struct sde_drm_csc_v1 csc_v1;
  3431. int i;
  3432. if (!psde) {
  3433. SDE_ERROR("invalid plane\n");
  3434. return;
  3435. }
  3436. psde->csc_usr_ptr = NULL;
  3437. if (!usr_ptr) {
  3438. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3439. return;
  3440. }
  3441. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3442. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3443. return;
  3444. }
  3445. /* populate from user space */
  3446. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3447. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3448. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3449. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3450. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3451. }
  3452. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3453. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3454. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3455. }
  3456. psde->csc_usr_ptr = &psde->csc_cfg;
  3457. }
  3458. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3459. struct sde_plane_state *pstate, void __user *usr)
  3460. {
  3461. struct sde_drm_scaler_v1 scale_v1;
  3462. struct sde_hw_pixel_ext *pe;
  3463. int i;
  3464. if (!psde || !pstate) {
  3465. SDE_ERROR("invalid argument(s)\n");
  3466. return;
  3467. }
  3468. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3469. if (!usr) {
  3470. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3471. return;
  3472. }
  3473. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3474. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3475. return;
  3476. }
  3477. /* force property to be dirty, even if the pointer didn't change */
  3478. msm_property_set_dirty(&psde->property_info,
  3479. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3480. /* populate from user space */
  3481. pe = &pstate->pixel_ext;
  3482. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3483. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3484. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3485. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3486. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3487. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3488. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3489. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3490. }
  3491. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3492. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3493. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3494. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3495. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3496. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3497. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3498. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3499. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3500. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3501. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3502. }
  3503. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3504. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3505. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3506. }
  3507. static void _sde_plane_clear_predownscale_settings(
  3508. struct sde_plane_state *pstate)
  3509. {
  3510. pstate->pre_down.pre_downscale_x_0 = 0;
  3511. pstate->pre_down.pre_downscale_x_1 = 0;
  3512. pstate->pre_down.pre_downscale_y_0 = 0;
  3513. pstate->pre_down.pre_downscale_y_1 = 0;
  3514. }
  3515. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3516. struct sde_plane_state *pstate, void __user *usr)
  3517. {
  3518. struct sde_drm_scaler_v2 scale_v2;
  3519. struct sde_hw_pixel_ext *pe;
  3520. int i;
  3521. struct sde_hw_scaler3_cfg *cfg;
  3522. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3523. if (!psde || !pstate) {
  3524. SDE_ERROR("invalid argument(s)\n");
  3525. return;
  3526. }
  3527. cfg = &pstate->scaler3_cfg;
  3528. pd_cfg = &pstate->pre_down;
  3529. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3530. if (!usr) {
  3531. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3532. cfg->enable = 0;
  3533. _sde_plane_clear_predownscale_settings(pstate);
  3534. goto end;
  3535. }
  3536. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3537. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3538. return;
  3539. }
  3540. /* detach/ignore user data if 'disabled' */
  3541. if (!scale_v2.enable) {
  3542. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3543. cfg->enable = 0;
  3544. _sde_plane_clear_predownscale_settings(pstate);
  3545. goto end;
  3546. }
  3547. /* populate from user space */
  3548. sde_set_scaler_v2(cfg, &scale_v2);
  3549. if (_sde_plane_has_pre_downscale(psde)) {
  3550. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3551. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3552. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3553. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3554. }
  3555. pe = &pstate->pixel_ext;
  3556. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3557. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3558. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3559. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3560. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3561. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3562. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3563. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3564. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3565. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3566. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3567. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3568. }
  3569. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3570. end:
  3571. /* force property to be dirty, even if the pointer didn't change */
  3572. msm_property_set_dirty(&psde->property_info,
  3573. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3574. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3575. cfg->src_width[0], cfg->src_height[0],
  3576. cfg->dst_width, cfg->dst_height);
  3577. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3578. }
  3579. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3580. struct sde_plane_state *pstate, void __user *usr_ptr)
  3581. {
  3582. struct drm_clip_rect excl_rect_v1;
  3583. if (!psde || !pstate) {
  3584. SDE_ERROR("invalid argument(s)\n");
  3585. return;
  3586. }
  3587. if (!usr_ptr) {
  3588. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3589. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3590. return;
  3591. }
  3592. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3593. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3594. return;
  3595. }
  3596. /* populate from user space */
  3597. pstate->excl_rect.x = excl_rect_v1.x1;
  3598. pstate->excl_rect.y = excl_rect_v1.y1;
  3599. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3600. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3601. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3602. pstate->excl_rect.x, pstate->excl_rect.y,
  3603. pstate->excl_rect.w, pstate->excl_rect.h);
  3604. }
  3605. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3606. struct sde_plane_state *pstate, void __user *usr_ptr)
  3607. {
  3608. struct sde_drm_ubwc_stats_roi roi = {0};
  3609. if (!psde || !pstate) {
  3610. SDE_ERROR("invalid argument(s)\n");
  3611. return;
  3612. }
  3613. if (!usr_ptr) {
  3614. SDE_DEBUG_PLANE(psde, "ubwc roi disabled");
  3615. goto end;
  3616. }
  3617. if (copy_from_user(&roi, usr_ptr, sizeof(roi))) {
  3618. SDE_ERROR_PLANE(psde, "failed to copy ubwc stats roi");
  3619. return;
  3620. }
  3621. if (roi.y_coord0 > psde->pipe_cfg.src_rect.h || roi.y_coord1 > psde->pipe_cfg.src_rect.h) {
  3622. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3623. roi.y_coord0, roi.y_coord1, psde->pipe_cfg.src_rect.h);
  3624. memset(&roi, 0, sizeof(roi));
  3625. }
  3626. end:
  3627. SDE_EVT32(psde, roi.y_coord0, roi.y_coord1);
  3628. memcpy(&pstate->ubwc_stats_roi, &roi, sizeof(struct sde_drm_ubwc_stats_roi));
  3629. }
  3630. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3631. struct drm_plane_state *state, struct drm_property *property,
  3632. uint64_t val)
  3633. {
  3634. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3635. struct sde_plane_state *pstate;
  3636. int idx, ret = -EINVAL;
  3637. SDE_DEBUG_PLANE(psde, "\n");
  3638. if (!plane) {
  3639. SDE_ERROR("invalid plane\n");
  3640. } else if (!state) {
  3641. SDE_ERROR_PLANE(psde, "invalid state\n");
  3642. } else {
  3643. pstate = to_sde_plane_state(state);
  3644. ret = msm_property_atomic_set(&psde->property_info,
  3645. &pstate->property_state, property, val);
  3646. if (!ret) {
  3647. idx = msm_property_index(&psde->property_info,
  3648. property);
  3649. switch (idx) {
  3650. case PLANE_PROP_INPUT_FENCE:
  3651. _sde_plane_set_input_fence(psde, pstate, val);
  3652. break;
  3653. case PLANE_PROP_CSC_V1:
  3654. case PLANE_PROP_CSC_DMA_V1:
  3655. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3656. break;
  3657. case PLANE_PROP_SCALER_V1:
  3658. _sde_plane_set_scaler_v1(psde, pstate,
  3659. (void *)(uintptr_t)val);
  3660. break;
  3661. case PLANE_PROP_SCALER_V2:
  3662. _sde_plane_set_scaler_v2(psde, pstate,
  3663. (void *)(uintptr_t)val);
  3664. break;
  3665. case PLANE_PROP_EXCL_RECT_V1:
  3666. _sde_plane_set_excl_rect_v1(psde, pstate,
  3667. (void *)(uintptr_t)val);
  3668. break;
  3669. case PLANE_PROP_UBWC_STATS_ROI:
  3670. _sde_plane_set_ubwc_stats_roi(psde, pstate,
  3671. (void __user *)(uintptr_t)val);
  3672. break;
  3673. default:
  3674. /* nothing to do */
  3675. break;
  3676. }
  3677. }
  3678. }
  3679. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3680. property->name, property->base.id, val, ret);
  3681. return ret;
  3682. }
  3683. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3684. const struct drm_plane_state *state,
  3685. struct drm_property *property, uint64_t *val)
  3686. {
  3687. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3688. struct sde_plane_state *pstate;
  3689. int ret = -EINVAL;
  3690. if (!plane) {
  3691. SDE_ERROR("invalid plane\n");
  3692. } else if (!state) {
  3693. SDE_ERROR("invalid state\n");
  3694. } else {
  3695. SDE_DEBUG_PLANE(psde, "\n");
  3696. pstate = to_sde_plane_state(state);
  3697. ret = msm_property_atomic_get(&psde->property_info,
  3698. &pstate->property_state, property, val);
  3699. }
  3700. return ret;
  3701. }
  3702. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3703. struct drm_plane_state *plane_state)
  3704. {
  3705. struct sde_plane *psde;
  3706. struct sde_plane_state *pstate;
  3707. struct drm_property *drm_prop;
  3708. enum msm_mdp_plane_property prop_idx;
  3709. if (!plane || !plane_state) {
  3710. SDE_ERROR("invalid params\n");
  3711. return -EINVAL;
  3712. }
  3713. psde = to_sde_plane(plane);
  3714. pstate = to_sde_plane_state(plane_state);
  3715. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3716. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3717. uint64_t val = pstate->property_values[prop_idx].value;
  3718. uint64_t def;
  3719. int ret;
  3720. drm_prop = msm_property_index_to_drm_property(
  3721. &psde->property_info, prop_idx);
  3722. if (!drm_prop) {
  3723. /* not all props will be installed, based on caps */
  3724. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3725. prop_idx);
  3726. continue;
  3727. }
  3728. def = msm_property_get_default(&psde->property_info, prop_idx);
  3729. if (val == def)
  3730. continue;
  3731. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3732. drm_prop->name, prop_idx, val, def);
  3733. ret = sde_plane_atomic_set_property(plane, plane_state,
  3734. drm_prop, def);
  3735. if (ret) {
  3736. SDE_ERROR_PLANE(psde,
  3737. "set property failed, idx %d ret %d\n",
  3738. prop_idx, ret);
  3739. continue;
  3740. }
  3741. }
  3742. return 0;
  3743. }
  3744. static void sde_plane_destroy(struct drm_plane *plane)
  3745. {
  3746. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3747. SDE_DEBUG_PLANE(psde, "\n");
  3748. if (psde) {
  3749. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3750. if (psde->blob_info)
  3751. drm_property_blob_put(psde->blob_info);
  3752. msm_property_destroy(&psde->property_info);
  3753. mutex_destroy(&psde->lock);
  3754. /* this will destroy the states as well */
  3755. drm_plane_cleanup(plane);
  3756. if (psde->pipe_hw)
  3757. sde_hw_sspp_destroy(psde->pipe_hw);
  3758. kfree(psde);
  3759. }
  3760. }
  3761. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3762. {
  3763. struct sde_plane_state *pstate;
  3764. if (!state) {
  3765. SDE_ERROR("invalid arg state %d\n", !state);
  3766. return;
  3767. }
  3768. pstate = to_sde_plane_state(state);
  3769. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3770. SDE_DRM_FB_SEC) {
  3771. /* remove ref count for frame buffers */
  3772. if (state->fb) {
  3773. drm_framebuffer_put(state->fb);
  3774. state->fb = NULL;
  3775. }
  3776. }
  3777. }
  3778. static void sde_plane_destroy_state(struct drm_plane *plane,
  3779. struct drm_plane_state *state)
  3780. {
  3781. struct sde_plane *psde;
  3782. struct sde_plane_state *pstate;
  3783. if (!plane || !state) {
  3784. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3785. !plane, !state);
  3786. return;
  3787. }
  3788. psde = to_sde_plane(plane);
  3789. pstate = to_sde_plane_state(state);
  3790. SDE_DEBUG_PLANE(psde, "\n");
  3791. /* remove ref count for frame buffers */
  3792. if (state->fb)
  3793. drm_framebuffer_put(state->fb);
  3794. /* remove ref count for fence */
  3795. if (pstate->input_fence)
  3796. sde_sync_put(pstate->input_fence);
  3797. pstate->input_fence = 0;
  3798. /* destroy value helper */
  3799. msm_property_destroy_state(&psde->property_info, pstate,
  3800. &pstate->property_state);
  3801. }
  3802. static struct drm_plane_state *
  3803. sde_plane_duplicate_state(struct drm_plane *plane)
  3804. {
  3805. struct sde_plane *psde;
  3806. struct sde_plane_state *pstate;
  3807. struct sde_plane_state *old_state;
  3808. struct drm_property *drm_prop;
  3809. uint64_t input_fence_default;
  3810. if (!plane) {
  3811. SDE_ERROR("invalid plane\n");
  3812. return NULL;
  3813. } else if (!plane->state) {
  3814. SDE_ERROR("invalid plane state\n");
  3815. return NULL;
  3816. }
  3817. old_state = to_sde_plane_state(plane->state);
  3818. psde = to_sde_plane(plane);
  3819. if (old_state->cont_splash_populated) {
  3820. plane->state->crtc = NULL;
  3821. old_state->cont_splash_populated = false;
  3822. }
  3823. pstate = msm_property_alloc_state(&psde->property_info);
  3824. if (!pstate) {
  3825. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3826. return NULL;
  3827. }
  3828. SDE_DEBUG_PLANE(psde, "\n");
  3829. /* duplicate value helper */
  3830. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3831. &pstate->property_state, pstate->property_values);
  3832. /* clear out any input fence */
  3833. pstate->input_fence = 0;
  3834. input_fence_default = msm_property_get_default(
  3835. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3836. drm_prop = msm_property_index_to_drm_property(
  3837. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3838. if (msm_property_atomic_set(&psde->property_info,
  3839. &pstate->property_state, drm_prop,
  3840. input_fence_default))
  3841. SDE_DEBUG_PLANE(psde,
  3842. "error clearing duplicated input fence\n");
  3843. pstate->dirty = 0x0;
  3844. pstate->pending = false;
  3845. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3846. /* reset layout offset */
  3847. if (pstate->layout_offset) {
  3848. if (pstate->layout_offset > 0)
  3849. pstate->base.crtc_x += pstate->layout_offset;
  3850. pstate->layout = SDE_LAYOUT_NONE;
  3851. pstate->layout_offset = 0;
  3852. }
  3853. return &pstate->base;
  3854. }
  3855. static void sde_plane_reset(struct drm_plane *plane)
  3856. {
  3857. struct sde_plane *psde;
  3858. struct sde_plane_state *pstate;
  3859. if (!plane) {
  3860. SDE_ERROR("invalid plane\n");
  3861. return;
  3862. }
  3863. psde = to_sde_plane(plane);
  3864. SDE_DEBUG_PLANE(psde, "\n");
  3865. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3866. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3867. return;
  3868. }
  3869. /* remove previous state, if present */
  3870. if (plane->state) {
  3871. sde_plane_destroy_state(plane, plane->state);
  3872. plane->state = 0;
  3873. }
  3874. pstate = msm_property_alloc_state(&psde->property_info);
  3875. if (!pstate) {
  3876. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3877. return;
  3878. }
  3879. /* reset value helper */
  3880. msm_property_reset_state(&psde->property_info, pstate,
  3881. &pstate->property_state,
  3882. pstate->property_values);
  3883. pstate->base.plane = plane;
  3884. plane->state = &pstate->base;
  3885. }
  3886. void sde_plane_get_frame_data(struct drm_plane *plane,
  3887. struct sde_drm_plane_frame_data *data)
  3888. {
  3889. struct sde_plane *psde;
  3890. struct sde_plane_state *pstate;
  3891. struct sde_drm_ubwc_stats_data *ubwc_stats;
  3892. if (!plane) {
  3893. SDE_ERROR("invalid plane\n");
  3894. return;
  3895. }
  3896. psde = to_sde_plane(plane);
  3897. pstate = to_sde_plane_state(plane->state);
  3898. ubwc_stats = &data->ubwc_stats;
  3899. data->plane_id = DRMID(plane);
  3900. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  3901. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  3902. sizeof(struct sde_drm_ubwc_stats_roi));
  3903. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  3904. pstate->multirect_index, ubwc_stats);
  3905. }
  3906. if (psde->pipe_hw->ops.get_ubwc_error)
  3907. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3908. pstate->multirect_index);
  3909. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  3910. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3911. if (psde->pipe_hw->ops.get_meta_error)
  3912. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3913. pstate->multirect_index);
  3914. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  3915. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3916. if (ubwc_stats->error || ubwc_stats->meta_error) {
  3917. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  3918. SDE_EVTLOG_ERROR);
  3919. SDE_DEBUG_PLANE(psde, "ubwc_error:0x%x meta_error:0x%x\n",
  3920. ubwc_stats->error, ubwc_stats->meta_error);
  3921. }
  3922. }
  3923. #if IS_ENABLED(CONFIG_DEBUG_FS)
  3924. static ssize_t _sde_plane_danger_read(struct file *file,
  3925. char __user *buff, size_t count, loff_t *ppos)
  3926. {
  3927. struct sde_kms *kms = file->private_data;
  3928. struct sde_mdss_cfg *cfg = kms->catalog;
  3929. int len = 0;
  3930. char buf[40] = {'\0'};
  3931. if (!cfg)
  3932. return -ENODEV;
  3933. if (*ppos)
  3934. return 0; /* the end */
  3935. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3936. if (len < 0 || len >= sizeof(buf))
  3937. return 0;
  3938. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3939. return -EFAULT;
  3940. *ppos += len; /* increase offset */
  3941. return len;
  3942. }
  3943. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3944. {
  3945. struct drm_plane *plane;
  3946. drm_for_each_plane(plane, kms->dev) {
  3947. if (plane->fb && plane->state) {
  3948. sde_plane_danger_signal_ctrl(plane, enable);
  3949. SDE_DEBUG("plane:%d img:%dx%d ",
  3950. plane->base.id, plane->fb->width,
  3951. plane->fb->height);
  3952. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3953. plane->state->src_x >> 16,
  3954. plane->state->src_y >> 16,
  3955. plane->state->src_w >> 16,
  3956. plane->state->src_h >> 16,
  3957. plane->state->crtc_x, plane->state->crtc_y,
  3958. plane->state->crtc_w, plane->state->crtc_h);
  3959. } else {
  3960. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3961. }
  3962. }
  3963. }
  3964. static ssize_t _sde_plane_danger_write(struct file *file,
  3965. const char __user *user_buf, size_t count, loff_t *ppos)
  3966. {
  3967. struct sde_kms *kms = file->private_data;
  3968. struct sde_mdss_cfg *cfg = kms->catalog;
  3969. int disable_panic;
  3970. char buf[10];
  3971. if (!cfg)
  3972. return -EFAULT;
  3973. if (count >= sizeof(buf))
  3974. return -EFAULT;
  3975. if (copy_from_user(buf, user_buf, count))
  3976. return -EFAULT;
  3977. buf[count] = 0; /* end of string */
  3978. if (kstrtoint(buf, 0, &disable_panic))
  3979. return -EFAULT;
  3980. if (disable_panic) {
  3981. /* Disable panic signal for all active pipes */
  3982. SDE_DEBUG("Disabling danger:\n");
  3983. _sde_plane_set_danger_state(kms, false);
  3984. kms->has_danger_ctrl = false;
  3985. } else {
  3986. /* Enable panic signal for all active pipes */
  3987. SDE_DEBUG("Enabling danger:\n");
  3988. kms->has_danger_ctrl = true;
  3989. _sde_plane_set_danger_state(kms, true);
  3990. }
  3991. return count;
  3992. }
  3993. static const struct file_operations sde_plane_danger_enable = {
  3994. .open = simple_open,
  3995. .read = _sde_plane_danger_read,
  3996. .write = _sde_plane_danger_write,
  3997. };
  3998. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3999. {
  4000. struct sde_plane *psde;
  4001. struct sde_kms *kms;
  4002. struct msm_drm_private *priv;
  4003. const struct sde_sspp_sub_blks *sblk = 0;
  4004. const struct sde_sspp_cfg *cfg = 0;
  4005. if (!plane || !plane->dev) {
  4006. SDE_ERROR("invalid arguments\n");
  4007. return -EINVAL;
  4008. }
  4009. priv = plane->dev->dev_private;
  4010. if (!priv || !priv->kms) {
  4011. SDE_ERROR("invalid KMS reference\n");
  4012. return -EINVAL;
  4013. }
  4014. kms = to_sde_kms(priv->kms);
  4015. psde = to_sde_plane(plane);
  4016. if (psde && psde->pipe_hw)
  4017. cfg = psde->pipe_hw->cap;
  4018. if (cfg)
  4019. sblk = cfg->sblk;
  4020. if (!sblk)
  4021. return 0;
  4022. /* create overall sub-directory for the pipe */
  4023. psde->debugfs_root =
  4024. debugfs_create_dir(psde->pipe_name,
  4025. plane->dev->primary->debugfs_root);
  4026. if (!psde->debugfs_root)
  4027. return -ENOMEM;
  4028. /* don't error check these */
  4029. debugfs_create_x64("features", 0400,
  4030. psde->debugfs_root, &psde->features);
  4031. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  4032. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  4033. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  4034. debugfs_create_bool("default_scaling",
  4035. 0600,
  4036. psde->debugfs_root,
  4037. &psde->debugfs_default_scale);
  4038. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  4039. debugfs_create_u32("in_rot_max_downscale_rt_num",
  4040. 0600,
  4041. psde->debugfs_root,
  4042. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  4043. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  4044. 0600,
  4045. psde->debugfs_root,
  4046. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  4047. debugfs_create_u32("in_rot_max_downscale_nrt",
  4048. 0600,
  4049. psde->debugfs_root,
  4050. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  4051. debugfs_create_u32("in_rot_max_height",
  4052. 0600,
  4053. psde->debugfs_root,
  4054. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  4055. }
  4056. debugfs_create_u32("xin_id",
  4057. 0400,
  4058. psde->debugfs_root,
  4059. (u32 *) &cfg->xin_id);
  4060. debugfs_create_x32("creq_vblank",
  4061. 0600,
  4062. psde->debugfs_root,
  4063. (u32 *) &sblk->creq_vblank);
  4064. debugfs_create_x32("danger_vblank",
  4065. 0600,
  4066. psde->debugfs_root,
  4067. (u32 *) &sblk->danger_vblank);
  4068. debugfs_create_file("disable_danger",
  4069. 0600,
  4070. psde->debugfs_root,
  4071. kms, &sde_plane_danger_enable);
  4072. return 0;
  4073. }
  4074. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4075. {
  4076. struct sde_plane *psde;
  4077. if (!plane)
  4078. return;
  4079. psde = to_sde_plane(plane);
  4080. debugfs_remove_recursive(psde->debugfs_root);
  4081. }
  4082. #else
  4083. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4084. {
  4085. return 0;
  4086. }
  4087. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4088. {
  4089. }
  4090. #endif /* CONFIG_DEBUG_FS */
  4091. static int sde_plane_late_register(struct drm_plane *plane)
  4092. {
  4093. return _sde_plane_init_debugfs(plane);
  4094. }
  4095. static void sde_plane_early_unregister(struct drm_plane *plane)
  4096. {
  4097. _sde_plane_destroy_debugfs(plane);
  4098. }
  4099. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4100. static bool sde_plane_format_mod_supported(struct drm_plane *plane,
  4101. uint32_t format, uint64_t modifier)
  4102. {
  4103. return (sde_get_sde_format_ext(format, modifier) != NULL);
  4104. }
  4105. #endif
  4106. static const struct drm_plane_funcs sde_plane_funcs = {
  4107. .update_plane = drm_atomic_helper_update_plane,
  4108. .disable_plane = drm_atomic_helper_disable_plane,
  4109. .destroy = sde_plane_destroy,
  4110. .atomic_set_property = sde_plane_atomic_set_property,
  4111. .atomic_get_property = sde_plane_atomic_get_property,
  4112. .reset = sde_plane_reset,
  4113. .atomic_duplicate_state = sde_plane_duplicate_state,
  4114. .atomic_destroy_state = sde_plane_destroy_state,
  4115. .late_register = sde_plane_late_register,
  4116. .early_unregister = sde_plane_early_unregister,
  4117. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4118. .format_mod_supported = sde_plane_format_mod_supported,
  4119. #endif
  4120. };
  4121. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4122. .prepare_fb = sde_plane_prepare_fb,
  4123. .cleanup_fb = sde_plane_cleanup_fb,
  4124. .atomic_check = sde_plane_atomic_check,
  4125. .atomic_update = sde_plane_atomic_update,
  4126. };
  4127. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4128. {
  4129. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4130. }
  4131. bool is_sde_plane_virtual(struct drm_plane *plane)
  4132. {
  4133. return plane ? to_sde_plane(plane)->is_virtual : false;
  4134. }
  4135. /* initialize plane */
  4136. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4137. uint32_t pipe, bool primary_plane,
  4138. unsigned long possible_crtcs, u32 master_plane_id)
  4139. {
  4140. struct drm_plane *plane = NULL, *master_plane = NULL;
  4141. const struct sde_format_extended *format_list;
  4142. struct sde_plane *psde;
  4143. struct msm_drm_private *priv;
  4144. struct sde_kms *kms;
  4145. enum drm_plane_type type;
  4146. struct sde_vbif_clk_client clk_client;
  4147. int ret = -EINVAL;
  4148. if (!dev) {
  4149. SDE_ERROR("[%u]device is NULL\n", pipe);
  4150. goto exit;
  4151. }
  4152. priv = dev->dev_private;
  4153. if (!priv) {
  4154. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4155. goto exit;
  4156. }
  4157. if (!priv->kms) {
  4158. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4159. goto exit;
  4160. }
  4161. kms = to_sde_kms(priv->kms);
  4162. if (!kms->catalog) {
  4163. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4164. goto exit;
  4165. }
  4166. /* create and zero local structure */
  4167. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4168. if (!psde) {
  4169. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4170. ret = -ENOMEM;
  4171. goto exit;
  4172. }
  4173. /* cache local stuff for later */
  4174. plane = &psde->base;
  4175. psde->pipe = pipe;
  4176. psde->is_virtual = (master_plane_id != 0);
  4177. INIT_LIST_HEAD(&psde->mplane_list);
  4178. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4179. if (master_plane) {
  4180. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4181. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4182. }
  4183. /* initialize underlying h/w driver */
  4184. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4185. &clk_client);
  4186. if (IS_ERR(psde->pipe_hw)) {
  4187. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4188. ret = PTR_ERR(psde->pipe_hw);
  4189. goto clean_plane;
  4190. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4191. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4192. goto clean_sspp;
  4193. }
  4194. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4195. ret = sde_vbif_clk_register(kms, &clk_client);
  4196. if (ret) {
  4197. SDE_ERROR("failed to register vbif client %d\n",
  4198. clk_client.clk_ctrl);
  4199. goto clean_sspp;
  4200. }
  4201. }
  4202. /* cache features mask for later */
  4203. psde->features = psde->pipe_hw->cap->features_ext;
  4204. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4205. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4206. if (!psde->pipe_sblk) {
  4207. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4208. goto clean_sspp;
  4209. }
  4210. if (psde->is_virtual)
  4211. format_list = psde->pipe_sblk->virt_format_list;
  4212. else
  4213. format_list = psde->pipe_sblk->format_list;
  4214. psde->nformats = sde_populate_formats(format_list,
  4215. psde->formats,
  4216. 0,
  4217. ARRAY_SIZE(psde->formats));
  4218. if (!psde->nformats) {
  4219. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4220. goto clean_sspp;
  4221. }
  4222. if (primary_plane)
  4223. type = DRM_PLANE_TYPE_PRIMARY;
  4224. else
  4225. type = DRM_PLANE_TYPE_OVERLAY;
  4226. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4227. psde->formats, psde->nformats,
  4228. NULL, type, NULL);
  4229. if (ret)
  4230. goto clean_sspp;
  4231. /* Populate static array of plane property flags */
  4232. _sde_plane_map_prop_to_dirty_bits();
  4233. /* success! finalize initialization */
  4234. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4235. msm_property_init(&psde->property_info, &plane->base, dev,
  4236. priv->plane_property, psde->property_data,
  4237. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4238. sizeof(struct sde_plane_state));
  4239. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4240. /* save user friendly pipe name for later */
  4241. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4242. mutex_init(&psde->lock);
  4243. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4244. pipe, plane->base.id, master_plane_id);
  4245. return plane;
  4246. clean_sspp:
  4247. if (psde && psde->pipe_hw)
  4248. sde_hw_sspp_destroy(psde->pipe_hw);
  4249. clean_plane:
  4250. kfree(psde);
  4251. exit:
  4252. return ERR_PTR(ret);
  4253. }
  4254. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4255. {
  4256. struct sde_plane *sde_plane;
  4257. struct sde_plane_state *pstate;
  4258. sde_plane = to_sde_plane(plane);
  4259. pstate = to_sde_plane_state(plane->state);
  4260. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4261. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4262. }