0a93edbae6
Change avoids clock framework APIs to configure the DSI PHY PLL. It follows HW recommendation to set the byte and pclk dividers. Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8 Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
355 regels
10 KiB
C
355 regels
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DSI_CLK_H_
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#define _DSI_CLK_H_
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/clk.h>
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#define MAX_STRING_LEN 32
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#define MAX_DSI_CTRL 2
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enum dsi_clk_state {
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DSI_CLK_OFF,
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DSI_CLK_ON,
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DSI_CLK_EARLY_GATE,
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};
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enum clk_req_client {
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DSI_CLK_REQ_MDP_CLIENT = 0,
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DSI_CLK_REQ_DSI_CLIENT,
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};
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enum dsi_link_clk_type {
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DSI_LINK_ESC_CLK,
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DSI_LINK_BYTE_CLK,
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DSI_LINK_PIX_CLK,
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DSI_LINK_BYTE_INTF_CLK,
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DSI_LINK_CLK_MAX,
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};
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enum dsi_link_clk_op_type {
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DSI_LINK_CLK_SET_RATE = BIT(0),
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DSI_LINK_CLK_PREPARE = BIT(1),
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DSI_LINK_CLK_ENABLE = BIT(2),
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DSI_LINK_CLK_START = BIT(0) | BIT(1) | BIT(2),
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};
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enum dsi_clk_type {
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DSI_CORE_CLK = BIT(0),
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DSI_LINK_CLK = BIT(1),
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DSI_ALL_CLKS = (BIT(0) | BIT(1)),
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DSI_CLKS_MAX = BIT(2),
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};
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enum dsi_lclk_type {
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DSI_LINK_NONE = 0,
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DSI_LINK_LP_CLK = BIT(0),
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DSI_LINK_HS_CLK = BIT(1),
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};
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struct dsi_clk_ctrl_info {
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enum dsi_clk_type clk_type;
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enum dsi_clk_state clk_state;
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enum clk_req_client client;
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};
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struct clk_ctrl_cb {
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void *priv;
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int (*dsi_clk_cb)(void *priv, struct dsi_clk_ctrl_info clk_ctrl_info);
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};
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/**
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* struct dsi_core_clk_info - Core clock information for DSI hardware
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* @mdp_core_clk: Handle to MDP core clock.
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* @iface_clk: Handle to MDP interface clock.
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* @core_mmss_clk: Handle to MMSS core clock.
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* @bus_clk: Handle to bus clock.
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* @mnoc_clk: Handle to MMSS NOC clock.
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* @drm: Pointer to drm device node
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*/
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struct dsi_core_clk_info {
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struct clk *mdp_core_clk;
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struct clk *iface_clk;
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struct clk *core_mmss_clk;
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struct clk *bus_clk;
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struct clk *mnoc_clk;
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struct drm_device *drm;
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};
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/**
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* struct dsi_link_hs_clk_info - Set of high speed link clocks for DSI HW
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* @byte_clk: Handle to DSI byte_clk.
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* @pixel_clk: Handle to DSI pixel_clk.
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* @byte_intf_clk: Handle to DSI byte intf. clock.
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*/
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struct dsi_link_hs_clk_info {
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struct clk *byte_clk;
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struct clk *pixel_clk;
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struct clk *byte_intf_clk;
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};
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/**
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* struct dsi_link_lp_clk_info - Set of low power link clocks for DSI HW.
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* @esc_clk: Handle to DSI escape clock.
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*/
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struct dsi_link_lp_clk_info {
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struct clk *esc_clk;
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};
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/**
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* struct link_clk_freq - Clock frequency information for Link clocks
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* @byte_clk_rate: Frequency of DSI byte_clk in Hz.
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* @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in Hz.
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* @pixel_clk_rate: Frequency of DSI pixel_clk in Hz.
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* @esc_clk_rate: Frequency of DSI escape clock in Hz.
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*/
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struct link_clk_freq {
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u32 byte_clk_rate;
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u32 byte_intf_clk_rate;
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u32 pix_clk_rate;
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u32 esc_clk_rate;
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};
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/**
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* typedef *pre_clockoff_cb() - Callback before clock is turned off
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* @priv: private data pointer.
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* @clk_type: clock which is being turned off.
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* @l_type: specifies if the clock is HS or LP type. Valid only for link clocks.
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* @new_state: next state for the clock.
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*
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* @return: error code.
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*/
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typedef int (*pre_clockoff_cb)(void *priv,
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enum dsi_clk_type clk_type,
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enum dsi_lclk_type l_type,
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enum dsi_clk_state new_state);
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/**
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* typedef *post_clockoff_cb() - Callback after clock is turned off
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* @priv: private data pointer.
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* @clk_type: clock which was turned off.
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* @l_type: specifies if the clock is HS or LP type. Valid only for link clocks.
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* @curr_state: current state for the clock.
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*
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* @return: error code.
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*/
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typedef int (*post_clockoff_cb)(void *priv,
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enum dsi_clk_type clk_type,
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enum dsi_lclk_type l_type,
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enum dsi_clk_state curr_state);
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/**
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* typedef *post_clockon_cb() - Callback after clock is turned on
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* @priv: private data pointer.
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* @clk_type: clock which was turned on.
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* @l_type: specifies if the clock is HS or LP type. Valid only for link clocks.
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* @curr_state: current state for the clock.
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*
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* @return: error code.
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*/
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typedef int (*post_clockon_cb)(void *priv,
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enum dsi_clk_type clk_type,
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enum dsi_lclk_type l_type,
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enum dsi_clk_state curr_state);
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/**
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* typedef *pre_clockon_cb() - Callback before clock is turned on
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* @priv: private data pointer.
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* @clk_type: clock which is being turned on.
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* @l_type: specifies if the clock is HS or LP type.Valid only for link clocks.
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* @new_state: next state for the clock.
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*
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* @return: error code.
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*/
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typedef int (*pre_clockon_cb)(void *priv,
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enum dsi_clk_type clk_type,
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enum dsi_lclk_type l_type,
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enum dsi_clk_state new_state);
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/**
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* typedef *phy_configure_cb() - Callback to configure PHY for PLL clocks
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* @priv: private data pointer.
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* @commit: boolean to specify if calculated PHY configuration needs to be
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* committed. Set to false in case of dynamic clock switch.
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*
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* @return: error code.
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*/
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typedef int (*phy_configure_cb)(void *priv, bool commit);
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/**
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* typedef *pll_toggle_cb() - Callback to toggle PHY PLL
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* @priv: private data pointer.
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* @prepare: specifies if the PLL needs to be turned on or off.
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*
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* @return: error code.
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*/
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typedef int (*pll_toggle_cb)(void *priv, bool prepare);
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/**
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* struct dsi_clk_info - clock information for DSI hardware.
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* @name: client name.
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* @c_clks[MAX_DSI_CTRL] array of core clock configurations
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* @l_lp_clks[MAX_DSI_CTRL] array of low power(esc) clock configurations
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* @l_hs_clks[MAX_DSI_CTRL] array of high speed clock configurations
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* @ctrl_index[MAX_DSI_CTRL] array of DSI controller indexes mapped
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* to core and link clock configurations
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* @pre_clkoff_cb callback before clock is turned off
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* @post_clkoff_cb callback after clock is turned off
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* @post_clkon_cb callback after clock is turned on
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* @pre_clkon_cb callback before clock is turned on
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* @phy_config_cb callback to configure PHY PLL
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* @phy_pll_toggle_cb callback to toggle PHY PLL state
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* @priv_data pointer to private data
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* @master_ndx master DSI controller index
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* @dsi_ctrl_count number of DSI controllers
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*/
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struct dsi_clk_info {
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char name[MAX_STRING_LEN];
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struct dsi_core_clk_info c_clks[MAX_DSI_CTRL];
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struct dsi_link_lp_clk_info l_lp_clks[MAX_DSI_CTRL];
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struct dsi_link_hs_clk_info l_hs_clks[MAX_DSI_CTRL];
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u32 ctrl_index[MAX_DSI_CTRL];
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pre_clockoff_cb pre_clkoff_cb;
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post_clockoff_cb post_clkoff_cb;
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post_clockon_cb post_clkon_cb;
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pre_clockon_cb pre_clkon_cb;
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phy_configure_cb phy_config_cb;
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pll_toggle_cb phy_pll_toggle_cb;
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void *priv_data;
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u32 master_ndx;
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u32 dsi_ctrl_count;
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};
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/**
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* struct dsi_clk_link_set - Pair of clock handles to describe link clocks
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* @byte_clk: Handle to DSi byte_clk.
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* @pixel_clk: Handle to DSI pixel_clk.
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*/
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struct dsi_clk_link_set {
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struct clk *byte_clk;
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struct clk *pixel_clk;
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};
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/**
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* dsi_display_clk_mngr_update_splash_status() - Update splash stattus
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* @clk_mngr: Structure containing DSI clock information
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* @status: Splash status
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*/
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void dsi_display_clk_mngr_update_splash_status(void *clk_mgr, bool status);
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/**
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* dsi_display_clk_mgr_register() - Register DSI clock manager
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* @info: Structure containing DSI clock information
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*/
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void *dsi_display_clk_mngr_register(struct dsi_clk_info *info);
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/**
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* dsi_display_clk_mngr_deregister() - Deregister DSI clock manager
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* @clk_mngr: DSI clock manager pointer
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*/
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int dsi_display_clk_mngr_deregister(void *clk_mngr);
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/**
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* dsi_register_clk_handle() - Register clock handle with DSI clock manager
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* @clk_mngr: DSI clock manager pointer
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* @client: DSI clock client pointer.
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*/
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void *dsi_register_clk_handle(void *clk_mngr, char *client);
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/**
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* dsi_deregister_clk_handle() - Deregister clock handle from DSI clock manager
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* @client: DSI clock client pointer.
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*
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* return: error code in case of failure or 0 for success.
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*/
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int dsi_deregister_clk_handle(void *client);
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/**
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* dsi_display_link_clk_force_update_ctrl() - force to set link clks
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* @handle: Handle of desired DSI clock client.
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*
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* return: error code in case of failure or 0 for success.
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*/
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int dsi_display_link_clk_force_update_ctrl(void *handle);
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/**
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* dsi_display_clk_ctrl() - set frequencies for link clks
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* @handle: Handle of desired DSI clock client.
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* @clk_type: Clock which is being controlled.
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* @clk_state: Desired state of clock
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*
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* return: error code in case of failure or 0 for success.
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*/
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int dsi_display_clk_ctrl(void *handle, u32 clk_type, u32 clk_state);
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/**
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* dsi_clk_set_link_frequencies() - set frequencies for link clks
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* @client: DSI clock client pointer.
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* @freq: Structure containing link clock frequencies.
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* @index: Index of the DSI controller.
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*
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* return: error code in case of failure or 0 for success.
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*/
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int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
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u32 index);
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/**
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* dsi_clk_set_pixel_clk_rate() - set frequency for pixel_clk
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* @client: DSI clock client pointer.
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* @pixel_clk: Pixel_clk rate in Hz.
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* @index: Index of the DSI controller.
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* return: error code in case of failure or 0 for success.
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*/
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int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index);
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/**
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* dsi_clk_set_byte_clk_rate() - set frequency for byte clock
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* @client: DSI clock client pointer.
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* @byte_clk: Pixel clock rate in Hz.
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* @byte_intf_clk: Byte interface clock rate in Hz.
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* @index: Index of the DSI controller.
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* return: error code in case of failure or 0 for success.
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*/
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int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,
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u64 byte_intf_clk, u32 index);
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/**
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* dsi_clk_update_parent() - update parent clocks for specified clock
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* @parent: link clock pair which are set as parent.
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* @child: link clock pair whose parent has to be set.
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*/
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int dsi_clk_update_parent(struct dsi_clk_link_set *parent,
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struct dsi_clk_link_set *child);
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/**
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* dsi_clk_prepare_enable() - prepare and enable dsi src clocks
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* @clk: list of src clocks.
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*
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* @return: Zero on success and err no on failure
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*/
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int dsi_clk_prepare_enable(struct dsi_clk_link_set *clk);
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/**
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* dsi_clk_disable_unprepare() - disable and unprepare dsi src clocks
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* @clk: list of src clocks.
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*/
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void dsi_clk_disable_unprepare(struct dsi_clk_link_set *clk);
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/**
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* dsi_display_dump_clk_handle_state() - dump client clock state
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* @client: DSI clock client pointer.
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*/
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int dsi_display_dump_clk_handle_state(void *client);
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#endif /* _DSI_CLK_H_ */
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