dp_tx.c 77 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /**
  51. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  52. * @vdev: DP Virtual device handle
  53. * @nbuf: Buffer pointer
  54. * @queue: queue ids container for nbuf
  55. *
  56. * TX packet queue has 2 instances, software descriptors id and dma ring id
  57. * Based on tx feature and hardware configuration queue id combination could be
  58. * different.
  59. * For example -
  60. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  61. * With no XPS,lock based resource protection, Descriptor pool ids are different
  62. * for each vdev, dma ring id will be same as single pdev id
  63. *
  64. * Return: None
  65. */
  66. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  67. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  68. {
  69. /* get flow id */
  70. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  71. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  72. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  73. "%s, pool_id:%d ring_id: %d",
  74. __func__, queue->desc_pool_id, queue->ring_id);
  75. return;
  76. }
  77. #if defined(FEATURE_TSO)
  78. /**
  79. * dp_tx_tso_desc_release() - Release the tso segment
  80. * after unmapping all the fragments
  81. *
  82. * @pdev - physical device handle
  83. * @tx_desc - Tx software descriptor
  84. */
  85. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  86. struct dp_tx_desc_s *tx_desc)
  87. {
  88. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  89. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  91. "%s %d TSO desc is NULL!",
  92. __func__, __LINE__);
  93. qdf_assert(0);
  94. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  95. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  96. "%s %d TSO common info is NULL!",
  97. __func__, __LINE__);
  98. qdf_assert(0);
  99. } else {
  100. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  101. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  102. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  103. tso_num_desc->num_seg.tso_cmn_num_seg--;
  104. qdf_nbuf_unmap_tso_segment(soc->osdev,
  105. tx_desc->tso_desc, false);
  106. } else {
  107. tso_num_desc->num_seg.tso_cmn_num_seg--;
  108. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  109. qdf_nbuf_unmap_tso_segment(soc->osdev,
  110. tx_desc->tso_desc, true);
  111. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  112. tx_desc->tso_num_desc);
  113. tx_desc->tso_num_desc = NULL;
  114. }
  115. dp_tx_tso_desc_free(soc,
  116. tx_desc->pool_id, tx_desc->tso_desc);
  117. tx_desc->tso_desc = NULL;
  118. }
  119. }
  120. #else
  121. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  122. struct dp_tx_desc_s *tx_desc)
  123. {
  124. return;
  125. }
  126. #endif
  127. /**
  128. * dp_tx_desc_release() - Release Tx Descriptor
  129. * @tx_desc : Tx Descriptor
  130. * @desc_pool_id: Descriptor Pool ID
  131. *
  132. * Deallocate all resources attached to Tx descriptor and free the Tx
  133. * descriptor.
  134. *
  135. * Return:
  136. */
  137. static void
  138. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  139. {
  140. struct dp_pdev *pdev = tx_desc->pdev;
  141. struct dp_soc *soc;
  142. uint8_t comp_status = 0;
  143. qdf_assert(pdev);
  144. soc = pdev->soc;
  145. if (tx_desc->frm_type == dp_tx_frm_tso)
  146. dp_tx_tso_desc_release(soc, tx_desc);
  147. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  148. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  149. qdf_atomic_dec(&pdev->num_tx_outstanding);
  150. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  151. qdf_atomic_dec(&pdev->num_tx_exception);
  152. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  153. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  154. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  155. else
  156. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  158. "Tx Completion Release desc %d status %d outstanding %d",
  159. tx_desc->id, comp_status,
  160. qdf_atomic_read(&pdev->num_tx_outstanding));
  161. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  162. return;
  163. }
  164. /**
  165. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  166. * @vdev: DP vdev Handle
  167. * @nbuf: skb
  168. *
  169. * Prepares and fills HTT metadata in the frame pre-header for special frames
  170. * that should be transmitted using varying transmit parameters.
  171. * There are 2 VDEV modes that currently needs this special metadata -
  172. * 1) Mesh Mode
  173. * 2) DSRC Mode
  174. *
  175. * Return: HTT metadata size
  176. *
  177. */
  178. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  179. uint32_t *meta_data)
  180. {
  181. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  182. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  183. uint8_t htt_desc_size;
  184. /* Size rounded of multiple of 8 bytes */
  185. uint8_t htt_desc_size_aligned;
  186. uint8_t *hdr = NULL;
  187. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  188. /*
  189. * Metadata - HTT MSDU Extension header
  190. */
  191. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  192. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  193. if (vdev->mesh_vdev) {
  194. /* Fill and add HTT metaheader */
  195. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  196. if (hdr == NULL) {
  197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  198. "Error in filling HTT metadata\n");
  199. return 0;
  200. }
  201. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  202. } else if (vdev->opmode == wlan_op_mode_ocb) {
  203. /* Todo - Add support for DSRC */
  204. }
  205. return htt_desc_size_aligned;
  206. }
  207. /**
  208. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  209. * @tso_seg: TSO segment to process
  210. * @ext_desc: Pointer to MSDU extension descriptor
  211. *
  212. * Return: void
  213. */
  214. #if defined(FEATURE_TSO)
  215. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  216. void *ext_desc)
  217. {
  218. uint8_t num_frag;
  219. uint32_t tso_flags;
  220. /*
  221. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  222. * tcp_flag_mask
  223. *
  224. * Checksum enable flags are set in TCL descriptor and not in Extension
  225. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  226. */
  227. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  228. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  229. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  230. tso_seg->tso_flags.ip_len);
  231. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  232. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  233. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  234. uint32_t lo = 0;
  235. uint32_t hi = 0;
  236. qdf_dmaaddr_to_32s(
  237. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  238. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  239. tso_seg->tso_frags[num_frag].length);
  240. }
  241. return;
  242. }
  243. #else
  244. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  245. void *ext_desc)
  246. {
  247. return;
  248. }
  249. #endif
  250. #if defined(FEATURE_TSO)
  251. /**
  252. * dp_tx_free_tso_seg() - Loop through the tso segments
  253. * allocated and free them
  254. *
  255. * @soc: soc handle
  256. * @free_seg: list of tso segments
  257. * @msdu_info: msdu descriptor
  258. *
  259. * Return - void
  260. */
  261. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  262. struct qdf_tso_seg_elem_t *free_seg,
  263. struct dp_tx_msdu_info_s *msdu_info)
  264. {
  265. struct qdf_tso_seg_elem_t *next_seg;
  266. while (free_seg) {
  267. next_seg = free_seg->next;
  268. dp_tx_tso_desc_free(soc,
  269. msdu_info->tx_queue.desc_pool_id,
  270. free_seg);
  271. free_seg = next_seg;
  272. }
  273. }
  274. /**
  275. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  276. * allocated and free them
  277. *
  278. * @soc: soc handle
  279. * @free_seg: list of tso segments
  280. * @msdu_info: msdu descriptor
  281. * Return - void
  282. */
  283. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  284. struct qdf_tso_num_seg_elem_t *free_seg,
  285. struct dp_tx_msdu_info_s *msdu_info)
  286. {
  287. struct qdf_tso_num_seg_elem_t *next_seg;
  288. while (free_seg) {
  289. next_seg = free_seg->next;
  290. dp_tso_num_seg_free(soc,
  291. msdu_info->tx_queue.desc_pool_id,
  292. free_seg);
  293. free_seg = next_seg;
  294. }
  295. }
  296. /**
  297. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  298. * @vdev: virtual device handle
  299. * @msdu: network buffer
  300. * @msdu_info: meta data associated with the msdu
  301. *
  302. * Return: QDF_STATUS_SUCCESS success
  303. */
  304. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  305. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  306. {
  307. struct qdf_tso_seg_elem_t *tso_seg;
  308. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  309. struct dp_soc *soc = vdev->pdev->soc;
  310. struct qdf_tso_info_t *tso_info;
  311. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  312. tso_info = &msdu_info->u.tso_info;
  313. tso_info->curr_seg = NULL;
  314. tso_info->tso_seg_list = NULL;
  315. tso_info->num_segs = num_seg;
  316. msdu_info->frm_type = dp_tx_frm_tso;
  317. tso_info->tso_num_seg_list = NULL;
  318. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  319. while (num_seg) {
  320. tso_seg = dp_tx_tso_desc_alloc(
  321. soc, msdu_info->tx_queue.desc_pool_id);
  322. if (tso_seg) {
  323. tso_seg->next = tso_info->tso_seg_list;
  324. tso_info->tso_seg_list = tso_seg;
  325. num_seg--;
  326. } else {
  327. struct qdf_tso_seg_elem_t *free_seg =
  328. tso_info->tso_seg_list;
  329. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  330. return QDF_STATUS_E_NOMEM;
  331. }
  332. }
  333. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  334. tso_num_seg = dp_tso_num_seg_alloc(soc,
  335. msdu_info->tx_queue.desc_pool_id);
  336. if (tso_num_seg) {
  337. tso_num_seg->next = tso_info->tso_num_seg_list;
  338. tso_info->tso_num_seg_list = tso_num_seg;
  339. } else {
  340. /* Bug: free tso_num_seg and tso_seg */
  341. /* Free the already allocated num of segments */
  342. struct qdf_tso_seg_elem_t *free_seg =
  343. tso_info->tso_seg_list;
  344. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  345. __func__);
  346. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  347. return QDF_STATUS_E_NOMEM;
  348. }
  349. msdu_info->num_seg =
  350. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  351. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  352. msdu_info->num_seg);
  353. if (!(msdu_info->num_seg)) {
  354. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  355. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  356. msdu_info);
  357. return QDF_STATUS_E_INVAL;
  358. }
  359. tso_info->curr_seg = tso_info->tso_seg_list;
  360. return QDF_STATUS_SUCCESS;
  361. }
  362. #else
  363. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  364. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  365. {
  366. return QDF_STATUS_E_NOMEM;
  367. }
  368. #endif
  369. /**
  370. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  371. * @vdev: DP Vdev handle
  372. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  373. * @desc_pool_id: Descriptor Pool ID
  374. *
  375. * Return:
  376. */
  377. static
  378. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  379. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  380. {
  381. uint8_t i;
  382. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  383. struct dp_tx_seg_info_s *seg_info;
  384. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  385. struct dp_soc *soc = vdev->pdev->soc;
  386. /* Allocate an extension descriptor */
  387. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  388. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  389. if (!msdu_ext_desc) {
  390. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  391. return NULL;
  392. }
  393. if (qdf_unlikely(vdev->mesh_vdev)) {
  394. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  395. &msdu_info->meta_data[0],
  396. sizeof(struct htt_tx_msdu_desc_ext2_t));
  397. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  398. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  399. }
  400. switch (msdu_info->frm_type) {
  401. case dp_tx_frm_sg:
  402. case dp_tx_frm_me:
  403. case dp_tx_frm_raw:
  404. seg_info = msdu_info->u.sg_info.curr_seg;
  405. /* Update the buffer pointers in MSDU Extension Descriptor */
  406. for (i = 0; i < seg_info->frag_cnt; i++) {
  407. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  408. seg_info->frags[i].paddr_lo,
  409. seg_info->frags[i].paddr_hi,
  410. seg_info->frags[i].len);
  411. }
  412. break;
  413. case dp_tx_frm_tso:
  414. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  415. &cached_ext_desc[0]);
  416. break;
  417. default:
  418. break;
  419. }
  420. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  421. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  422. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  423. msdu_ext_desc->vaddr);
  424. return msdu_ext_desc;
  425. }
  426. /**
  427. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  428. * @vdev: DP vdev handle
  429. * @nbuf: skb
  430. * @desc_pool_id: Descriptor pool ID
  431. * Allocate and prepare Tx descriptor with msdu information.
  432. *
  433. * Return: Pointer to Tx Descriptor on success,
  434. * NULL on failure
  435. */
  436. static
  437. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  438. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  439. uint32_t *meta_data)
  440. {
  441. uint8_t align_pad;
  442. uint8_t is_exception = 0;
  443. uint8_t htt_hdr_size;
  444. struct ether_header *eh;
  445. struct dp_tx_desc_s *tx_desc;
  446. struct dp_pdev *pdev = vdev->pdev;
  447. struct dp_soc *soc = pdev->soc;
  448. /* Allocate software Tx descriptor */
  449. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  450. if (qdf_unlikely(!tx_desc)) {
  451. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  452. return NULL;
  453. }
  454. /* Flow control/Congestion Control counters */
  455. qdf_atomic_inc(&pdev->num_tx_outstanding);
  456. /* Initialize the SW tx descriptor */
  457. tx_desc->nbuf = nbuf;
  458. tx_desc->frm_type = dp_tx_frm_std;
  459. tx_desc->tx_encap_type = vdev->tx_encap_type;
  460. tx_desc->vdev = vdev;
  461. tx_desc->pdev = pdev;
  462. tx_desc->msdu_ext_desc = NULL;
  463. tx_desc->pkt_offset = 0;
  464. /*
  465. * For special modes (vdev_type == ocb or mesh), data frames should be
  466. * transmitted using varying transmit parameters (tx spec) which include
  467. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  468. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  469. * These frames are sent as exception packets to firmware.
  470. *
  471. * HW requirement is that metadata should always point to a
  472. * 8-byte aligned address. So we add alignment pad to start of buffer.
  473. * HTT Metadata should be ensured to be multiple of 8-bytes,
  474. * to get 8-byte aligned start address along with align_pad added
  475. *
  476. * |-----------------------------|
  477. * | |
  478. * |-----------------------------| <-----Buffer Pointer Address given
  479. * | | ^ in HW descriptor (aligned)
  480. * | HTT Metadata | |
  481. * | | |
  482. * | | | Packet Offset given in descriptor
  483. * | | |
  484. * |-----------------------------| |
  485. * | Alignment Pad | v
  486. * |-----------------------------| <----- Actual buffer start address
  487. * | SKB Data | (Unaligned)
  488. * | |
  489. * | |
  490. * | |
  491. * | |
  492. * | |
  493. * |-----------------------------|
  494. */
  495. if (qdf_unlikely(vdev->mesh_vdev ||
  496. (vdev->opmode == wlan_op_mode_ocb))) {
  497. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  498. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  500. "qdf_nbuf_push_head failed\n");
  501. goto failure;
  502. }
  503. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  504. meta_data);
  505. if (htt_hdr_size == 0)
  506. goto failure;
  507. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  508. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  509. is_exception = 1;
  510. }
  511. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  512. qdf_nbuf_map(soc->osdev, nbuf,
  513. QDF_DMA_TO_DEVICE))) {
  514. /* Handle failure */
  515. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  516. "qdf_nbuf_map failed\n");
  517. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  518. goto failure;
  519. }
  520. if (qdf_unlikely(vdev->nawds_enabled)) {
  521. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  522. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  523. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  524. is_exception = 1;
  525. }
  526. }
  527. #if !TQM_BYPASS_WAR
  528. if (is_exception)
  529. #endif
  530. {
  531. /* Temporary WAR due to TQM VP issues */
  532. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  533. qdf_atomic_inc(&pdev->num_tx_exception);
  534. }
  535. return tx_desc;
  536. failure:
  537. dp_tx_desc_release(tx_desc, desc_pool_id);
  538. return NULL;
  539. }
  540. /**
  541. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  542. * @vdev: DP vdev handle
  543. * @nbuf: skb
  544. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  545. * @desc_pool_id : Descriptor Pool ID
  546. *
  547. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  548. * information. For frames wth fragments, allocate and prepare
  549. * an MSDU extension descriptor
  550. *
  551. * Return: Pointer to Tx Descriptor on success,
  552. * NULL on failure
  553. */
  554. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  555. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  556. uint8_t desc_pool_id)
  557. {
  558. struct dp_tx_desc_s *tx_desc;
  559. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  560. struct dp_pdev *pdev = vdev->pdev;
  561. struct dp_soc *soc = pdev->soc;
  562. /* Allocate software Tx descriptor */
  563. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  564. if (!tx_desc) {
  565. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  566. return NULL;
  567. }
  568. /* Flow control/Congestion Control counters */
  569. qdf_atomic_inc(&pdev->num_tx_outstanding);
  570. /* Initialize the SW tx descriptor */
  571. tx_desc->nbuf = nbuf;
  572. tx_desc->frm_type = msdu_info->frm_type;
  573. tx_desc->tx_encap_type = vdev->tx_encap_type;
  574. tx_desc->vdev = vdev;
  575. tx_desc->pdev = pdev;
  576. tx_desc->pkt_offset = 0;
  577. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  578. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  579. /* Handle scattered frames - TSO/SG/ME */
  580. /* Allocate and prepare an extension descriptor for scattered frames */
  581. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  582. if (!msdu_ext_desc) {
  583. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  584. "%s Tx Extension Descriptor Alloc Fail\n",
  585. __func__);
  586. goto failure;
  587. }
  588. #if TQM_BYPASS_WAR
  589. /* Temporary WAR due to TQM VP issues */
  590. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  591. qdf_atomic_inc(&pdev->num_tx_exception);
  592. #endif
  593. if (qdf_unlikely(vdev->mesh_vdev))
  594. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  595. tx_desc->msdu_ext_desc = msdu_ext_desc;
  596. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  597. return tx_desc;
  598. failure:
  599. dp_tx_desc_release(tx_desc, desc_pool_id);
  600. return NULL;
  601. }
  602. /**
  603. * dp_tx_prepare_raw() - Prepare RAW packet TX
  604. * @vdev: DP vdev handle
  605. * @nbuf: buffer pointer
  606. * @seg_info: Pointer to Segment info Descriptor to be prepared
  607. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  608. * descriptor
  609. *
  610. * Return:
  611. */
  612. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  613. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  614. {
  615. qdf_nbuf_t curr_nbuf = NULL;
  616. uint16_t total_len = 0;
  617. qdf_dma_addr_t paddr;
  618. int32_t i;
  619. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  620. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  621. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  622. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  623. if ((qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  624. && (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU)) {
  625. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  626. }
  627. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  628. QDF_DMA_TO_DEVICE)) {
  629. qdf_print("dma map error\n");
  630. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  631. qdf_nbuf_free(nbuf);
  632. return NULL;
  633. }
  634. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  635. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  636. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  637. seg_info->frags[i].paddr_lo = paddr;
  638. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  639. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  640. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  641. total_len += qdf_nbuf_len(curr_nbuf);
  642. }
  643. seg_info->frag_cnt = i;
  644. seg_info->total_len = total_len;
  645. seg_info->next = NULL;
  646. sg_info->curr_seg = seg_info;
  647. msdu_info->frm_type = dp_tx_frm_raw;
  648. msdu_info->num_seg = 1;
  649. return nbuf;
  650. }
  651. /**
  652. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  653. * @soc: DP Soc Handle
  654. * @vdev: DP vdev handle
  655. * @tx_desc: Tx Descriptor Handle
  656. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  657. * @fw_metadata: Metadata to send to Target Firmware along with frame
  658. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  659. *
  660. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  661. * from software Tx descriptor
  662. *
  663. * Return:
  664. */
  665. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  666. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  667. uint16_t fw_metadata, uint8_t ring_id)
  668. {
  669. uint8_t type;
  670. uint16_t length;
  671. void *hal_tx_desc, *hal_tx_desc_cached;
  672. qdf_dma_addr_t dma_addr;
  673. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  674. /* Return Buffer Manager ID */
  675. uint8_t bm_id = ring_id;
  676. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  677. hal_tx_desc_cached = (void *) cached_desc;
  678. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  679. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  680. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  681. type = HAL_TX_BUF_TYPE_EXT_DESC;
  682. dma_addr = tx_desc->msdu_ext_desc->paddr;
  683. } else {
  684. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  685. type = HAL_TX_BUF_TYPE_BUFFER;
  686. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  687. }
  688. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  689. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  690. dma_addr , bm_id, tx_desc->id, type);
  691. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  692. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  693. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  694. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  695. vdev->dscp_tid_map_id);
  696. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  697. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  698. __func__, length, type, (uint64_t)dma_addr,
  699. tx_desc->pkt_offset, tx_desc->id);
  700. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  701. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  702. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  703. vdev->hal_desc_addr_search_flags);
  704. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  705. || qdf_nbuf_is_tso(tx_desc->nbuf)) {
  706. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  707. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  708. }
  709. if (tid != HTT_TX_EXT_TID_INVALID)
  710. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  711. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  712. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  713. /* Sync cached descriptor with HW */
  714. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  715. if (!hal_tx_desc) {
  716. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  717. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  718. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  719. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  720. return QDF_STATUS_E_RESOURCES;
  721. }
  722. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  723. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  724. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  725. /*
  726. * If one packet is enqueued in HW, PM usage count needs to be
  727. * incremented by one to prevent future runtime suspend. This
  728. * should be tied with the success of enqueuing. It will be
  729. * decremented after the packet has been sent.
  730. */
  731. hif_pm_runtime_get_noresume(soc->hif_handle);
  732. return QDF_STATUS_SUCCESS;
  733. }
  734. /**
  735. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  736. * @vdev: DP vdev handle
  737. * @nbuf: skb
  738. *
  739. * Extract the DSCP or PCP information from frame and map into TID value.
  740. * Software based TID classification is required when more than 2 DSCP-TID
  741. * mapping tables are needed.
  742. * Hardware supports 2 DSCP-TID mapping tables
  743. *
  744. * Return: void
  745. */
  746. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  747. struct dp_tx_msdu_info_s *msdu_info)
  748. {
  749. uint8_t tos = 0, dscp_tid_override = 0;
  750. uint8_t *hdr_ptr, *L3datap;
  751. uint8_t is_mcast = 0;
  752. struct ether_header *eh = NULL;
  753. qdf_ethervlan_header_t *evh = NULL;
  754. uint16_t ether_type;
  755. qdf_llc_t *llcHdr;
  756. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  757. /* for mesh packets don't do any classification */
  758. if (qdf_unlikely(vdev->mesh_vdev))
  759. return;
  760. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  761. eh = (struct ether_header *) nbuf->data;
  762. hdr_ptr = eh->ether_dhost;
  763. L3datap = hdr_ptr + sizeof(struct ether_header);
  764. } else {
  765. qdf_dot3_qosframe_t *qos_wh =
  766. (qdf_dot3_qosframe_t *) nbuf->data;
  767. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  768. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  769. return;
  770. }
  771. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  772. ether_type = eh->ether_type;
  773. /*
  774. * Check if packet is dot3 or eth2 type.
  775. */
  776. if (IS_LLC_PRESENT(ether_type)) {
  777. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  778. sizeof(*llcHdr));
  779. if (ether_type == htons(ETHERTYPE_8021Q)) {
  780. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  781. sizeof(*llcHdr);
  782. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  783. + sizeof(*llcHdr) +
  784. sizeof(qdf_net_vlanhdr_t));
  785. } else {
  786. L3datap = hdr_ptr + sizeof(struct ether_header) +
  787. sizeof(*llcHdr);
  788. }
  789. } else {
  790. if (ether_type == htons(ETHERTYPE_8021Q)) {
  791. evh = (qdf_ethervlan_header_t *) eh;
  792. ether_type = evh->ether_type;
  793. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  794. }
  795. }
  796. /*
  797. * Find priority from IP TOS DSCP field
  798. */
  799. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  800. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  801. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  802. /* Only for unicast frames */
  803. if (!is_mcast) {
  804. /* send it on VO queue */
  805. msdu_info->tid = DP_VO_TID;
  806. }
  807. } else {
  808. /*
  809. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  810. * from TOS byte.
  811. */
  812. tos = ip->ip_tos;
  813. dscp_tid_override = 1;
  814. }
  815. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  816. /* TODO
  817. * use flowlabel
  818. *igmpmld cases to be handled in phase 2
  819. */
  820. unsigned long ver_pri_flowlabel;
  821. unsigned long pri;
  822. ver_pri_flowlabel = *(unsigned long *) L3datap;
  823. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  824. DP_IPV6_PRIORITY_SHIFT;
  825. tos = pri;
  826. dscp_tid_override = 1;
  827. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  828. msdu_info->tid = DP_VO_TID;
  829. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  830. /* Only for unicast frames */
  831. if (!is_mcast) {
  832. /* send ucast arp on VO queue */
  833. msdu_info->tid = DP_VO_TID;
  834. }
  835. }
  836. /*
  837. * Assign all MCAST packets to BE
  838. */
  839. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  840. if (is_mcast) {
  841. tos = 0;
  842. dscp_tid_override = 1;
  843. }
  844. }
  845. if (dscp_tid_override == 1) {
  846. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  847. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  848. }
  849. return;
  850. }
  851. #ifdef CONVERGED_TDLS_ENABLE
  852. /**
  853. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  854. * @tx_desc: TX descriptor
  855. *
  856. * Return: None
  857. */
  858. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  859. {
  860. if (tx_desc->vdev) {
  861. if (tx_desc->vdev->is_tdls_frame)
  862. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  863. tx_desc->vdev->is_tdls_frame = false;
  864. }
  865. }
  866. /**
  867. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  868. * @tx_desc: TX descriptor
  869. * @vdev: datapath vdev handle
  870. *
  871. * Return: None
  872. */
  873. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  874. struct dp_vdev *vdev)
  875. {
  876. struct hal_tx_completion_status ts = {0};
  877. qdf_nbuf_t nbuf = tx_desc->nbuf;
  878. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  879. if (vdev->tx_non_std_data_callback.func) {
  880. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  881. vdev->tx_non_std_data_callback.func(
  882. vdev->tx_non_std_data_callback.ctxt,
  883. nbuf, ts.status);
  884. return;
  885. }
  886. }
  887. #endif
  888. /**
  889. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  890. * @vdev: DP vdev handle
  891. * @nbuf: skb
  892. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  893. * @tx_q: Tx queue to be used for this Tx frame
  894. * @peer_id: peer_id of the peer in case of NAWDS frames
  895. *
  896. * Return: NULL on success,
  897. * nbuf when it fails to send
  898. */
  899. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  900. uint8_t tid, struct dp_tx_queue *tx_q,
  901. uint32_t *meta_data, uint16_t peer_id)
  902. {
  903. struct dp_pdev *pdev = vdev->pdev;
  904. struct dp_soc *soc = pdev->soc;
  905. struct dp_tx_desc_s *tx_desc;
  906. QDF_STATUS status;
  907. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  908. uint16_t htt_tcl_metadata = 0;
  909. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  910. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  911. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, meta_data);
  912. if (!tx_desc) {
  913. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  914. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  915. __func__, vdev, tx_q->desc_pool_id);
  916. return nbuf;
  917. }
  918. dp_tx_update_tdls_flags(tx_desc);
  919. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  920. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  921. "%s %d : HAL RING Access Failed -- %pK\n",
  922. __func__, __LINE__, hal_srng);
  923. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  924. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  925. goto fail_return;
  926. }
  927. if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  928. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  929. HTT_TCL_METADATA_TYPE_PEER_BASED);
  930. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  931. peer_id);
  932. } else
  933. htt_tcl_metadata = vdev->htt_tcl_metadata;
  934. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  935. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  936. htt_tcl_metadata, tx_q->ring_id);
  937. if (status != QDF_STATUS_SUCCESS) {
  938. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  939. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  940. __func__, tx_desc, tx_q->ring_id);
  941. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  942. goto fail_return;
  943. }
  944. nbuf = NULL;
  945. fail_return:
  946. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  947. hal_srng_access_end(soc->hal_soc, hal_srng);
  948. hif_pm_runtime_put(soc->hif_handle);
  949. } else {
  950. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  951. }
  952. return nbuf;
  953. }
  954. /**
  955. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  956. * @vdev: DP vdev handle
  957. * @nbuf: skb
  958. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  959. *
  960. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  961. *
  962. * Return: NULL on success,
  963. * nbuf when it fails to send
  964. */
  965. #if QDF_LOCK_STATS
  966. static noinline
  967. #else
  968. static
  969. #endif
  970. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  971. struct dp_tx_msdu_info_s *msdu_info)
  972. {
  973. uint8_t i;
  974. struct dp_pdev *pdev = vdev->pdev;
  975. struct dp_soc *soc = pdev->soc;
  976. struct dp_tx_desc_s *tx_desc;
  977. QDF_STATUS status;
  978. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  979. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  980. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  981. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  982. "%s %d : HAL RING Access Failed -- %pK\n",
  983. __func__, __LINE__, hal_srng);
  984. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  985. return nbuf;
  986. }
  987. if (msdu_info->frm_type == dp_tx_frm_me)
  988. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  989. i = 0;
  990. /* Print statement to track i and num_seg */
  991. /*
  992. * For each segment (maps to 1 MSDU) , prepare software and hardware
  993. * descriptors using information in msdu_info
  994. */
  995. while (i < msdu_info->num_seg) {
  996. /*
  997. * Setup Tx descriptor for an MSDU, and MSDU extension
  998. * descriptor
  999. */
  1000. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1001. tx_q->desc_pool_id);
  1002. if (!tx_desc) {
  1003. if (msdu_info->frm_type == dp_tx_frm_me) {
  1004. dp_tx_me_free_buf(pdev,
  1005. (void *)(msdu_info->u.sg_info
  1006. .curr_seg->frags[0].vaddr));
  1007. }
  1008. goto done;
  1009. }
  1010. if (msdu_info->frm_type == dp_tx_frm_me) {
  1011. tx_desc->me_buffer =
  1012. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1013. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1014. }
  1015. /*
  1016. * Enqueue the Tx MSDU descriptor to HW for transmit
  1017. */
  1018. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1019. vdev->htt_tcl_metadata, tx_q->ring_id);
  1020. if (status != QDF_STATUS_SUCCESS) {
  1021. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1022. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1023. __func__, tx_desc, tx_q->ring_id);
  1024. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1025. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1026. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1027. goto done;
  1028. }
  1029. /*
  1030. * TODO
  1031. * if tso_info structure can be modified to have curr_seg
  1032. * as first element, following 2 blocks of code (for TSO and SG)
  1033. * can be combined into 1
  1034. */
  1035. /*
  1036. * For frames with multiple segments (TSO, ME), jump to next
  1037. * segment.
  1038. */
  1039. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1040. if (msdu_info->u.tso_info.curr_seg->next) {
  1041. msdu_info->u.tso_info.curr_seg =
  1042. msdu_info->u.tso_info.curr_seg->next;
  1043. /*
  1044. * If this is a jumbo nbuf, then increment the number of
  1045. * nbuf users for each additional segment of the msdu.
  1046. * This will ensure that the skb is freed only after
  1047. * receiving tx completion for all segments of an nbuf
  1048. */
  1049. qdf_nbuf_inc_users(nbuf);
  1050. /* Check with MCL if this is needed */
  1051. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1052. }
  1053. }
  1054. /*
  1055. * For Multicast-Unicast converted packets,
  1056. * each converted frame (for a client) is represented as
  1057. * 1 segment
  1058. */
  1059. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1060. (msdu_info->frm_type == dp_tx_frm_me)) {
  1061. if (msdu_info->u.sg_info.curr_seg->next) {
  1062. msdu_info->u.sg_info.curr_seg =
  1063. msdu_info->u.sg_info.curr_seg->next;
  1064. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1065. }
  1066. }
  1067. i++;
  1068. }
  1069. nbuf = NULL;
  1070. done:
  1071. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1072. hal_srng_access_end(soc->hal_soc, hal_srng);
  1073. hif_pm_runtime_put(soc->hif_handle);
  1074. } else {
  1075. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1076. }
  1077. return nbuf;
  1078. }
  1079. /**
  1080. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1081. * for SG frames
  1082. * @vdev: DP vdev handle
  1083. * @nbuf: skb
  1084. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1085. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1086. *
  1087. * Return: NULL on success,
  1088. * nbuf when it fails to send
  1089. */
  1090. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1091. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1092. {
  1093. uint32_t cur_frag, nr_frags;
  1094. qdf_dma_addr_t paddr;
  1095. struct dp_tx_sg_info_s *sg_info;
  1096. sg_info = &msdu_info->u.sg_info;
  1097. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1098. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1099. QDF_DMA_TO_DEVICE)) {
  1100. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1101. "dma map error\n");
  1102. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1103. qdf_nbuf_free(nbuf);
  1104. return NULL;
  1105. }
  1106. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1107. seg_info->frags[0].paddr_lo = paddr;
  1108. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1109. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1110. seg_info->frags[0].vaddr = (void *) nbuf;
  1111. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1112. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1113. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1114. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1115. "frag dma map error\n");
  1116. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1117. qdf_nbuf_free(nbuf);
  1118. return NULL;
  1119. }
  1120. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1121. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1122. seg_info->frags[cur_frag + 1].paddr_hi =
  1123. ((uint64_t) paddr) >> 32;
  1124. seg_info->frags[cur_frag + 1].len =
  1125. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1126. }
  1127. seg_info->frag_cnt = (cur_frag + 1);
  1128. seg_info->total_len = qdf_nbuf_len(nbuf);
  1129. seg_info->next = NULL;
  1130. sg_info->curr_seg = seg_info;
  1131. msdu_info->frm_type = dp_tx_frm_sg;
  1132. msdu_info->num_seg = 1;
  1133. return nbuf;
  1134. }
  1135. #ifdef MESH_MODE_SUPPORT
  1136. /**
  1137. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1138. and prepare msdu_info for mesh frames.
  1139. * @vdev: DP vdev handle
  1140. * @nbuf: skb
  1141. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1142. *
  1143. * Return: NULL on failure,
  1144. * nbuf when extracted successfully
  1145. */
  1146. static
  1147. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1148. struct dp_tx_msdu_info_s *msdu_info)
  1149. {
  1150. struct meta_hdr_s *mhdr;
  1151. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1152. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1153. nbuf = qdf_nbuf_unshare(nbuf);
  1154. if (nbuf == NULL) {
  1155. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1156. "qdf_nbuf_unshare failed\n");
  1157. return nbuf;
  1158. }
  1159. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1160. qdf_mem_set(meta_data, 0, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1161. meta_data->host_tx_desc_pool = 1;
  1162. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1163. meta_data->power = mhdr->power;
  1164. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1165. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1166. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1167. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1168. meta_data->dyn_bw = 1;
  1169. meta_data->valid_pwr = 1;
  1170. meta_data->valid_mcs_mask = 1;
  1171. meta_data->valid_nss_mask = 1;
  1172. meta_data->valid_preamble_type = 1;
  1173. meta_data->valid_retries = 1;
  1174. meta_data->valid_bw_info = 1;
  1175. }
  1176. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1177. meta_data->encrypt_type = 0;
  1178. meta_data->valid_encrypt_type = 1;
  1179. }
  1180. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1181. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1182. else
  1183. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1184. meta_data->valid_key_flags = 1;
  1185. meta_data->key_flags = (mhdr->keyix & 0x3);
  1186. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1187. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1188. "qdf_nbuf_pull_head failed\n");
  1189. qdf_nbuf_free(nbuf);
  1190. return NULL;
  1191. }
  1192. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1193. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1194. __func__, msdu_info->meta_data[0],
  1195. msdu_info->meta_data[1],
  1196. msdu_info->meta_data[2],
  1197. msdu_info->meta_data[3],
  1198. msdu_info->meta_data[4]);
  1199. return nbuf;
  1200. }
  1201. #else
  1202. static
  1203. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1204. struct dp_tx_msdu_info_s *msdu_info)
  1205. {
  1206. return nbuf;
  1207. }
  1208. #endif
  1209. /**
  1210. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1211. * @vdev: dp_vdev handle
  1212. * @nbuf: skb
  1213. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1214. * @tx_q: Tx queue to be used for this Tx frame
  1215. * @meta_data: Meta date for mesh
  1216. * @peer_id: peer_id of the peer in case of NAWDS frames
  1217. *
  1218. * return: NULL on success nbuf on failure
  1219. */
  1220. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1221. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data,
  1222. uint32_t peer_id)
  1223. {
  1224. struct dp_peer *peer = NULL;
  1225. qdf_nbuf_t nbuf_copy;
  1226. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1227. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1228. (peer->nawds_enabled || peer->bss_peer)) {
  1229. nbuf_copy = qdf_nbuf_copy(nbuf);
  1230. if (!nbuf_copy) {
  1231. QDF_TRACE(QDF_MODULE_ID_DP,
  1232. QDF_TRACE_LEVEL_ERROR,
  1233. "nbuf copy failed");
  1234. }
  1235. peer_id = peer->peer_ids[0];
  1236. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1237. tx_q, meta_data, peer_id);
  1238. if (nbuf_copy != NULL) {
  1239. qdf_nbuf_free(nbuf);
  1240. return nbuf_copy;
  1241. }
  1242. }
  1243. }
  1244. if (peer_id == HTT_INVALID_PEER)
  1245. return nbuf;
  1246. qdf_nbuf_free(nbuf);
  1247. return NULL;
  1248. }
  1249. /**
  1250. * dp_tx_send() - Transmit a frame on a given VAP
  1251. * @vap_dev: DP vdev handle
  1252. * @nbuf: skb
  1253. *
  1254. * Entry point for Core Tx layer (DP_TX) invoked from
  1255. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1256. * cases
  1257. *
  1258. * Return: NULL on success,
  1259. * nbuf when it fails to send
  1260. */
  1261. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1262. {
  1263. struct ether_header *eh = NULL;
  1264. struct dp_tx_msdu_info_s msdu_info;
  1265. struct dp_tx_seg_info_s seg_info;
  1266. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1267. uint16_t peer_id = HTT_INVALID_PEER;
  1268. qdf_nbuf_t nbuf_mesh = NULL;
  1269. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1270. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1271. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1272. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1273. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1274. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1275. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1276. /*
  1277. * Set Default Host TID value to invalid TID
  1278. * (TID override disabled)
  1279. */
  1280. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1281. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1282. if (qdf_unlikely(vdev->mesh_vdev)) {
  1283. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1284. &msdu_info);
  1285. if (nbuf_mesh == NULL) {
  1286. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1287. "Extracting mesh metadata failed\n");
  1288. return nbuf;
  1289. }
  1290. nbuf = nbuf_mesh;
  1291. }
  1292. /*
  1293. * Get HW Queue to use for this frame.
  1294. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1295. * dedicated for data and 1 for command.
  1296. * "queue_id" maps to one hardware ring.
  1297. * With each ring, we also associate a unique Tx descriptor pool
  1298. * to minimize lock contention for these resources.
  1299. */
  1300. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1301. /*
  1302. * TCL H/W supports 2 DSCP-TID mapping tables.
  1303. * Table 1 - Default DSCP-TID mapping table
  1304. * Table 2 - 1 DSCP-TID override table
  1305. *
  1306. * If we need a different DSCP-TID mapping for this vap,
  1307. * call tid_classify to extract DSCP/ToS from frame and
  1308. * map to a TID and store in msdu_info. This is later used
  1309. * to fill in TCL Input descriptor (per-packet TID override).
  1310. */
  1311. if (vdev->dscp_tid_map_id > 1)
  1312. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1313. /* Reset the control block */
  1314. qdf_nbuf_reset_ctxt(nbuf);
  1315. /*
  1316. * Classify the frame and call corresponding
  1317. * "prepare" function which extracts the segment (TSO)
  1318. * and fragmentation information (for TSO , SG, ME, or Raw)
  1319. * into MSDU_INFO structure which is later used to fill
  1320. * SW and HW descriptors.
  1321. */
  1322. if (qdf_nbuf_is_tso(nbuf)) {
  1323. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1324. "%s TSO frame %pK\n", __func__, vdev);
  1325. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1326. qdf_nbuf_len(nbuf));
  1327. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1328. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1329. return nbuf;
  1330. }
  1331. goto send_multiple;
  1332. }
  1333. /* SG */
  1334. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1335. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1336. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1337. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1338. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1339. qdf_nbuf_len(nbuf));
  1340. goto send_multiple;
  1341. }
  1342. #ifdef ATH_SUPPORT_IQUE
  1343. /* Mcast to Ucast Conversion*/
  1344. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1345. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1346. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1347. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1348. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1349. DP_STATS_INC_PKT(vdev,
  1350. tx_i.mcast_en.mcast_pkt, 1,
  1351. qdf_nbuf_len(nbuf));
  1352. if (dp_tx_prepare_send_me(vdev, nbuf)) {
  1353. qdf_nbuf_free(nbuf);
  1354. return NULL;
  1355. }
  1356. return nbuf;
  1357. }
  1358. }
  1359. #endif
  1360. /* RAW */
  1361. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1362. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1363. if (nbuf == NULL)
  1364. return NULL;
  1365. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1366. "%s Raw frame %pK\n", __func__, vdev);
  1367. goto send_multiple;
  1368. }
  1369. if (vdev->nawds_enabled) {
  1370. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1371. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1372. nbuf = dp_tx_prepare_nawds(vdev, nbuf, msdu_info.tid,
  1373. &msdu_info.tx_queue,
  1374. msdu_info.meta_data, peer_id);
  1375. return nbuf;
  1376. }
  1377. }
  1378. /* Single linear frame */
  1379. /*
  1380. * If nbuf is a simple linear frame, use send_single function to
  1381. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1382. * SRNG. There is no need to setup a MSDU extension descriptor.
  1383. */
  1384. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1385. &msdu_info.tx_queue, msdu_info.meta_data, peer_id);
  1386. return nbuf;
  1387. send_multiple:
  1388. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1389. return nbuf;
  1390. }
  1391. /**
  1392. * dp_tx_reinject_handler() - Tx Reinject Handler
  1393. * @tx_desc: software descriptor head pointer
  1394. * @status : Tx completion status from HTT descriptor
  1395. *
  1396. * This function reinjects frames back to Target.
  1397. * Todo - Host queue needs to be added
  1398. *
  1399. * Return: none
  1400. */
  1401. static
  1402. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1403. {
  1404. struct dp_vdev *vdev;
  1405. struct dp_peer *peer = NULL;
  1406. uint32_t peer_id = HTT_INVALID_PEER;
  1407. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1408. qdf_nbuf_t nbuf_copy = NULL;
  1409. struct dp_tx_msdu_info_s msdu_info;
  1410. vdev = tx_desc->vdev;
  1411. qdf_assert(vdev);
  1412. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1413. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1414. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1415. "%s Tx reinject path\n", __func__);
  1416. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1417. qdf_nbuf_len(tx_desc->nbuf));
  1418. if (!vdev->osif_proxy_arp) {
  1419. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1420. "function pointer to proxy arp not present\n");
  1421. return;
  1422. }
  1423. if (qdf_unlikely(vdev->mesh_vdev)) {
  1424. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1425. } else {
  1426. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1427. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1428. (peer->bss_peer || peer->nawds_enabled)
  1429. && !(vdev->osif_proxy_arp(
  1430. vdev->osif_vdev,
  1431. nbuf))) {
  1432. nbuf_copy = qdf_nbuf_copy(nbuf);
  1433. if (!nbuf_copy) {
  1434. QDF_TRACE(QDF_MODULE_ID_DP,
  1435. QDF_TRACE_LEVEL_DEBUG,
  1436. FL("nbuf copy failed"));
  1437. break;
  1438. }
  1439. if (peer->nawds_enabled)
  1440. peer_id = peer->peer_ids[0];
  1441. else
  1442. peer_id = HTT_INVALID_PEER;
  1443. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1444. nbuf_copy, msdu_info.tid,
  1445. &msdu_info.tx_queue,
  1446. msdu_info.meta_data, peer_id);
  1447. if (nbuf_copy) {
  1448. QDF_TRACE(QDF_MODULE_ID_DP,
  1449. QDF_TRACE_LEVEL_DEBUG,
  1450. FL("pkt send failed"));
  1451. qdf_nbuf_free(nbuf_copy);
  1452. }
  1453. }
  1454. }
  1455. }
  1456. qdf_nbuf_free(nbuf);
  1457. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1458. }
  1459. /**
  1460. * dp_tx_inspect_handler() - Tx Inspect Handler
  1461. * @tx_desc: software descriptor head pointer
  1462. * @status : Tx completion status from HTT descriptor
  1463. *
  1464. * Handles Tx frames sent back to Host for inspection
  1465. * (ProxyARP)
  1466. *
  1467. * Return: none
  1468. */
  1469. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1470. {
  1471. struct dp_soc *soc;
  1472. struct dp_pdev *pdev = tx_desc->pdev;
  1473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1474. "%s Tx inspect path\n",
  1475. __func__);
  1476. qdf_assert(pdev);
  1477. soc = pdev->soc;
  1478. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1479. qdf_nbuf_len(tx_desc->nbuf));
  1480. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1481. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1482. }
  1483. #ifdef FEATURE_PERPKT_INFO
  1484. static QDF_STATUS
  1485. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  1486. uint16_t peer_id, uint32_t ppdu_id)
  1487. {
  1488. struct tx_capture_hdr *ppdu_hdr;
  1489. struct dp_peer *peer = NULL;
  1490. qdf_nbuf_t netbuf = desc->nbuf;
  1491. if (!desc->pdev->tx_sniffer_enable)
  1492. return QDF_STATUS_E_NOSUPPORT;
  1493. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1494. dp_peer_find_by_id(soc, peer_id);
  1495. if (!peer) {
  1496. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1497. FL("Peer Invalid"));
  1498. return QDF_STATUS_E_INVAL;
  1499. }
  1500. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1502. FL("No headroom"));
  1503. return QDF_STATUS_E_NOMEM;
  1504. }
  1505. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1506. qdf_mem_copy(ppdu_hdr->ta, desc->vdev->mac_addr.raw, IEEE80211_ADDR_LEN);
  1507. ppdu_hdr->ppdu_id = ppdu_id;
  1508. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1509. IEEE80211_ADDR_LEN);
  1510. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1511. netbuf, peer_id,
  1512. WDI_NO_VAL, desc->pdev->pdev_id);
  1513. return QDF_STATUS_SUCCESS;
  1514. }
  1515. #else
  1516. static QDF_STATUS
  1517. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  1518. uint16_t peer_id, uint32_t ppdu_id)
  1519. {
  1520. return QDF_STATUS_E_NOSUPPORT;
  1521. }
  1522. #endif
  1523. /**
  1524. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1525. * @soc: Soc handle
  1526. * @desc: software Tx descriptor to be processed
  1527. *
  1528. * Return: none
  1529. */
  1530. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1531. struct dp_tx_desc_s *desc)
  1532. {
  1533. struct dp_vdev *vdev = desc->vdev;
  1534. qdf_nbuf_t nbuf = desc->nbuf;
  1535. struct hal_tx_completion_status ts = {0};
  1536. if (desc)
  1537. hal_tx_comp_get_status(&desc->comp, &ts);
  1538. /* If it is TDLS mgmt, don't unmap or free the frame */
  1539. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1540. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1541. /* 0 : MSDU buffer, 1 : MLE */
  1542. if (desc->msdu_ext_desc) {
  1543. /* TSO free */
  1544. if (hal_tx_ext_desc_get_tso_enable(
  1545. desc->msdu_ext_desc->vaddr)) {
  1546. /* If remaining number of segment is 0
  1547. * actual TSO may unmap and free */
  1548. if (!DP_DESC_NUM_FRAG(desc)) {
  1549. qdf_nbuf_unmap(soc->osdev, nbuf,
  1550. QDF_DMA_TO_DEVICE);
  1551. qdf_nbuf_free(nbuf);
  1552. return;
  1553. }
  1554. }
  1555. }
  1556. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1557. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1558. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1559. if (dp_send_compl_to_stack(soc, desc, ts.peer_id, ts.ppdu_id) ==
  1560. QDF_STATUS_SUCCESS)
  1561. return;
  1562. if (!vdev->mesh_vdev) {
  1563. qdf_nbuf_free(nbuf);
  1564. } else {
  1565. vdev->osif_tx_free_ext((nbuf));
  1566. }
  1567. }
  1568. /**
  1569. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1570. * @vdev: pointer to dp dev handler
  1571. * @status : Tx completion status from HTT descriptor
  1572. *
  1573. * Handles MEC notify event sent from fw to Host
  1574. *
  1575. * Return: none
  1576. */
  1577. #ifdef FEATURE_WDS
  1578. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1579. {
  1580. struct dp_soc *soc;
  1581. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1582. struct dp_peer *peer;
  1583. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1584. soc = vdev->pdev->soc;
  1585. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1586. peer = TAILQ_FIRST(&vdev->peer_list);
  1587. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1588. if (!peer) {
  1589. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1590. FL("peer is NULL"));
  1591. return;
  1592. }
  1593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1594. "%s Tx MEC Handler\n",
  1595. __func__);
  1596. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1597. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1598. status[(DP_MAC_ADDR_LEN - 2) + i];
  1599. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN) &&
  1600. !dp_peer_add_ast(soc, peer, mac_addr, 2)) {
  1601. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1602. vdev->pdev->osif_pdev,
  1603. mac_addr,
  1604. vdev->mac_addr.raw,
  1605. flags);
  1606. }
  1607. }
  1608. #else
  1609. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1610. {
  1611. }
  1612. #endif
  1613. /**
  1614. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1615. * @tx_desc: software descriptor head pointer
  1616. * @status : Tx completion status from HTT descriptor
  1617. *
  1618. * This function will process HTT Tx indication messages from Target
  1619. *
  1620. * Return: none
  1621. */
  1622. static
  1623. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1624. {
  1625. uint8_t tx_status;
  1626. struct dp_pdev *pdev;
  1627. struct dp_vdev *vdev;
  1628. struct dp_soc *soc;
  1629. uint32_t *htt_status_word = (uint32_t *) status;
  1630. qdf_assert(tx_desc->pdev);
  1631. pdev = tx_desc->pdev;
  1632. vdev = tx_desc->vdev;
  1633. soc = pdev->soc;
  1634. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1635. switch (tx_status) {
  1636. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1637. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1638. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1639. {
  1640. dp_tx_comp_free_buf(soc, tx_desc);
  1641. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1642. break;
  1643. }
  1644. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1645. {
  1646. dp_tx_reinject_handler(tx_desc, status);
  1647. break;
  1648. }
  1649. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1650. {
  1651. dp_tx_inspect_handler(tx_desc, status);
  1652. break;
  1653. }
  1654. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  1655. {
  1656. dp_tx_mec_handler(vdev, status);
  1657. break;
  1658. }
  1659. default:
  1660. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1661. "%s Invalid HTT tx_status %d\n",
  1662. __func__, tx_status);
  1663. break;
  1664. }
  1665. }
  1666. #ifdef MESH_MODE_SUPPORT
  1667. /**
  1668. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1669. * in mesh meta header
  1670. * @tx_desc: software descriptor head pointer
  1671. * @ts: pointer to tx completion stats
  1672. * Return: none
  1673. */
  1674. static
  1675. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1676. struct hal_tx_completion_status *ts)
  1677. {
  1678. struct meta_hdr_s *mhdr;
  1679. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1680. if (!tx_desc->msdu_ext_desc) {
  1681. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  1682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1683. "netbuf %pK offset %d\n",
  1684. netbuf, tx_desc->pkt_offset);
  1685. return;
  1686. }
  1687. }
  1688. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1689. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1690. "netbuf %pK offset %d\n", netbuf,
  1691. sizeof(struct meta_hdr_s));
  1692. return;
  1693. }
  1694. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1695. mhdr->rssi = ts->ack_frame_rssi;
  1696. mhdr->channel = tx_desc->pdev->operating_channel;
  1697. }
  1698. #else
  1699. static
  1700. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1701. struct hal_tx_completion_status *ts)
  1702. {
  1703. }
  1704. #endif
  1705. /**
  1706. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  1707. * @peer: Handle to DP peer
  1708. * @ts: pointer to HAL Tx completion stats
  1709. * @length: MSDU length
  1710. *
  1711. * Return: None
  1712. */
  1713. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  1714. struct hal_tx_completion_status *ts, uint32_t length)
  1715. {
  1716. struct dp_pdev *pdev = peer->vdev->pdev;
  1717. struct dp_soc *soc = pdev->soc;
  1718. uint8_t mcs, pkt_type;
  1719. mcs = ts->mcs;
  1720. pkt_type = ts->pkt_type;
  1721. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  1722. return;
  1723. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  1724. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  1725. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  1726. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  1727. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  1728. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  1729. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  1730. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  1731. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  1732. return;
  1733. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  1734. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  1735. if (!(soc->process_tx_status))
  1736. return;
  1737. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1738. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  1739. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1740. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  1741. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1742. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  1743. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1744. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  1745. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1746. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  1747. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1748. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  1749. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1750. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  1751. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1752. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  1753. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  1754. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  1755. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  1756. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  1757. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  1758. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  1759. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  1760. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  1761. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  1762. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  1763. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  1764. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  1765. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  1766. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  1767. &peer->stats, ts->peer_id,
  1768. UPDATE_PEER_STATS);
  1769. }
  1770. }
  1771. /**
  1772. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  1773. * @tx_desc: software descriptor head pointer
  1774. * @length: packet length
  1775. *
  1776. * Return: none
  1777. */
  1778. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  1779. uint32_t length)
  1780. {
  1781. struct hal_tx_completion_status ts;
  1782. struct dp_soc *soc = NULL;
  1783. struct dp_vdev *vdev = tx_desc->vdev;
  1784. struct dp_peer *peer = NULL;
  1785. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1786. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1787. "-------------------- \n"
  1788. "Tx Completion Stats: \n"
  1789. "-------------------- \n"
  1790. "ack_frame_rssi = %d \n"
  1791. "first_msdu = %d \n"
  1792. "last_msdu = %d \n"
  1793. "msdu_part_of_amsdu = %d \n"
  1794. "rate_stats valid = %d \n"
  1795. "bw = %d \n"
  1796. "pkt_type = %d \n"
  1797. "stbc = %d \n"
  1798. "ldpc = %d \n"
  1799. "sgi = %d \n"
  1800. "mcs = %d \n"
  1801. "ofdma = %d \n"
  1802. "tones_in_ru = %d \n"
  1803. "tsf = %d \n"
  1804. "ppdu_id = %d \n"
  1805. "transmit_cnt = %d \n"
  1806. "tid = %d \n"
  1807. "peer_id = %d \n",
  1808. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  1809. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  1810. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  1811. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  1812. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  1813. ts.peer_id);
  1814. if (!vdev) {
  1815. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1816. "invalid vdev");
  1817. goto out;
  1818. }
  1819. soc = vdev->pdev->soc;
  1820. /* Update SoC level stats */
  1821. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  1822. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  1823. /* Update per-packet stats */
  1824. if (qdf_unlikely(vdev->mesh_vdev))
  1825. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  1826. /* Update peer level stats */
  1827. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1828. if (!peer) {
  1829. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1830. "invalid peer");
  1831. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  1832. goto out;
  1833. }
  1834. dp_tx_update_peer_stats(peer, &ts, length);
  1835. out:
  1836. return;
  1837. }
  1838. /**
  1839. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  1840. * @soc: core txrx main context
  1841. * @comp_head: software descriptor head pointer
  1842. *
  1843. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  1844. * and release the software descriptors after processing is complete
  1845. *
  1846. * Return: none
  1847. */
  1848. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  1849. struct dp_tx_desc_s *comp_head)
  1850. {
  1851. struct dp_tx_desc_s *desc;
  1852. struct dp_tx_desc_s *next;
  1853. struct hal_tx_completion_status ts = {0};
  1854. uint32_t length;
  1855. struct dp_peer *peer;
  1856. DP_HIST_INIT();
  1857. desc = comp_head;
  1858. while (desc) {
  1859. hal_tx_comp_get_status(&desc->comp, &ts);
  1860. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1861. length = qdf_nbuf_len(desc->nbuf);
  1862. /* Process Tx status in descriptor */
  1863. if (soc->process_tx_status ||
  1864. (desc->vdev && desc->vdev->mesh_vdev))
  1865. dp_tx_comp_process_tx_status(desc, length);
  1866. dp_tx_comp_free_buf(soc, desc);
  1867. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  1868. next = desc->next;
  1869. dp_tx_desc_release(desc, desc->pool_id);
  1870. desc = next;
  1871. }
  1872. DP_TX_HIST_STATS_PER_PDEV();
  1873. }
  1874. /**
  1875. * dp_tx_comp_handler() - Tx completion handler
  1876. * @soc: core txrx main context
  1877. * @ring_id: completion ring id
  1878. * @quota: No. of packets/descriptors that can be serviced in one loop
  1879. *
  1880. * This function will collect hardware release ring element contents and
  1881. * handle descriptor contents. Based on contents, free packet or handle error
  1882. * conditions
  1883. *
  1884. * Return: none
  1885. */
  1886. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  1887. {
  1888. void *tx_comp_hal_desc;
  1889. uint8_t buffer_src;
  1890. uint8_t pool_id;
  1891. uint32_t tx_desc_id;
  1892. struct dp_tx_desc_s *tx_desc = NULL;
  1893. struct dp_tx_desc_s *head_desc = NULL;
  1894. struct dp_tx_desc_s *tail_desc = NULL;
  1895. uint32_t num_processed;
  1896. uint32_t count;
  1897. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1898. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1899. "%s %d : HAL RING Access Failed -- %pK\n",
  1900. __func__, __LINE__, hal_srng);
  1901. return 0;
  1902. }
  1903. num_processed = 0;
  1904. count = 0;
  1905. /* Find head descriptor from completion ring */
  1906. while (qdf_likely(tx_comp_hal_desc =
  1907. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  1908. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  1909. /* If this buffer was not released by TQM or FW, then it is not
  1910. * Tx completion indication, assert */
  1911. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  1912. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1913. QDF_TRACE(QDF_MODULE_ID_DP,
  1914. QDF_TRACE_LEVEL_FATAL,
  1915. "Tx comp release_src != TQM | FW");
  1916. qdf_assert_always(0);
  1917. }
  1918. /* Get descriptor id */
  1919. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  1920. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  1921. DP_TX_DESC_ID_POOL_OS;
  1922. /* Pool ID is out of limit. Error */
  1923. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  1924. soc->wlan_cfg_ctx)) {
  1925. QDF_TRACE(QDF_MODULE_ID_DP,
  1926. QDF_TRACE_LEVEL_FATAL,
  1927. "Tx Comp pool id %d not valid",
  1928. pool_id);
  1929. qdf_assert_always(0);
  1930. }
  1931. /* Find Tx descriptor */
  1932. tx_desc = dp_tx_desc_find(soc, pool_id,
  1933. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  1934. DP_TX_DESC_ID_PAGE_OS,
  1935. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  1936. DP_TX_DESC_ID_OFFSET_OS);
  1937. /* Pool id is not matching. Error */
  1938. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  1939. QDF_TRACE(QDF_MODULE_ID_DP,
  1940. QDF_TRACE_LEVEL_FATAL,
  1941. "Tx Comp pool id %d not matched %d",
  1942. pool_id, tx_desc->pool_id);
  1943. qdf_assert_always(0);
  1944. }
  1945. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  1946. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  1947. QDF_TRACE(QDF_MODULE_ID_DP,
  1948. QDF_TRACE_LEVEL_FATAL,
  1949. "Txdesc invalid, flgs = %x,id = %d",
  1950. tx_desc->flags, tx_desc_id);
  1951. qdf_assert_always(0);
  1952. }
  1953. /*
  1954. * If the release source is FW, process the HTT status
  1955. */
  1956. if (qdf_unlikely(buffer_src ==
  1957. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1958. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1959. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  1960. htt_tx_status);
  1961. dp_tx_process_htt_completion(tx_desc,
  1962. htt_tx_status);
  1963. } else {
  1964. /* First ring descriptor on the cycle */
  1965. if (!head_desc) {
  1966. head_desc = tx_desc;
  1967. tail_desc = tx_desc;
  1968. }
  1969. tail_desc->next = tx_desc;
  1970. tx_desc->next = NULL;
  1971. tail_desc = tx_desc;
  1972. /* Collect hw completion contents */
  1973. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1974. &tx_desc->comp, soc->process_tx_status);
  1975. }
  1976. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  1977. /* Decrement PM usage count if the packet has been sent.*/
  1978. hif_pm_runtime_put(soc->hif_handle);
  1979. /*
  1980. * Processed packet count is more than given quota
  1981. * stop to processing
  1982. */
  1983. if ((num_processed >= quota))
  1984. break;
  1985. count++;
  1986. }
  1987. hal_srng_access_end(soc->hal_soc, hal_srng);
  1988. /* Process the reaped descriptors */
  1989. if (head_desc)
  1990. dp_tx_comp_process_desc(soc, head_desc);
  1991. return num_processed;
  1992. }
  1993. #ifdef CONVERGED_TDLS_ENABLE
  1994. /**
  1995. * dp_tx_non_std() - Allow the control-path SW to send data frames
  1996. *
  1997. * @data_vdev - which vdev should transmit the tx data frames
  1998. * @tx_spec - what non-standard handling to apply to the tx data frames
  1999. * @msdu_list - NULL-terminated list of tx MSDUs
  2000. *
  2001. * Return: NULL on success,
  2002. * nbuf when it fails to send
  2003. */
  2004. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2005. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2006. {
  2007. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2008. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2009. vdev->is_tdls_frame = true;
  2010. return dp_tx_send(vdev_handle, msdu_list);
  2011. }
  2012. #endif
  2013. /**
  2014. * dp_tx_vdev_attach() - attach vdev to dp tx
  2015. * @vdev: virtual device instance
  2016. *
  2017. * Return: QDF_STATUS_SUCCESS: success
  2018. * QDF_STATUS_E_RESOURCES: Error return
  2019. */
  2020. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2021. {
  2022. /*
  2023. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2024. */
  2025. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2026. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2027. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2028. vdev->vdev_id);
  2029. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2030. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2031. /*
  2032. * Set HTT Extension Valid bit to 0 by default
  2033. */
  2034. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2035. dp_tx_vdev_update_search_flags(vdev);
  2036. return QDF_STATUS_SUCCESS;
  2037. }
  2038. /**
  2039. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2040. * @vdev: virtual device instance
  2041. *
  2042. * Return: void
  2043. *
  2044. */
  2045. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2046. {
  2047. /*
  2048. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2049. * for TDLS link
  2050. *
  2051. * Enable AddrY (SA based search) only for non-WDS STA and
  2052. * ProxySTA VAP modes.
  2053. *
  2054. * In all other VAP modes, only DA based search should be
  2055. * enabled
  2056. */
  2057. if (vdev->opmode == wlan_op_mode_sta &&
  2058. vdev->tdls_link_connected)
  2059. vdev->hal_desc_addr_search_flags =
  2060. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2061. else if ((vdev->opmode == wlan_op_mode_sta &&
  2062. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2063. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2064. else
  2065. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2066. }
  2067. /**
  2068. * dp_tx_vdev_detach() - detach vdev from dp tx
  2069. * @vdev: virtual device instance
  2070. *
  2071. * Return: QDF_STATUS_SUCCESS: success
  2072. * QDF_STATUS_E_RESOURCES: Error return
  2073. */
  2074. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2075. {
  2076. return QDF_STATUS_SUCCESS;
  2077. }
  2078. /**
  2079. * dp_tx_pdev_attach() - attach pdev to dp tx
  2080. * @pdev: physical device instance
  2081. *
  2082. * Return: QDF_STATUS_SUCCESS: success
  2083. * QDF_STATUS_E_RESOURCES: Error return
  2084. */
  2085. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2086. {
  2087. struct dp_soc *soc = pdev->soc;
  2088. /* Initialize Flow control counters */
  2089. qdf_atomic_init(&pdev->num_tx_exception);
  2090. qdf_atomic_init(&pdev->num_tx_outstanding);
  2091. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2092. /* Initialize descriptors in TCL Ring */
  2093. hal_tx_init_data_ring(soc->hal_soc,
  2094. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2095. }
  2096. return QDF_STATUS_SUCCESS;
  2097. }
  2098. /**
  2099. * dp_tx_pdev_detach() - detach pdev from dp tx
  2100. * @pdev: physical device instance
  2101. *
  2102. * Return: QDF_STATUS_SUCCESS: success
  2103. * QDF_STATUS_E_RESOURCES: Error return
  2104. */
  2105. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2106. {
  2107. /* What should do here? */
  2108. return QDF_STATUS_SUCCESS;
  2109. }
  2110. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2111. /* Pools will be allocated dynamically */
  2112. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2113. int num_desc)
  2114. {
  2115. uint8_t i;
  2116. for (i = 0; i < num_pool; i++) {
  2117. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2118. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2119. }
  2120. return 0;
  2121. }
  2122. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2123. {
  2124. uint8_t i;
  2125. for (i = 0; i < num_pool; i++)
  2126. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2127. }
  2128. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2129. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2130. int num_desc)
  2131. {
  2132. uint8_t i;
  2133. /* Allocate software Tx descriptor pools */
  2134. for (i = 0; i < num_pool; i++) {
  2135. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2136. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2137. "%s Tx Desc Pool alloc %d failed %pK\n",
  2138. __func__, i, soc);
  2139. return ENOMEM;
  2140. }
  2141. }
  2142. return 0;
  2143. }
  2144. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2145. {
  2146. uint8_t i;
  2147. for (i = 0; i < num_pool; i++) {
  2148. if (dp_tx_desc_pool_free(soc, i)) {
  2149. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2150. "%s Tx Desc Pool Free failed\n", __func__);
  2151. }
  2152. }
  2153. }
  2154. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2155. /**
  2156. * dp_tx_soc_detach() - detach soc from dp tx
  2157. * @soc: core txrx main context
  2158. *
  2159. * This function will detach dp tx into main device context
  2160. * will free dp tx resource and initialize resources
  2161. *
  2162. * Return: QDF_STATUS_SUCCESS: success
  2163. * QDF_STATUS_E_RESOURCES: Error return
  2164. */
  2165. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2166. {
  2167. uint8_t num_pool;
  2168. uint16_t num_desc;
  2169. uint16_t num_ext_desc;
  2170. uint8_t i;
  2171. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2172. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2173. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2174. dp_tx_flow_control_deinit(soc);
  2175. dp_tx_delete_static_pools(soc, num_pool);
  2176. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2177. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2178. __func__, num_pool, num_desc);
  2179. for (i = 0; i < num_pool; i++) {
  2180. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2182. "%s Tx Ext Desc Pool Free failed\n",
  2183. __func__);
  2184. return QDF_STATUS_E_RESOURCES;
  2185. }
  2186. }
  2187. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2188. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2189. __func__, num_pool, num_ext_desc);
  2190. for (i = 0; i < num_pool; i++) {
  2191. dp_tx_tso_desc_pool_free(soc, i);
  2192. }
  2193. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2194. "%s TSO Desc Pool %d Free descs = %d\n",
  2195. __func__, num_pool, num_desc);
  2196. for (i = 0; i < num_pool; i++)
  2197. dp_tx_tso_num_seg_pool_free(soc, i);
  2198. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2199. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2200. __func__, num_pool, num_desc);
  2201. return QDF_STATUS_SUCCESS;
  2202. }
  2203. /**
  2204. * dp_tx_soc_attach() - attach soc to dp tx
  2205. * @soc: core txrx main context
  2206. *
  2207. * This function will attach dp tx into main device context
  2208. * will allocate dp tx resource and initialize resources
  2209. *
  2210. * Return: QDF_STATUS_SUCCESS: success
  2211. * QDF_STATUS_E_RESOURCES: Error return
  2212. */
  2213. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2214. {
  2215. uint8_t i;
  2216. uint8_t num_pool;
  2217. uint32_t num_desc;
  2218. uint32_t num_ext_desc;
  2219. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2220. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2221. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2222. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2223. goto fail;
  2224. dp_tx_flow_control_init(soc);
  2225. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2226. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2227. __func__, num_pool, num_desc);
  2228. /* Allocate extension tx descriptor pools */
  2229. for (i = 0; i < num_pool; i++) {
  2230. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2231. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2232. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2233. i, soc);
  2234. goto fail;
  2235. }
  2236. }
  2237. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2238. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2239. __func__, num_pool, num_ext_desc);
  2240. for (i = 0; i < num_pool; i++) {
  2241. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2242. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2243. "TSO Desc Pool alloc %d failed %pK\n",
  2244. i, soc);
  2245. goto fail;
  2246. }
  2247. }
  2248. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2249. "%s TSO Desc Alloc %d, descs = %d\n",
  2250. __func__, num_pool, num_desc);
  2251. for (i = 0; i < num_pool; i++) {
  2252. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2254. "TSO Num of seg Pool alloc %d failed %pK\n",
  2255. i, soc);
  2256. goto fail;
  2257. }
  2258. }
  2259. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2260. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2261. __func__, num_pool, num_desc);
  2262. /* Initialize descriptors in TCL Rings */
  2263. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2264. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2265. hal_tx_init_data_ring(soc->hal_soc,
  2266. soc->tcl_data_ring[i].hal_srng);
  2267. }
  2268. }
  2269. /*
  2270. * todo - Add a runtime config option to enable this.
  2271. */
  2272. /*
  2273. * Due to multiple issues on NPR EMU, enable it selectively
  2274. * only for NPR EMU, should be removed, once NPR platforms
  2275. * are stable.
  2276. */
  2277. soc->process_tx_status = 0;
  2278. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2279. "%s HAL Tx init Success\n", __func__);
  2280. return QDF_STATUS_SUCCESS;
  2281. fail:
  2282. /* Detach will take care of freeing only allocated resources */
  2283. dp_tx_soc_detach(soc);
  2284. return QDF_STATUS_E_RESOURCES;
  2285. }
  2286. /*
  2287. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2288. * pdev: pointer to DP PDEV structure
  2289. * seg_info_head: Pointer to the head of list
  2290. *
  2291. * return: void
  2292. */
  2293. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2294. struct dp_tx_seg_info_s *seg_info_head)
  2295. {
  2296. struct dp_tx_me_buf_t *mc_uc_buf;
  2297. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2298. qdf_nbuf_t nbuf = NULL;
  2299. uint64_t phy_addr;
  2300. while (seg_info_head) {
  2301. nbuf = seg_info_head->nbuf;
  2302. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2303. seg_info_new->frags[0].vaddr;
  2304. phy_addr = seg_info_head->frags[0].paddr_hi;
  2305. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2306. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2307. phy_addr,
  2308. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2309. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2310. qdf_nbuf_free(nbuf);
  2311. seg_info_new = seg_info_head;
  2312. seg_info_head = seg_info_head->next;
  2313. qdf_mem_free(seg_info_new);
  2314. }
  2315. }
  2316. /**
  2317. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2318. * @vdev: DP VDEV handle
  2319. * @nbuf: Multicast nbuf
  2320. * @newmac: Table of the clients to which packets have to be sent
  2321. * @new_mac_cnt: No of clients
  2322. *
  2323. * return: no of converted packets
  2324. */
  2325. uint16_t
  2326. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2327. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2328. {
  2329. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2330. struct dp_pdev *pdev = vdev->pdev;
  2331. struct ether_header *eh;
  2332. uint8_t *data;
  2333. uint16_t len;
  2334. /* reference to frame dst addr */
  2335. uint8_t *dstmac;
  2336. /* copy of original frame src addr */
  2337. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2338. /* local index into newmac */
  2339. uint8_t new_mac_idx = 0;
  2340. struct dp_tx_me_buf_t *mc_uc_buf;
  2341. qdf_nbuf_t nbuf_clone;
  2342. struct dp_tx_msdu_info_s msdu_info;
  2343. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2344. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2345. struct dp_tx_seg_info_s *seg_info_new;
  2346. struct dp_tx_frag_info_s data_frag;
  2347. qdf_dma_addr_t paddr_data;
  2348. qdf_dma_addr_t paddr_mcbuf = 0;
  2349. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2350. QDF_STATUS status;
  2351. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2352. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2353. eh = (struct ether_header *) nbuf;
  2354. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2355. len = qdf_nbuf_len(nbuf);
  2356. data = qdf_nbuf_data(nbuf);
  2357. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2358. QDF_DMA_TO_DEVICE);
  2359. if (status) {
  2360. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2361. "Mapping failure Error:%d", status);
  2362. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2363. return 0;
  2364. }
  2365. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2366. /*preparing data fragment*/
  2367. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2368. data_frag.paddr_lo = (uint32_t)paddr_data;
  2369. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2370. data_frag.len = len - DP_MAC_ADDR_LEN;
  2371. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2372. dstmac = newmac[new_mac_idx];
  2373. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2374. "added mac addr (%pM)", dstmac);
  2375. /* Check for NULL Mac Address */
  2376. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2377. continue;
  2378. /* frame to self mac. skip */
  2379. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2380. continue;
  2381. /*
  2382. * TODO: optimize to avoid malloc in per-packet path
  2383. * For eg. seg_pool can be made part of vdev structure
  2384. */
  2385. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2386. if (!seg_info_new) {
  2387. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2388. "alloc failed");
  2389. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2390. goto fail_seg_alloc;
  2391. }
  2392. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2393. if (mc_uc_buf == NULL)
  2394. goto fail_buf_alloc;
  2395. /*
  2396. * TODO: Check if we need to clone the nbuf
  2397. * Or can we just use the reference for all cases
  2398. */
  2399. if (new_mac_idx < (new_mac_cnt - 1)) {
  2400. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2401. if (nbuf_clone == NULL) {
  2402. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2403. goto fail_clone;
  2404. }
  2405. } else {
  2406. /*
  2407. * Update the ref
  2408. * to account for frame sent without cloning
  2409. */
  2410. qdf_nbuf_ref(nbuf);
  2411. nbuf_clone = nbuf;
  2412. }
  2413. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2414. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2415. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2416. &paddr_mcbuf);
  2417. if (status) {
  2418. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2419. "Mapping failure Error:%d", status);
  2420. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2421. goto fail_map;
  2422. }
  2423. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2424. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2425. seg_info_new->frags[0].paddr_hi =
  2426. ((uint64_t) paddr_mcbuf >> 32);
  2427. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2428. seg_info_new->frags[1] = data_frag;
  2429. seg_info_new->nbuf = nbuf_clone;
  2430. seg_info_new->frag_cnt = 2;
  2431. seg_info_new->total_len = len;
  2432. seg_info_new->next = NULL;
  2433. if (seg_info_head == NULL)
  2434. seg_info_head = seg_info_new;
  2435. else
  2436. seg_info_tail->next = seg_info_new;
  2437. seg_info_tail = seg_info_new;
  2438. }
  2439. if (!seg_info_head)
  2440. return 0;
  2441. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2442. msdu_info.num_seg = new_mac_cnt;
  2443. msdu_info.frm_type = dp_tx_frm_me;
  2444. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2445. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2446. while (seg_info_head->next) {
  2447. seg_info_new = seg_info_head;
  2448. seg_info_head = seg_info_head->next;
  2449. qdf_mem_free(seg_info_new);
  2450. }
  2451. qdf_mem_free(seg_info_head);
  2452. return new_mac_cnt;
  2453. fail_map:
  2454. qdf_nbuf_free(nbuf_clone);
  2455. fail_clone:
  2456. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2457. fail_buf_alloc:
  2458. qdf_mem_free(seg_info_new);
  2459. fail_seg_alloc:
  2460. dp_tx_me_mem_free(pdev, seg_info_head);
  2461. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2462. return 0;
  2463. }