hal_rx.h 115 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_RX_H_
  19. #define _HAL_RX_H_
  20. #include <hal_api.h>
  21. #define HAL_INVALID_PPDU_ID 0xFFFFFFFF
  22. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  23. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  24. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  25. #define HAL_RX_GET(_ptr, block, field) \
  26. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  27. HAL_RX_MASk(block, field)) >> \
  28. HAL_RX_LSB(block, field))
  29. /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */
  30. #ifndef RX_DATA_BUFFER_SIZE
  31. #define RX_DATA_BUFFER_SIZE 2048
  32. #endif
  33. #ifndef RX_MONITOR_BUFFER_SIZE
  34. #define RX_MONITOR_BUFFER_SIZE 2048
  35. #endif
  36. /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes
  37. * including buffer reservation, buffer alignment and skb shared info size.
  38. */
  39. #define RX_MON_STATUS_BASE_BUF_SIZE 2048
  40. #define RX_MON_STATUS_BUF_ALIGN 128
  41. #define RX_MON_STATUS_BUF_RESERVATION 128
  42. #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \
  43. (RX_MON_STATUS_BUF_RESERVATION + \
  44. RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE))
  45. /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */
  46. #define HAL_RX_NON_QOS_TID 16
  47. enum {
  48. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  49. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  50. HAL_HW_RX_DECAP_FORMAT_ETH2,
  51. HAL_HW_RX_DECAP_FORMAT_8023,
  52. };
  53. /**
  54. * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons
  55. *
  56. * @reo_psh_rsn: REO push reason
  57. * @reo_err_code: REO Error code
  58. * @rxdma_psh_rsn: RXDMA push reason
  59. * @rxdma_err_code: RXDMA Error code
  60. * @reserved_1: Reserved bits
  61. * @wbm_err_src: WBM error source
  62. * @pool_id: pool ID, indicates which rxdma pool
  63. * @reserved_2: Reserved bits
  64. */
  65. struct hal_wbm_err_desc_info {
  66. uint16_t reo_psh_rsn:2,
  67. reo_err_code:5,
  68. rxdma_psh_rsn:2,
  69. rxdma_err_code:5,
  70. reserved_1:2;
  71. uint8_t wbm_err_src:3,
  72. pool_id:2,
  73. msdu_continued:1,
  74. reserved_2:2;
  75. };
  76. /**
  77. * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info
  78. * @first_buffer: First buffer of MSDU
  79. * @last_buffer: Last buffer of MSDU
  80. * @is_decap_raw: Is RAW Frame
  81. * @reserved_1: Reserved
  82. *
  83. * MSDU with continuation:
  84. * -----------------------------------------------------------
  85. * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 |
  86. * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 |
  87. * | is_decap_raw:1/0 | Same as earlier | Same as earlier|
  88. * -----------------------------------------------------------
  89. *
  90. * Single buffer MSDU:
  91. * ------------------
  92. * | first_buffer:1 |
  93. * | last_buffer :1 |
  94. * | is_decap_raw:1/0 |
  95. * ------------------
  96. */
  97. struct hal_rx_mon_dest_buf_info {
  98. uint8_t first_buffer:1,
  99. last_buffer:1,
  100. is_decap_raw:1,
  101. reserved_1:5;
  102. };
  103. /**
  104. * struct hal_rx_msdu_metadata:Structure to hold rx fast path information.
  105. *
  106. * @l3_hdr_pad: l3 header padding
  107. * @reserved: Reserved bits
  108. * @sa_sw_peer_id: sa sw peer id
  109. * @sa_idx: sa index
  110. * @da_idx: da index
  111. */
  112. struct hal_rx_msdu_metadata {
  113. uint32_t l3_hdr_pad:16,
  114. sa_sw_peer_id:16;
  115. uint32_t sa_idx:16,
  116. da_idx:16;
  117. };
  118. /**
  119. * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason"
  120. *
  121. * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected
  122. * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing
  123. */
  124. enum hal_reo_error_status {
  125. HAL_REO_ERROR_DETECTED = 0,
  126. HAL_REO_ROUTING_INSTRUCTION = 1,
  127. };
  128. /**
  129. * @msdu_flags: [0] first_msdu_in_mpdu
  130. * [1] last_msdu_in_mpdu
  131. * [2] msdu_continuation - MSDU spread across buffers
  132. * [23] sa_is_valid - SA match in peer table
  133. * [24] sa_idx_timeout - Timeout while searching for SA match
  134. * [25] da_is_valid - Used to identtify intra-bss forwarding
  135. * [26] da_is_MCBC
  136. * [27] da_idx_timeout - Timeout while searching for DA match
  137. *
  138. */
  139. struct hal_rx_msdu_desc_info {
  140. uint32_t msdu_flags;
  141. uint16_t msdu_len; /* 14 bits for length */
  142. };
  143. /**
  144. * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO
  145. *
  146. * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU
  147. * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU
  148. * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation
  149. * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST
  150. * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out
  151. * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST
  152. * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address
  153. * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out
  154. */
  155. enum hal_rx_msdu_desc_flags {
  156. HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0),
  157. HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1),
  158. HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2),
  159. HAL_MSDU_F_SA_IS_VALID = (0x1 << 23),
  160. HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24),
  161. HAL_MSDU_F_DA_IS_VALID = (0x1 << 25),
  162. HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26),
  163. HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27)
  164. };
  165. /*
  166. * @msdu_count: no. of msdus in the MPDU
  167. * @mpdu_seq: MPDU sequence number
  168. * @mpdu_flags [0] Fragment flag
  169. * [1] MPDU_retry_bit
  170. * [2] AMPDU flag
  171. * [3] raw_ampdu
  172. * @peer_meta_data: Upper bits containing peer id, vdev id
  173. * @bar_frame: indicates if received frame is a bar frame
  174. */
  175. struct hal_rx_mpdu_desc_info {
  176. uint16_t msdu_count;
  177. uint16_t mpdu_seq; /* 12 bits for length */
  178. uint32_t mpdu_flags;
  179. uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */
  180. uint16_t bar_frame;
  181. };
  182. /**
  183. * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO
  184. *
  185. * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation)
  186. * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU
  187. * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU
  188. * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU
  189. */
  190. enum hal_rx_mpdu_desc_flags {
  191. HAL_MPDU_F_FRAGMENT = (0x1 << 20),
  192. HAL_MPDU_F_RETRY_BIT = (0x1 << 21),
  193. HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22),
  194. HAL_MPDU_F_RAW_AMPDU = (0x1 << 30)
  195. };
  196. /**
  197. * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in
  198. * BUFFER_ADDR_INFO structure
  199. *
  200. * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
  201. * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
  202. * descriptor list
  203. * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
  204. * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
  205. * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
  206. * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
  207. * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
  208. */
  209. enum hal_rx_ret_buf_manager {
  210. HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0,
  211. HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1,
  212. HAL_RX_BUF_RBM_FW_BM = 2,
  213. HAL_RX_BUF_RBM_SW0_BM = 3,
  214. HAL_RX_BUF_RBM_SW1_BM = 4,
  215. HAL_RX_BUF_RBM_SW2_BM = 5,
  216. HAL_RX_BUF_RBM_SW3_BM = 6,
  217. };
  218. /*
  219. * Given the offset of a field in bytes, returns uint8_t *
  220. */
  221. #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
  222. (((uint8_t *)(_ptr)) + (_off_in_bytes))
  223. /*
  224. * Given the offset of a field in bytes, returns uint32_t *
  225. */
  226. #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
  227. (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
  228. #define _HAL_MS(_word, _mask, _shift) \
  229. (((_word) & (_mask)) >> (_shift))
  230. /*
  231. * macro to set the LSW of the nbuf data physical address
  232. * to the rxdma ring entry
  233. */
  234. #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \
  235. ((*(((unsigned int *) buff_addr_info) + \
  236. (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
  237. (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
  238. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
  239. /*
  240. * macro to set the LSB of MSW of the nbuf data physical address
  241. * to the rxdma ring entry
  242. */
  243. #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \
  244. ((*(((unsigned int *) buff_addr_info) + \
  245. (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
  246. (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
  247. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
  248. #define HAL_RX_COOKIE_INVALID_MASK 0x80000000
  249. /*
  250. * macro to get the invalid bit for sw cookie
  251. */
  252. #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \
  253. ((*(((unsigned int *)buff_addr_info) + \
  254. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  255. HAL_RX_COOKIE_INVALID_MASK)
  256. /*
  257. * macro to set the invalid bit for sw cookie
  258. */
  259. #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \
  260. ((*(((unsigned int *)buff_addr_info) + \
  261. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  262. HAL_RX_COOKIE_INVALID_MASK)
  263. /*
  264. * macro to set the cookie into the rxdma ring entry
  265. */
  266. #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
  267. ((*(((unsigned int *) buff_addr_info) + \
  268. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  269. ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \
  270. ((*(((unsigned int *) buff_addr_info) + \
  271. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  272. (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
  273. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
  274. /*
  275. * macro to set the manager into the rxdma ring entry
  276. */
  277. #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
  278. ((*(((unsigned int *) buff_addr_info) + \
  279. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
  280. ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \
  281. ((*(((unsigned int *) buff_addr_info) + \
  282. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
  283. (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
  284. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)
  285. #define HAL_RX_ERROR_STATUS_GET(reo_desc) \
  286. (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \
  287. REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\
  288. REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \
  289. REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB))
  290. #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \
  291. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  292. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \
  293. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \
  294. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB))
  295. #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \
  296. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  297. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \
  298. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \
  299. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB))
  300. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  301. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  302. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  303. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  304. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  305. #define HAL_RX_BUF_RBM_GET(buff_addr_info) \
  306. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  307. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\
  308. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \
  309. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB))
  310. #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000
  311. #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \
  312. ((*(((unsigned int *)buff_addr_info) + \
  313. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  314. HAL_RX_LINK_COOKIE_INVALID_MASK)
  315. #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \
  316. ((*(((unsigned int *)buff_addr_info) + \
  317. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  318. HAL_RX_LINK_COOKIE_INVALID_MASK)
  319. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \
  320. (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \
  321. (((struct reo_destination_ring *) \
  322. reo_desc)->buf_or_link_desc_addr_info)))
  323. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \
  324. (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \
  325. (((struct reo_destination_ring *) \
  326. reo_desc)->buf_or_link_desc_addr_info)))
  327. /* TODO: Convert the following structure fields accesseses to offsets */
  328. #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \
  329. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  330. (((struct reo_destination_ring *) \
  331. reo_desc)->buf_or_link_desc_addr_info)))
  332. #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \
  333. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  334. (((struct reo_destination_ring *) \
  335. reo_desc)->buf_or_link_desc_addr_info)))
  336. #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \
  337. (HAL_RX_BUF_COOKIE_INVALID_GET(& \
  338. (((struct reo_destination_ring *) \
  339. reo_desc)->buf_or_link_desc_addr_info)))
  340. #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \
  341. (HAL_RX_BUF_COOKIE_INVALID_SET(& \
  342. (((struct reo_destination_ring *) \
  343. reo_desc)->buf_or_link_desc_addr_info)))
  344. #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \
  345. (HAL_RX_BUF_COOKIE_GET(& \
  346. (((struct reo_destination_ring *) \
  347. reo_desc)->buf_or_link_desc_addr_info)))
  348. #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \
  349. ((mpdu_info_ptr \
  350. [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \
  351. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \
  352. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB)
  353. #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \
  354. ((mpdu_info_ptr \
  355. [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \
  356. RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \
  357. RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB)
  358. #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \
  359. ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \
  360. RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \
  361. RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB)
  362. #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \
  363. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \
  364. RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK)
  365. #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \
  366. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \
  367. RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK)
  368. #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \
  369. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \
  370. RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK)
  371. #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \
  372. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \
  373. RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK)
  374. #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \
  375. (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \
  376. HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \
  377. HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \
  378. HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr))
  379. #define HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info_ptr) \
  380. ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET >> 2] & \
  381. RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK) >> \
  382. RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB)
  383. #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \
  384. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  385. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \
  386. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \
  387. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB))
  388. /*
  389. * NOTE: None of the following _GET macros need a right
  390. * shift by the corresponding _LSB. This is because, they are
  391. * finally taken and "OR'ed" into a single word again.
  392. */
  393. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  394. ((*(((uint32_t *)msdu_info_ptr) + \
  395. (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \
  396. (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \
  397. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  398. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  399. ((*(((uint32_t *)msdu_info_ptr) + \
  400. (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \
  401. (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \
  402. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK)
  403. #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \
  404. ((*(((uint32_t *)msdu_info_ptr) + \
  405. (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \
  406. (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \
  407. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  408. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  409. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  410. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  411. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  412. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  413. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  414. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  415. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK)
  416. #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \
  417. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  418. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \
  419. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  420. #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \
  421. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  422. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \
  423. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \
  424. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB))
  425. #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  426. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  427. RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \
  428. RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK)
  429. #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  430. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  431. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \
  432. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK)
  433. #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  434. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  435. RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \
  436. RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK)
  437. #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \
  438. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  439. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \
  440. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK)
  441. #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  442. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  443. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \
  444. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK)
  445. #define HAL_RX_REO_MSDU_REO_DST_IND_GET(reo_desc) \
  446. (HAL_RX_MSDU_REO_DST_IND_GET(& \
  447. (((struct reo_destination_ring *) \
  448. reo_desc)->rx_msdu_desc_info_details)))
  449. #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \
  450. (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  451. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  452. HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \
  453. HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  454. HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \
  455. HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  456. HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
  457. HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
  458. #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \
  459. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  460. RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \
  461. RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \
  462. RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB))
  463. #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \
  464. (*(uint32_t *)(((uint8_t *)_ptr) + \
  465. _wrd ## _ ## _field ## _OFFSET) |= \
  466. ((_val << _wrd ## _ ## _field ## _LSB) & \
  467. _wrd ## _ ## _field ## _MASK))
  468. #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \
  469. HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \
  470. _field, _val)
  471. #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \
  472. HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \
  473. _field, _val)
  474. #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \
  475. HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \
  476. _field, _val)
  477. static inline void hal_rx_mpdu_desc_info_get(void *desc_addr,
  478. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  479. {
  480. struct reo_destination_ring *reo_dst_ring;
  481. uint32_t *mpdu_info;
  482. reo_dst_ring = (struct reo_destination_ring *) desc_addr;
  483. mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details;
  484. mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
  485. mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info);
  486. mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info);
  487. mpdu_desc_info->peer_meta_data =
  488. HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info);
  489. mpdu_desc_info->bar_frame = HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info);
  490. }
  491. /*
  492. * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor.
  493. * @ Specifically flags needed are:
  494. * @ first_msdu_in_mpdu, last_msdu_in_mpdu,
  495. * @ msdu_continuation, sa_is_valid,
  496. * @ sa_idx_timeout, da_is_valid, da_idx_timeout,
  497. * @ da_is_MCBC
  498. *
  499. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current
  500. * @ descriptor
  501. * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor
  502. * @ Return: void
  503. */
  504. static inline void hal_rx_msdu_desc_info_get(void *desc_addr,
  505. struct hal_rx_msdu_desc_info *msdu_desc_info)
  506. {
  507. struct reo_destination_ring *reo_dst_ring;
  508. uint32_t *msdu_info;
  509. reo_dst_ring = (struct reo_destination_ring *) desc_addr;
  510. msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details;
  511. msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info);
  512. msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info);
  513. }
  514. /*
  515. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  516. * rxdma ring entry.
  517. * @rxdma_entry: descriptor entry
  518. * @paddr: physical address of nbuf data pointer.
  519. * @cookie: SW cookie used as a index to SW rx desc.
  520. * @manager: who owns the nbuf (host, NSS, etc...).
  521. *
  522. */
  523. static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry,
  524. qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager)
  525. {
  526. uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
  527. uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
  528. HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
  529. HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
  530. HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
  531. HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
  532. }
  533. /*
  534. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  535. * pre-header.
  536. */
  537. /*
  538. * Every Rx packet starts at an offset from the top of the buffer.
  539. * If the host hasn't subscribed to any specific TLV, there is
  540. * still space reserved for the following TLV's from the start of
  541. * the buffer:
  542. * -- RX ATTENTION
  543. * -- RX MPDU START
  544. * -- RX MSDU START
  545. * -- RX MSDU END
  546. * -- RX MPDU END
  547. * -- RX PACKET HEADER (802.11)
  548. * If the host subscribes to any of the TLV's above, that TLV
  549. * if populated by the HW
  550. */
  551. #define NUM_DWORDS_TAG 1
  552. /* By default the packet header TLV is 128 bytes */
  553. #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128
  554. #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \
  555. (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2)
  556. #define RX_PKT_OFFSET_WORDS \
  557. ( \
  558. NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \
  559. NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \
  560. NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \
  561. NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \
  562. NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \
  563. NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \
  564. )
  565. #define RX_PKT_OFFSET_BYTES \
  566. (RX_PKT_OFFSET_WORDS << 2)
  567. #define RX_PKT_HDR_TLV_LEN 120
  568. /*
  569. * Each RX descriptor TLV is preceded by 1 DWORD "tag"
  570. */
  571. struct rx_attention_tlv {
  572. uint32_t tag;
  573. struct rx_attention rx_attn;
  574. };
  575. struct rx_mpdu_start_tlv {
  576. uint32_t tag;
  577. struct rx_mpdu_start rx_mpdu_start;
  578. };
  579. struct rx_msdu_start_tlv {
  580. uint32_t tag;
  581. struct rx_msdu_start rx_msdu_start;
  582. };
  583. struct rx_msdu_end_tlv {
  584. uint32_t tag;
  585. struct rx_msdu_end rx_msdu_end;
  586. };
  587. struct rx_mpdu_end_tlv {
  588. uint32_t tag;
  589. struct rx_mpdu_end rx_mpdu_end;
  590. };
  591. struct rx_pkt_hdr_tlv {
  592. uint32_t tag; /* 4 B */
  593. uint32_t phy_ppdu_id; /* 4 B */
  594. char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */
  595. };
  596. #define RXDMA_OPTIMIZATION
  597. /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status
  598. * buffers, monitor destination buffers and monitor descriptor buffers.
  599. */
  600. #ifdef RXDMA_OPTIMIZATION
  601. /*
  602. * The RX_PADDING_BYTES is required so that the TLV's don't
  603. * spread across the 128 byte boundary
  604. * RXDMA optimization requires:
  605. * 1) MSDU_END & ATTENTION TLV's follow in that order
  606. * 2) TLV's don't span across 128 byte lines
  607. * 3) Rx Buffer is nicely aligned on the 128 byte boundary
  608. */
  609. #define RX_PADDING0_BYTES 4
  610. #define RX_PADDING1_BYTES 16
  611. struct rx_pkt_tlvs {
  612. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  613. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  614. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  615. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  616. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  617. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  618. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  619. #ifndef NO_RX_PKT_HDR_TLV
  620. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  621. #endif
  622. };
  623. #else /* RXDMA_OPTIMIZATION */
  624. struct rx_pkt_tlvs {
  625. struct rx_attention_tlv attn_tlv;
  626. struct rx_mpdu_start_tlv mpdu_start_tlv;
  627. struct rx_msdu_start_tlv msdu_start_tlv;
  628. struct rx_msdu_end_tlv msdu_end_tlv;
  629. struct rx_mpdu_end_tlv mpdu_end_tlv;
  630. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  631. };
  632. #endif /* RXDMA_OPTIMIZATION */
  633. /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */
  634. #ifdef RXDMA_OPTIMIZATION
  635. struct rx_mon_pkt_tlvs {
  636. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  637. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  638. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  639. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  640. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  641. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  642. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  643. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  644. };
  645. #else /* RXDMA_OPTIMIZATION */
  646. struct rx_mon_pkt_tlvs {
  647. struct rx_attention_tlv attn_tlv;
  648. struct rx_mpdu_start_tlv mpdu_start_tlv;
  649. struct rx_msdu_start_tlv msdu_start_tlv;
  650. struct rx_msdu_end_tlv msdu_end_tlv;
  651. struct rx_mpdu_end_tlv mpdu_end_tlv;
  652. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  653. };
  654. #endif
  655. #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs)
  656. #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs)
  657. #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV
  658. #ifdef NO_RX_PKT_HDR_TLV
  659. static inline uint8_t
  660. *hal_rx_pkt_hdr_get(uint8_t *buf)
  661. {
  662. return buf + RX_PKT_TLVS_LEN;
  663. }
  664. #else
  665. static inline uint8_t
  666. *hal_rx_pkt_hdr_get(uint8_t *buf)
  667. {
  668. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  669. return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr;
  670. }
  671. #endif
  672. #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field)
  673. #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \
  674. RX_PKT_TLV_OFFSET(mpdu_start_tlv)
  675. #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv)
  676. #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \
  677. RX_PKT_TLV_OFFSET(msdu_start_tlv)
  678. #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv)
  679. #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv)
  680. #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv)
  681. static inline uint8_t
  682. *hal_rx_padding0_get(uint8_t *buf)
  683. {
  684. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  685. return pkt_tlvs->rx_padding0;
  686. }
  687. /*
  688. * hal_rx_encryption_info_valid(): Returns encryption type.
  689. *
  690. * @hal_soc_hdl: hal soc handle
  691. * @buf: rx_tlv_hdr of the received packet
  692. *
  693. * Return: encryption type
  694. */
  695. static inline uint32_t
  696. hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  697. {
  698. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  699. return hal_soc->ops->hal_rx_encryption_info_valid(buf);
  700. }
  701. /*
  702. * hal_rx_print_pn: Prints the PN of rx packet.
  703. * @hal_soc_hdl: hal soc handle
  704. * @buf: rx_tlv_hdr of the received packet
  705. *
  706. * Return: void
  707. */
  708. static inline void
  709. hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  710. {
  711. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  712. hal_soc->ops->hal_rx_print_pn(buf);
  713. }
  714. /*
  715. * Get msdu_done bit from the RX_ATTENTION TLV
  716. */
  717. #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \
  718. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  719. RX_ATTENTION_2_MSDU_DONE_OFFSET)), \
  720. RX_ATTENTION_2_MSDU_DONE_MASK, \
  721. RX_ATTENTION_2_MSDU_DONE_LSB))
  722. static inline uint32_t
  723. hal_rx_attn_msdu_done_get(uint8_t *buf)
  724. {
  725. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  726. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  727. uint32_t msdu_done;
  728. msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn);
  729. return msdu_done;
  730. }
  731. #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \
  732. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  733. RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \
  734. RX_ATTENTION_1_FIRST_MPDU_MASK, \
  735. RX_ATTENTION_1_FIRST_MPDU_LSB))
  736. /*
  737. * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention
  738. * @buf: pointer to rx_pkt_tlvs
  739. *
  740. * reutm: uint32_t(first_msdu)
  741. */
  742. static inline uint32_t
  743. hal_rx_attn_first_mpdu_get(uint8_t *buf)
  744. {
  745. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  746. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  747. uint32_t first_mpdu;
  748. first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
  749. return first_mpdu;
  750. }
  751. #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \
  752. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  753. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \
  754. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \
  755. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB))
  756. /*
  757. * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit
  758. * from rx attention
  759. * @buf: pointer to rx_pkt_tlvs
  760. *
  761. * Return: tcp_udp_cksum_fail
  762. */
  763. static inline bool
  764. hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf)
  765. {
  766. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  767. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  768. bool tcp_udp_cksum_fail;
  769. tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn);
  770. return tcp_udp_cksum_fail;
  771. }
  772. #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \
  773. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  774. RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \
  775. RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \
  776. RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB))
  777. /*
  778. * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit
  779. * from rx attention
  780. * @buf: pointer to rx_pkt_tlvs
  781. *
  782. * Return: ip_cksum_fail
  783. */
  784. static inline bool
  785. hal_rx_attn_ip_cksum_fail_get(uint8_t *buf)
  786. {
  787. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  788. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  789. bool ip_cksum_fail;
  790. ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn);
  791. return ip_cksum_fail;
  792. }
  793. #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \
  794. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  795. RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \
  796. RX_ATTENTION_0_PHY_PPDU_ID_MASK, \
  797. RX_ATTENTION_0_PHY_PPDU_ID_LSB))
  798. /*
  799. * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
  800. * from rx attention
  801. * @buf: pointer to rx_pkt_tlvs
  802. *
  803. * Return: phy_ppdu_id
  804. */
  805. static inline uint16_t
  806. hal_rx_attn_phy_ppdu_id_get(uint8_t *buf)
  807. {
  808. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  809. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  810. uint16_t phy_ppdu_id;
  811. phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn);
  812. return phy_ppdu_id;
  813. }
  814. #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \
  815. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  816. RX_ATTENTION_1_CCE_MATCH_OFFSET)), \
  817. RX_ATTENTION_1_CCE_MATCH_MASK, \
  818. RX_ATTENTION_1_CCE_MATCH_LSB))
  819. /*
  820. * hal_rx_msdu_cce_match_get(): get CCE match bit
  821. * from rx attention
  822. * @buf: pointer to rx_pkt_tlvs
  823. * Return: CCE match value
  824. */
  825. static inline bool
  826. hal_rx_msdu_cce_match_get(uint8_t *buf)
  827. {
  828. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  829. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  830. bool cce_match_val;
  831. cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn);
  832. return cce_match_val;
  833. }
  834. /*
  835. * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
  836. */
  837. #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \
  838. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  839. RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \
  840. RX_MPDU_INFO_8_PEER_META_DATA_MASK, \
  841. RX_MPDU_INFO_8_PEER_META_DATA_LSB))
  842. static inline uint32_t
  843. hal_rx_mpdu_peer_meta_data_get(uint8_t *buf)
  844. {
  845. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  846. struct rx_mpdu_start *mpdu_start =
  847. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  848. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  849. uint32_t peer_meta_data;
  850. peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info);
  851. return peer_meta_data;
  852. }
  853. #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \
  854. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  855. RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \
  856. RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \
  857. RX_MPDU_INFO_12_AMPDU_FLAG_LSB))
  858. /**
  859. * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit
  860. * from rx mpdu info
  861. * @buf: pointer to rx_pkt_tlvs
  862. *
  863. * Return: ampdu flag
  864. */
  865. static inline bool
  866. hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf)
  867. {
  868. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  869. struct rx_mpdu_start *mpdu_start =
  870. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  871. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  872. bool ampdu_flag;
  873. ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info);
  874. return ampdu_flag;
  875. }
  876. #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \
  877. ((*(((uint32_t *)_rx_mpdu_info) + \
  878. (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \
  879. (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \
  880. RX_MPDU_INFO_8_PEER_META_DATA_MASK)
  881. /*
  882. * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv
  883. *
  884. * @ buf: rx_tlv_hdr of the received packet
  885. * @ peer_mdata: peer meta data to be set.
  886. * @ Return: void
  887. */
  888. static inline void
  889. hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata)
  890. {
  891. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  892. struct rx_mpdu_start *mpdu_start =
  893. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  894. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  895. HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata);
  896. }
  897. /**
  898. * LRO information needed from the TLVs
  899. */
  900. #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \
  901. (_HAL_MS( \
  902. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  903. msdu_end_tlv.rx_msdu_end), \
  904. RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \
  905. RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \
  906. RX_MSDU_END_9_LRO_ELIGIBLE_LSB))
  907. #define HAL_RX_TLV_GET_TCP_ACK(buf) \
  908. (_HAL_MS( \
  909. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  910. msdu_end_tlv.rx_msdu_end), \
  911. RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \
  912. RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \
  913. RX_MSDU_END_8_TCP_ACK_NUMBER_LSB))
  914. #define HAL_RX_TLV_GET_TCP_SEQ(buf) \
  915. (_HAL_MS( \
  916. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  917. msdu_end_tlv.rx_msdu_end), \
  918. RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \
  919. RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \
  920. RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB))
  921. #define HAL_RX_TLV_GET_TCP_WIN(buf) \
  922. (_HAL_MS( \
  923. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  924. msdu_end_tlv.rx_msdu_end), \
  925. RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \
  926. RX_MSDU_END_9_WINDOW_SIZE_MASK, \
  927. RX_MSDU_END_9_WINDOW_SIZE_LSB))
  928. #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \
  929. (_HAL_MS( \
  930. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  931. msdu_start_tlv.rx_msdu_start), \
  932. RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \
  933. RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \
  934. RX_MSDU_START_2_TCP_ONLY_ACK_LSB))
  935. #define HAL_RX_TLV_GET_TCP_PROTO(buf) \
  936. (_HAL_MS( \
  937. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  938. msdu_start_tlv.rx_msdu_start), \
  939. RX_MSDU_START_2_TCP_PROTO_OFFSET)), \
  940. RX_MSDU_START_2_TCP_PROTO_MASK, \
  941. RX_MSDU_START_2_TCP_PROTO_LSB))
  942. #define HAL_RX_TLV_GET_UDP_PROTO(buf) \
  943. (_HAL_MS( \
  944. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  945. msdu_start_tlv.rx_msdu_start), \
  946. RX_MSDU_START_2_UDP_PROTO_OFFSET)), \
  947. RX_MSDU_START_2_UDP_PROTO_MASK, \
  948. RX_MSDU_START_2_UDP_PROTO_LSB))
  949. #define HAL_RX_TLV_GET_IPV6(buf) \
  950. (_HAL_MS( \
  951. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  952. msdu_start_tlv.rx_msdu_start), \
  953. RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \
  954. RX_MSDU_START_2_IPV6_PROTO_MASK, \
  955. RX_MSDU_START_2_IPV6_PROTO_LSB))
  956. #define HAL_RX_TLV_GET_IP_OFFSET(buf) \
  957. (_HAL_MS( \
  958. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  959. msdu_start_tlv.rx_msdu_start), \
  960. RX_MSDU_START_1_L3_OFFSET_OFFSET)), \
  961. RX_MSDU_START_1_L3_OFFSET_MASK, \
  962. RX_MSDU_START_1_L3_OFFSET_LSB))
  963. #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \
  964. (_HAL_MS( \
  965. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  966. msdu_start_tlv.rx_msdu_start), \
  967. RX_MSDU_START_1_L4_OFFSET_OFFSET)), \
  968. RX_MSDU_START_1_L4_OFFSET_MASK, \
  969. RX_MSDU_START_1_L4_OFFSET_LSB))
  970. #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \
  971. (_HAL_MS( \
  972. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  973. msdu_start_tlv.rx_msdu_start), \
  974. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  975. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  976. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  977. /**
  978. * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the
  979. * l3_header padding from rx_msdu_end TLV
  980. *
  981. * @buf: pointer to the start of RX PKT TLV headers
  982. * Return: number of l3 header padding bytes
  983. */
  984. static inline uint32_t
  985. hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl,
  986. uint8_t *buf)
  987. {
  988. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  989. return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf);
  990. }
  991. /**
  992. * hal_rx_msdu_end_sa_idx_get(): API to get the
  993. * sa_idx from rx_msdu_end TLV
  994. *
  995. * @ buf: pointer to the start of RX PKT TLV headers
  996. * Return: sa_idx (SA AST index)
  997. */
  998. static inline uint16_t
  999. hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl,
  1000. uint8_t *buf)
  1001. {
  1002. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1003. return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf);
  1004. }
  1005. /**
  1006. * hal_rx_msdu_end_sa_is_valid_get(): API to get the
  1007. * sa_is_valid bit from rx_msdu_end TLV
  1008. *
  1009. * @ buf: pointer to the start of RX PKT TLV headers
  1010. * Return: sa_is_valid bit
  1011. */
  1012. static inline uint8_t
  1013. hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  1014. uint8_t *buf)
  1015. {
  1016. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1017. return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf);
  1018. }
  1019. #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \
  1020. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1021. RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \
  1022. RX_MSDU_START_1_MSDU_LENGTH_MASK, \
  1023. RX_MSDU_START_1_MSDU_LENGTH_LSB))
  1024. /**
  1025. * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length
  1026. * from rx_msdu_start TLV
  1027. *
  1028. * @ buf: pointer to the start of RX PKT TLV headers
  1029. * Return: msdu length
  1030. */
  1031. static inline uint32_t
  1032. hal_rx_msdu_start_msdu_len_get(uint8_t *buf)
  1033. {
  1034. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1035. struct rx_msdu_start *msdu_start =
  1036. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1037. uint32_t msdu_len;
  1038. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  1039. return msdu_len;
  1040. }
  1041. /**
  1042. * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length
  1043. * from rx_msdu_start TLV
  1044. *
  1045. * @buf: pointer to the start of RX PKT TLV headers
  1046. * @len: msdu length
  1047. *
  1048. * Return: none
  1049. */
  1050. static inline void
  1051. hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len)
  1052. {
  1053. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1054. struct rx_msdu_start *msdu_start =
  1055. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1056. void *wrd1;
  1057. wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET;
  1058. *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK);
  1059. *(uint32_t *)wrd1 |= len;
  1060. }
  1061. #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \
  1062. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  1063. RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \
  1064. RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \
  1065. RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB))
  1066. /*
  1067. * hal_rx_msdu_start_bw_get(): API to get the Bandwidth
  1068. * Interval from rx_msdu_start
  1069. *
  1070. * @buf: pointer to the start of RX PKT TLV header
  1071. * Return: uint32_t(bw)
  1072. */
  1073. static inline uint32_t
  1074. hal_rx_msdu_start_bw_get(uint8_t *buf)
  1075. {
  1076. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1077. struct rx_msdu_start *msdu_start =
  1078. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1079. uint32_t bw;
  1080. bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
  1081. return bw;
  1082. }
  1083. #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \
  1084. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1085. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  1086. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  1087. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  1088. /**
  1089. * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash
  1090. * from rx_msdu_start TLV
  1091. *
  1092. * @ buf: pointer to the start of RX PKT TLV headers
  1093. * Return: toeplitz hash
  1094. */
  1095. static inline uint32_t
  1096. hal_rx_msdu_start_toeplitz_get(uint8_t *buf)
  1097. {
  1098. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1099. struct rx_msdu_start *msdu_start =
  1100. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1101. return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start);
  1102. }
  1103. /**
  1104. * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO
  1105. *
  1106. * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame
  1107. * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame
  1108. * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame
  1109. * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame
  1110. * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame
  1111. * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame
  1112. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame
  1113. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame
  1114. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame
  1115. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame
  1116. * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported
  1117. * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit
  1118. */
  1119. enum hal_rx_mpdu_info_sw_frame_group_id_type {
  1120. HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0,
  1121. HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA,
  1122. HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA,
  1123. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA,
  1124. HAL_MPDU_SW_FRAME_GROUP_MGMT,
  1125. HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8,
  1126. HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12,
  1127. HAL_MPDU_SW_FRAME_GROUP_CTRL = 20,
  1128. HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25,
  1129. HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28,
  1130. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31,
  1131. HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36,
  1132. HAL_MPDU_SW_FRAME_GROUP_MAX = 37,
  1133. };
  1134. /**
  1135. * hal_rx_mpdu_start_mpdu_qos_control_valid_get():
  1136. * Retrieve qos control valid bit from the tlv.
  1137. * @hal_soc_hdl: hal_soc handle
  1138. * @buf: pointer to rx pkt TLV.
  1139. *
  1140. * Return: qos control value.
  1141. */
  1142. static inline uint32_t
  1143. hal_rx_mpdu_start_mpdu_qos_control_valid_get(
  1144. hal_soc_handle_t hal_soc_hdl,
  1145. uint8_t *buf)
  1146. {
  1147. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1148. if ((!hal_soc) || (!hal_soc->ops)) {
  1149. hal_err("hal handle is NULL");
  1150. QDF_BUG(0);
  1151. return QDF_STATUS_E_INVAL;
  1152. }
  1153. if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get)
  1154. return hal_soc->ops->
  1155. hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf);
  1156. return QDF_STATUS_E_INVAL;
  1157. }
  1158. /**
  1159. * hal_rx_is_unicast: check packet is unicast frame or not.
  1160. * @hal_soc_hdl: hal_soc handle
  1161. * @buf: pointer to rx pkt TLV.
  1162. *
  1163. * Return: true on unicast.
  1164. */
  1165. static inline bool
  1166. hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1167. {
  1168. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1169. return hal_soc->ops->hal_rx_is_unicast(buf);
  1170. }
  1171. /**
  1172. * hal_rx_tid_get: get tid based on qos control valid.
  1173. * @hal_soc_hdl: hal soc handle
  1174. * @buf: pointer to rx pkt TLV.
  1175. *
  1176. * Return: tid
  1177. */
  1178. static inline uint32_t
  1179. hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1180. {
  1181. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1182. return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf);
  1183. }
  1184. /**
  1185. * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id
  1186. * @hal_soc_hdl: hal soc handle
  1187. * @buf: pointer to rx pkt TLV.
  1188. *
  1189. * Return: sw peer_id
  1190. */
  1191. static inline uint32_t
  1192. hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  1193. uint8_t *buf)
  1194. {
  1195. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1196. return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf);
  1197. }
  1198. #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
  1199. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  1200. RX_MSDU_START_5_SGI_OFFSET)), \
  1201. RX_MSDU_START_5_SGI_MASK, \
  1202. RX_MSDU_START_5_SGI_LSB))
  1203. /**
  1204. * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd
  1205. * Interval from rx_msdu_start TLV
  1206. *
  1207. * @buf: pointer to the start of RX PKT TLV headers
  1208. * Return: uint32_t(sgi)
  1209. */
  1210. static inline uint32_t
  1211. hal_rx_msdu_start_sgi_get(uint8_t *buf)
  1212. {
  1213. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1214. struct rx_msdu_start *msdu_start =
  1215. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1216. uint32_t sgi;
  1217. sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
  1218. return sgi;
  1219. }
  1220. #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
  1221. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  1222. RX_MSDU_START_5_RATE_MCS_OFFSET)), \
  1223. RX_MSDU_START_5_RATE_MCS_MASK, \
  1224. RX_MSDU_START_5_RATE_MCS_LSB))
  1225. /**
  1226. * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate
  1227. * from rx_msdu_start TLV
  1228. *
  1229. * @buf: pointer to the start of RX PKT TLV headers
  1230. * Return: uint32_t(rate_mcs)
  1231. */
  1232. static inline uint32_t
  1233. hal_rx_msdu_start_rate_mcs_get(uint8_t *buf)
  1234. {
  1235. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1236. struct rx_msdu_start *msdu_start =
  1237. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1238. uint32_t rate_mcs;
  1239. rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
  1240. return rate_mcs;
  1241. }
  1242. #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
  1243. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  1244. RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \
  1245. RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
  1246. RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
  1247. /*
  1248. * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the
  1249. * packet from rx_attention
  1250. *
  1251. * @buf: pointer to the start of RX PKT TLV header
  1252. * Return: uint32_t(decryt status)
  1253. */
  1254. static inline uint32_t
  1255. hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf)
  1256. {
  1257. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1258. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  1259. uint32_t is_decrypt = 0;
  1260. uint32_t decrypt_status;
  1261. decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
  1262. if (!decrypt_status)
  1263. is_decrypt = 1;
  1264. return is_decrypt;
  1265. }
  1266. /*
  1267. * Get key index from RX_MSDU_END
  1268. */
  1269. #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \
  1270. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  1271. RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \
  1272. RX_MSDU_END_2_KEY_ID_OCTET_MASK, \
  1273. RX_MSDU_END_2_KEY_ID_OCTET_LSB))
  1274. /*
  1275. * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet
  1276. * from rx_msdu_end
  1277. *
  1278. * @buf: pointer to the start of RX PKT TLV header
  1279. * Return: uint32_t(key id)
  1280. */
  1281. static inline uint32_t
  1282. hal_rx_msdu_get_keyid(uint8_t *buf)
  1283. {
  1284. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1285. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1286. uint32_t keyid_octet;
  1287. keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end);
  1288. return keyid_octet & 0x3;
  1289. }
  1290. #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \
  1291. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1292. RX_MSDU_START_5_USER_RSSI_OFFSET)), \
  1293. RX_MSDU_START_5_USER_RSSI_MASK, \
  1294. RX_MSDU_START_5_USER_RSSI_LSB))
  1295. /*
  1296. * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt
  1297. * from rx_msdu_start
  1298. *
  1299. * @buf: pointer to the start of RX PKT TLV header
  1300. * Return: uint32_t(rssi)
  1301. */
  1302. static inline uint32_t
  1303. hal_rx_msdu_start_get_rssi(uint8_t *buf)
  1304. {
  1305. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1306. struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1307. uint32_t rssi;
  1308. rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
  1309. return rssi;
  1310. }
  1311. #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \
  1312. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1313. RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \
  1314. RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
  1315. RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
  1316. /*
  1317. * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel
  1318. * from rx_msdu_start
  1319. *
  1320. * @buf: pointer to the start of RX PKT TLV header
  1321. * Return: uint32_t(frequency)
  1322. */
  1323. static inline uint32_t
  1324. hal_rx_msdu_start_get_freq(uint8_t *buf)
  1325. {
  1326. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1327. struct rx_msdu_start *msdu_start =
  1328. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1329. uint32_t freq;
  1330. freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  1331. return freq;
  1332. }
  1333. #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
  1334. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1335. RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
  1336. RX_MSDU_START_5_PKT_TYPE_MASK, \
  1337. RX_MSDU_START_5_PKT_TYPE_LSB))
  1338. /*
  1339. * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type
  1340. * from rx_msdu_start
  1341. *
  1342. * @buf: pointer to the start of RX PKT TLV header
  1343. * Return: uint32_t(pkt type)
  1344. */
  1345. static inline uint32_t
  1346. hal_rx_msdu_start_get_pkt_type(uint8_t *buf)
  1347. {
  1348. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1349. struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1350. uint32_t pkt_type;
  1351. pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
  1352. return pkt_type;
  1353. }
  1354. /*
  1355. * hal_rx_mpdu_get_tods(): API to get the tods info
  1356. * from rx_mpdu_start
  1357. *
  1358. * @buf: pointer to the start of RX PKT TLV header
  1359. * Return: uint32_t(to_ds)
  1360. */
  1361. static inline uint32_t
  1362. hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1363. {
  1364. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1365. return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf);
  1366. }
  1367. /*
  1368. * hal_rx_mpdu_get_fr_ds(): API to get the from ds info
  1369. * from rx_mpdu_start
  1370. * @hal_soc_hdl: hal soc handle
  1371. * @buf: pointer to the start of RX PKT TLV header
  1372. *
  1373. * Return: uint32_t(fr_ds)
  1374. */
  1375. static inline uint32_t
  1376. hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1377. {
  1378. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1379. return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf);
  1380. }
  1381. #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
  1382. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  1383. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
  1384. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
  1385. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
  1386. #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
  1387. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  1388. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
  1389. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
  1390. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
  1391. /*
  1392. * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu
  1393. * @hal_soc_hdl: hal soc handle
  1394. * @buf: pointer to the start of RX PKT TLV headera
  1395. * @mac_addr: pointer to mac address
  1396. *
  1397. * Return: success/failure
  1398. */
  1399. static inline
  1400. QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl,
  1401. uint8_t *buf, uint8_t *mac_addr)
  1402. {
  1403. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1404. return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr);
  1405. }
  1406. /*
  1407. * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu
  1408. * in the packet
  1409. * @hal_soc_hdl: hal soc handle
  1410. * @buf: pointer to the start of RX PKT TLV header
  1411. * @mac_addr: pointer to mac address
  1412. *
  1413. * Return: success/failure
  1414. */
  1415. static inline
  1416. QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl,
  1417. uint8_t *buf, uint8_t *mac_addr)
  1418. {
  1419. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1420. return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr);
  1421. }
  1422. /*
  1423. * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu
  1424. * in the packet
  1425. * @hal_soc_hdl: hal soc handle
  1426. * @buf: pointer to the start of RX PKT TLV header
  1427. * @mac_addr: pointer to mac address
  1428. *
  1429. * Return: success/failure
  1430. */
  1431. static inline
  1432. QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl,
  1433. uint8_t *buf, uint8_t *mac_addr)
  1434. {
  1435. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1436. return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr);
  1437. }
  1438. /*
  1439. * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu
  1440. * in the packet
  1441. * @hal_soc_hdl: hal_soc handle
  1442. * @buf: pointer to the start of RX PKT TLV header
  1443. * @mac_addr: pointer to mac address
  1444. * Return: success/failure
  1445. */
  1446. static inline
  1447. QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl,
  1448. uint8_t *buf, uint8_t *mac_addr)
  1449. {
  1450. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1451. return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr);
  1452. }
  1453. /**
  1454. * hal_rx_msdu_end_da_idx_get: API to get da_idx
  1455. * from rx_msdu_end TLV
  1456. *
  1457. * @ buf: pointer to the start of RX PKT TLV headers
  1458. * Return: da index
  1459. */
  1460. static inline uint16_t
  1461. hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1462. {
  1463. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1464. return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf);
  1465. }
  1466. /**
  1467. * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid
  1468. * from rx_msdu_end TLV
  1469. * @hal_soc_hdl: hal soc handle
  1470. * @ buf: pointer to the start of RX PKT TLV headers
  1471. *
  1472. * Return: da_is_valid
  1473. */
  1474. static inline uint8_t
  1475. hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  1476. uint8_t *buf)
  1477. {
  1478. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1479. return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf);
  1480. }
  1481. /**
  1482. * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
  1483. * from rx_msdu_end TLV
  1484. *
  1485. * @buf: pointer to the start of RX PKT TLV headers
  1486. *
  1487. * Return: da_is_mcbc
  1488. */
  1489. static inline uint8_t
  1490. hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1491. {
  1492. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1493. return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf);
  1494. }
  1495. /**
  1496. * hal_rx_msdu_end_first_msdu_get: API to get first msdu status
  1497. * from rx_msdu_end TLV
  1498. * @hal_soc_hdl: hal soc handle
  1499. * @buf: pointer to the start of RX PKT TLV headers
  1500. *
  1501. * Return: first_msdu
  1502. */
  1503. static inline uint8_t
  1504. hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1505. uint8_t *buf)
  1506. {
  1507. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1508. return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf);
  1509. }
  1510. /**
  1511. * hal_rx_msdu_end_last_msdu_get: API to get last msdu status
  1512. * from rx_msdu_end TLV
  1513. * @hal_soc_hdl: hal soc handle
  1514. * @buf: pointer to the start of RX PKT TLV headers
  1515. *
  1516. * Return: last_msdu
  1517. */
  1518. static inline uint8_t
  1519. hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1520. uint8_t *buf)
  1521. {
  1522. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1523. return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf);
  1524. }
  1525. /**
  1526. * hal_rx_msdu_cce_metadata_get: API to get CCE metadata
  1527. * from rx_msdu_end TLV
  1528. * @buf: pointer to the start of RX PKT TLV headers
  1529. * Return: cce_meta_data
  1530. */
  1531. static inline uint16_t
  1532. hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1533. uint8_t *buf)
  1534. {
  1535. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1536. return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf);
  1537. }
  1538. /*******************************************************************************
  1539. * RX ERROR APIS
  1540. ******************************************************************************/
  1541. #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \
  1542. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  1543. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \
  1544. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
  1545. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
  1546. /**
  1547. * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR
  1548. * from rx_mpdu_end TLV
  1549. *
  1550. * @buf: pointer to the start of RX PKT TLV headers
  1551. * Return: uint32_t(decrypt_err)
  1552. */
  1553. static inline uint32_t
  1554. hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf)
  1555. {
  1556. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1557. struct rx_mpdu_end *mpdu_end =
  1558. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  1559. uint32_t decrypt_err;
  1560. decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
  1561. return decrypt_err;
  1562. }
  1563. #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
  1564. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  1565. RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
  1566. RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
  1567. RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
  1568. /**
  1569. * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR
  1570. * from rx_mpdu_end TLV
  1571. *
  1572. * @buf: pointer to the start of RX PKT TLV headers
  1573. * Return: uint32_t(mic_err)
  1574. */
  1575. static inline uint32_t
  1576. hal_rx_mpdu_end_mic_err_get(uint8_t *buf)
  1577. {
  1578. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1579. struct rx_mpdu_end *mpdu_end =
  1580. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  1581. uint32_t mic_err;
  1582. mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
  1583. return mic_err;
  1584. }
  1585. /*******************************************************************************
  1586. * RX REO ERROR APIS
  1587. ******************************************************************************/
  1588. #define HAL_RX_NUM_MSDU_DESC 6
  1589. #define HAL_RX_MAX_SAVED_RING_DESC 16
  1590. /* TODO: rework the structure */
  1591. struct hal_rx_msdu_list {
  1592. struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
  1593. uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC];
  1594. uint8_t rbm[HAL_RX_NUM_MSDU_DESC];
  1595. /* physical address of the msdu */
  1596. uint64_t paddr[HAL_RX_NUM_MSDU_DESC];
  1597. };
  1598. struct hal_buf_info {
  1599. uint64_t paddr;
  1600. uint32_t sw_cookie;
  1601. uint8_t rbm;
  1602. };
  1603. /**
  1604. * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details
  1605. * @msdu_link_ptr - msdu link ptr
  1606. * @hal - pointer to hal_soc
  1607. * Return - Pointer to rx_msdu_details structure
  1608. *
  1609. */
  1610. static inline
  1611. void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr,
  1612. struct hal_soc *hal_soc)
  1613. {
  1614. return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr);
  1615. }
  1616. /**
  1617. * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
  1618. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1619. * @hal - pointer to hal_soc
  1620. * Return - Pointer to rx_msdu_desc_info structure.
  1621. *
  1622. */
  1623. static inline
  1624. void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr,
  1625. struct hal_soc *hal_soc)
  1626. {
  1627. return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr);
  1628. }
  1629. /* This special cookie value will be used to indicate FW allocated buffers
  1630. * received through RXDMA2SW ring for RXDMA WARs
  1631. */
  1632. #define HAL_RX_COOKIE_SPECIAL 0x1fffff
  1633. /**
  1634. * hal_rx_msdu_link_desc_get(): API to get the MSDU information
  1635. * from the MSDU link descriptor
  1636. *
  1637. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  1638. * MSDU link descriptor (struct rx_msdu_link)
  1639. *
  1640. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  1641. *
  1642. * @num_msdus: Number of MSDUs in the MPDU
  1643. *
  1644. * Return: void
  1645. */
  1646. static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl,
  1647. void *msdu_link_desc,
  1648. struct hal_rx_msdu_list *msdu_list,
  1649. uint16_t *num_msdus)
  1650. {
  1651. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1652. struct rx_msdu_details *msdu_details;
  1653. struct rx_msdu_desc_info *msdu_desc_info;
  1654. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1655. int i;
  1656. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  1657. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1658. "[%s][%d] msdu_link=%pK msdu_details=%pK",
  1659. __func__, __LINE__, msdu_link, msdu_details);
  1660. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  1661. /* num_msdus received in mpdu descriptor may be incorrect
  1662. * sometimes due to HW issue. Check msdu buffer address also
  1663. */
  1664. if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET(
  1665. &msdu_details[i].buffer_addr_info_details) == 0))
  1666. break;
  1667. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  1668. &msdu_details[i].buffer_addr_info_details) == 0) {
  1669. /* set the last msdu bit in the prev msdu_desc_info */
  1670. msdu_desc_info =
  1671. hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc);
  1672. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1673. break;
  1674. }
  1675. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  1676. hal_soc);
  1677. /* set first MSDU bit or the last MSDU bit */
  1678. if (!i)
  1679. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1680. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  1681. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1682. msdu_list->msdu_info[i].msdu_flags =
  1683. HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  1684. msdu_list->msdu_info[i].msdu_len =
  1685. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  1686. msdu_list->sw_cookie[i] =
  1687. HAL_RX_BUF_COOKIE_GET(
  1688. &msdu_details[i].buffer_addr_info_details);
  1689. msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET(
  1690. &msdu_details[i].buffer_addr_info_details);
  1691. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  1692. &msdu_details[i].buffer_addr_info_details) |
  1693. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  1694. &msdu_details[i].buffer_addr_info_details) << 32;
  1695. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1696. "[%s][%d] i=%d sw_cookie=%d",
  1697. __func__, __LINE__, i, msdu_list->sw_cookie[i]);
  1698. }
  1699. *num_msdus = i;
  1700. }
  1701. /**
  1702. * hal_rx_msdu_reo_dst_ind_get: Gets the REO
  1703. * destination ring ID from the msdu desc info
  1704. *
  1705. * @msdu_link_desc : Opaque cookie pointer used by HAL to get to
  1706. * the current descriptor
  1707. *
  1708. * Return: dst_ind (REO destination ring ID)
  1709. */
  1710. static inline uint32_t
  1711. hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc)
  1712. {
  1713. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1714. struct rx_msdu_details *msdu_details;
  1715. struct rx_msdu_desc_info *msdu_desc_info;
  1716. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1717. uint32_t dst_ind;
  1718. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  1719. /* The first msdu in the link should exsist */
  1720. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0],
  1721. hal_soc);
  1722. dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
  1723. return dst_ind;
  1724. }
  1725. /**
  1726. * hal_rx_reo_buf_paddr_get: Gets the physical address and
  1727. * cookie from the REO destination ring element
  1728. *
  1729. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1730. * the current descriptor
  1731. * @ buf_info: structure to return the buffer information
  1732. * Return: void
  1733. */
  1734. static inline
  1735. void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc,
  1736. struct hal_buf_info *buf_info)
  1737. {
  1738. struct reo_destination_ring *reo_ring =
  1739. (struct reo_destination_ring *)rx_desc;
  1740. buf_info->paddr =
  1741. (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
  1742. ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
  1743. buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring);
  1744. }
  1745. /**
  1746. * enum hal_reo_error_code: Indicates that type of buffer or descriptor
  1747. *
  1748. * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer
  1749. * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link
  1750. * descriptor
  1751. */
  1752. enum hal_rx_reo_buf_type {
  1753. HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0,
  1754. HAL_RX_REO_MSDU_LINK_DESC_TYPE,
  1755. };
  1756. #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \
  1757. (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \
  1758. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \
  1759. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB)
  1760. #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \
  1761. (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \
  1762. REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \
  1763. REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB)
  1764. /**
  1765. * enum hal_reo_error_code: Error code describing the type of error detected
  1766. *
  1767. * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the
  1768. * REO_ENTRANCE ring is set to 0
  1769. * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set
  1770. * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session
  1771. * having been setup
  1772. * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN,
  1773. * Retry bit set: duplicate frame
  1774. * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame
  1775. * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame)
  1776. * received with 2K jump in SN
  1777. * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN
  1778. * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received
  1779. * with SN falling within the OOR window
  1780. * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the
  1781. * OOR window
  1782. * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session
  1783. * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN
  1784. * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet
  1785. * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  1786. * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor
  1787. * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  1788. * of the pn_error_detected_flag been set in the REO Queue descriptor
  1789. * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of
  1790. * the queue descriptor(address) being blocked as SW/FW seems to be currently
  1791. * in the process of making updates to this descriptor
  1792. */
  1793. enum hal_reo_error_code {
  1794. HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0,
  1795. HAL_REO_ERR_QUEUE_DESC_INVALID,
  1796. HAL_REO_ERR_AMPDU_IN_NON_BA,
  1797. HAL_REO_ERR_NON_BA_DUPLICATE,
  1798. HAL_REO_ERR_BA_DUPLICATE,
  1799. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP,
  1800. HAL_REO_ERR_BAR_FRAME_2K_JUMP,
  1801. HAL_REO_ERR_REGULAR_FRAME_OOR,
  1802. HAL_REO_ERR_BAR_FRAME_OOR,
  1803. HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION,
  1804. HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN,
  1805. HAL_REO_ERR_PN_CHECK_FAILED,
  1806. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET,
  1807. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET,
  1808. HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET,
  1809. HAL_REO_ERR_MAX
  1810. };
  1811. /**
  1812. * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected
  1813. *
  1814. * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow
  1815. * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO
  1816. * overflow
  1817. * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving
  1818. * incomplete
  1819. * MPDU from the PHY
  1820. * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed
  1821. * @ HAL_RXDMA_ERR_DECRYPT : Decryption error
  1822. * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error
  1823. * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be
  1824. * encrypted but wasn’t
  1825. * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error
  1826. * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded
  1827. * the max allowed
  1828. * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error
  1829. * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error
  1830. * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout
  1831. * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout
  1832. * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout
  1833. * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request
  1834. * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors
  1835. */
  1836. enum hal_rxdma_error_code {
  1837. HAL_RXDMA_ERR_OVERFLOW = 0,
  1838. HAL_RXDMA_ERR_MPDU_LENGTH,
  1839. HAL_RXDMA_ERR_FCS,
  1840. HAL_RXDMA_ERR_DECRYPT,
  1841. HAL_RXDMA_ERR_TKIP_MIC,
  1842. HAL_RXDMA_ERR_UNENCRYPTED,
  1843. HAL_RXDMA_ERR_MSDU_LEN,
  1844. HAL_RXDMA_ERR_MSDU_LIMIT,
  1845. HAL_RXDMA_ERR_WIFI_PARSE,
  1846. HAL_RXDMA_ERR_AMSDU_PARSE,
  1847. HAL_RXDMA_ERR_SA_TIMEOUT,
  1848. HAL_RXDMA_ERR_DA_TIMEOUT,
  1849. HAL_RXDMA_ERR_FLOW_TIMEOUT,
  1850. HAL_RXDMA_ERR_FLUSH_REQUEST,
  1851. HAL_RXDMA_ERR_WAR = 31,
  1852. HAL_RXDMA_ERR_MAX
  1853. };
  1854. /**
  1855. * HW BM action settings in WBM release ring
  1856. */
  1857. #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0
  1858. #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1
  1859. /**
  1860. * enum hal_rx_wbm_error_source: Indicates which module initiated the
  1861. * release of this buffer or descriptor
  1862. *
  1863. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  1864. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  1865. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  1866. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  1867. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  1868. */
  1869. enum hal_rx_wbm_error_source {
  1870. HAL_RX_WBM_ERR_SRC_TQM = 0,
  1871. HAL_RX_WBM_ERR_SRC_RXDMA,
  1872. HAL_RX_WBM_ERR_SRC_REO,
  1873. HAL_RX_WBM_ERR_SRC_FW,
  1874. HAL_RX_WBM_ERR_SRC_SW,
  1875. };
  1876. /**
  1877. * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor
  1878. * released
  1879. *
  1880. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  1881. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  1882. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  1883. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  1884. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  1885. */
  1886. enum hal_rx_wbm_buf_type {
  1887. HAL_RX_WBM_BUF_TYPE_REL_BUF = 0,
  1888. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC,
  1889. HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC,
  1890. HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC,
  1891. HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC,
  1892. };
  1893. #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \
  1894. (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \
  1895. REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \
  1896. REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB)
  1897. /**
  1898. * hal_rx_is_pn_error() - Indicate if this error was caused by a
  1899. * PN check failure
  1900. *
  1901. * @reo_desc: opaque pointer used by HAL to get the REO destination entry
  1902. *
  1903. * Return: true: error caused by PN check, false: other error
  1904. */
  1905. static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc)
  1906. {
  1907. struct reo_destination_ring *reo_desc =
  1908. (struct reo_destination_ring *)rx_desc;
  1909. return ((HAL_RX_REO_ERROR_GET(reo_desc) ==
  1910. HAL_REO_ERR_PN_CHECK_FAILED) |
  1911. (HAL_RX_REO_ERROR_GET(reo_desc) ==
  1912. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ?
  1913. true : false;
  1914. }
  1915. /**
  1916. * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in
  1917. * the sequence number
  1918. *
  1919. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1920. *
  1921. * Return: true: error caused by 2K jump, false: other error
  1922. */
  1923. static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc)
  1924. {
  1925. struct reo_destination_ring *reo_desc =
  1926. (struct reo_destination_ring *)rx_desc;
  1927. return ((HAL_RX_REO_ERROR_GET(reo_desc) ==
  1928. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) |
  1929. (HAL_RX_REO_ERROR_GET(reo_desc) ==
  1930. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ?
  1931. true : false;
  1932. }
  1933. /**
  1934. * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR
  1935. *
  1936. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1937. *
  1938. * Return: true: error caused by OOR, false: other error
  1939. */
  1940. static inline bool hal_rx_reo_is_oor_error(void *rx_desc)
  1941. {
  1942. struct reo_destination_ring *reo_desc =
  1943. (struct reo_destination_ring *)rx_desc;
  1944. return (HAL_RX_REO_ERROR_GET(reo_desc) ==
  1945. HAL_REO_ERR_REGULAR_FRAME_OOR) ? true : false;
  1946. }
  1947. #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
  1948. /**
  1949. * hal_dump_wbm_rel_desc() - dump wbm release descriptor
  1950. * @hal_desc: hardware descriptor pointer
  1951. *
  1952. * This function will print wbm release descriptor
  1953. *
  1954. * Return: none
  1955. */
  1956. static inline void hal_dump_wbm_rel_desc(void *src_srng_desc)
  1957. {
  1958. uint32_t *wbm_comp = (uint32_t *)src_srng_desc;
  1959. uint32_t i;
  1960. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1961. "Current Rx wbm release descriptor is");
  1962. for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) {
  1963. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1964. "DWORD[i] = 0x%x", wbm_comp[i]);
  1965. }
  1966. }
  1967. /**
  1968. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  1969. *
  1970. * @ hal_soc_hdl : HAL version of the SOC pointer
  1971. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  1972. * @ buf_addr_info : void pointer to the buffer_addr_info
  1973. * @ bm_action : put in IDLE list or release to MSDU_LIST
  1974. *
  1975. * Return: void
  1976. */
  1977. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  1978. static inline
  1979. void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl,
  1980. void *src_srng_desc,
  1981. hal_buff_addrinfo_t buf_addr_info,
  1982. uint8_t bm_action)
  1983. {
  1984. struct wbm_release_ring *wbm_rel_srng =
  1985. (struct wbm_release_ring *)src_srng_desc;
  1986. uint32_t addr_31_0;
  1987. uint8_t addr_39_32;
  1988. /* Structure copy !!! */
  1989. wbm_rel_srng->released_buff_or_desc_addr_info =
  1990. *((struct buffer_addr_info *)buf_addr_info);
  1991. addr_31_0 =
  1992. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0;
  1993. addr_39_32 =
  1994. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32;
  1995. HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2,
  1996. RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW);
  1997. HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION,
  1998. bm_action);
  1999. HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2,
  2000. BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC);
  2001. /* WBM error is indicated when any of the link descriptors given to
  2002. * WBM has a NULL address, and one those paths is the link descriptors
  2003. * released from host after processing RXDMA errors,
  2004. * or from Rx defrag path, and we want to add an assert here to ensure
  2005. * host is not releasing descriptors with NULL address.
  2006. */
  2007. if (qdf_unlikely(!addr_31_0 && !addr_39_32)) {
  2008. hal_dump_wbm_rel_desc(src_srng_desc);
  2009. qdf_assert_always(0);
  2010. }
  2011. }
  2012. /*
  2013. * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to
  2014. * REO entrance ring
  2015. *
  2016. * @ soc: HAL version of the SOC pointer
  2017. * @ pa: Physical address of the MSDU Link Descriptor
  2018. * @ cookie: SW cookie to get to the virtual address
  2019. * @ error_enabled_reo_q: Argument to determine whether this needs to go
  2020. * to the error enabled REO queue
  2021. *
  2022. * Return: void
  2023. */
  2024. static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc,
  2025. uint64_t pa, uint32_t cookie, bool error_enabled_reo_q)
  2026. {
  2027. /* TODO */
  2028. }
  2029. /**
  2030. * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the
  2031. * BUFFER_ADDR_INFO, give the RX descriptor
  2032. * (Assumption -- BUFFER_ADDR_INFO is the
  2033. * first field in the descriptor structure)
  2034. */
  2035. #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \
  2036. ((hal_link_desc_t)(ring_desc))
  2037. #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  2038. #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  2039. /**
  2040. * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager"
  2041. * from the BUFFER_ADDR_INFO structure
  2042. * given a REO destination ring descriptor.
  2043. * @ ring_desc: RX(REO/WBM release) destination ring descriptor
  2044. *
  2045. * Return: uint8_t (value of the return_buffer_manager)
  2046. */
  2047. static inline
  2048. uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc)
  2049. {
  2050. /*
  2051. * The following macro takes buf_addr_info as argument,
  2052. * but since buf_addr_info is the first field in ring_desc
  2053. * Hence the following call is OK
  2054. */
  2055. return HAL_RX_BUF_RBM_GET(ring_desc);
  2056. }
  2057. /*******************************************************************************
  2058. * RX WBM ERROR APIS
  2059. ******************************************************************************/
  2060. #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  2061. (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \
  2062. WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \
  2063. WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB)
  2064. /**
  2065. * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed
  2066. * the frame to this release ring
  2067. *
  2068. * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this
  2069. * frame to this queue
  2070. * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per
  2071. * received routing instructions. No error within REO was detected
  2072. */
  2073. enum hal_rx_wbm_reo_push_reason {
  2074. HAL_RX_WBM_REO_PSH_RSN_ERROR = 0,
  2075. HAL_RX_WBM_REO_PSH_RSN_ROUTE,
  2076. };
  2077. /**
  2078. * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to
  2079. * this release ring
  2080. *
  2081. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed
  2082. * this frame to this queue
  2083. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue
  2084. * per received routing instructions. No error within RXDMA was detected
  2085. */
  2086. enum hal_rx_wbm_rxdma_push_reason {
  2087. HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0,
  2088. HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE,
  2089. };
  2090. #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \
  2091. (((*(((uint32_t *) wbm_desc) + \
  2092. (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \
  2093. WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \
  2094. WBM_RELEASE_RING_4_FIRST_MSDU_LSB)
  2095. #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \
  2096. (((*(((uint32_t *) wbm_desc) + \
  2097. (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \
  2098. WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \
  2099. WBM_RELEASE_RING_4_LAST_MSDU_LSB)
  2100. #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \
  2101. HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \
  2102. wbm_desc)->released_buff_or_desc_addr_info)
  2103. /**
  2104. * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured
  2105. * humman readable format.
  2106. * @ rx_attn: pointer the rx_attention TLV in pkt.
  2107. * @ dbg_level: log level.
  2108. *
  2109. * Return: void
  2110. */
  2111. static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn,
  2112. uint8_t dbg_level)
  2113. {
  2114. hal_verbose_debug(
  2115. "rx_attention tlv (1/2) - "
  2116. "rxpcu_mpdu_filter_in_category: %x "
  2117. "sw_frame_group_id: %x "
  2118. "reserved_0: %x "
  2119. "phy_ppdu_id: %x "
  2120. "first_mpdu : %x "
  2121. "reserved_1a: %x "
  2122. "mcast_bcast: %x "
  2123. "ast_index_not_found: %x "
  2124. "ast_index_timeout: %x "
  2125. "power_mgmt: %x "
  2126. "non_qos: %x "
  2127. "null_data: %x "
  2128. "mgmt_type: %x "
  2129. "ctrl_type: %x "
  2130. "more_data: %x "
  2131. "eosp: %x "
  2132. "a_msdu_error: %x "
  2133. "fragment_flag: %x "
  2134. "order: %x "
  2135. "cce_match: %x "
  2136. "overflow_err: %x "
  2137. "msdu_length_err: %x "
  2138. "tcp_udp_chksum_fail: %x "
  2139. "ip_chksum_fail: %x "
  2140. "sa_idx_invalid: %x "
  2141. "da_idx_invalid: %x "
  2142. "reserved_1b: %x "
  2143. "rx_in_tx_decrypt_byp: %x ",
  2144. rx_attn->rxpcu_mpdu_filter_in_category,
  2145. rx_attn->sw_frame_group_id,
  2146. rx_attn->reserved_0,
  2147. rx_attn->phy_ppdu_id,
  2148. rx_attn->first_mpdu,
  2149. rx_attn->reserved_1a,
  2150. rx_attn->mcast_bcast,
  2151. rx_attn->ast_index_not_found,
  2152. rx_attn->ast_index_timeout,
  2153. rx_attn->power_mgmt,
  2154. rx_attn->non_qos,
  2155. rx_attn->null_data,
  2156. rx_attn->mgmt_type,
  2157. rx_attn->ctrl_type,
  2158. rx_attn->more_data,
  2159. rx_attn->eosp,
  2160. rx_attn->a_msdu_error,
  2161. rx_attn->fragment_flag,
  2162. rx_attn->order,
  2163. rx_attn->cce_match,
  2164. rx_attn->overflow_err,
  2165. rx_attn->msdu_length_err,
  2166. rx_attn->tcp_udp_chksum_fail,
  2167. rx_attn->ip_chksum_fail,
  2168. rx_attn->sa_idx_invalid,
  2169. rx_attn->da_idx_invalid,
  2170. rx_attn->reserved_1b,
  2171. rx_attn->rx_in_tx_decrypt_byp);
  2172. hal_verbose_debug(
  2173. "rx_attention tlv (2/2) - "
  2174. "encrypt_required: %x "
  2175. "directed: %x "
  2176. "buffer_fragment: %x "
  2177. "mpdu_length_err: %x "
  2178. "tkip_mic_err: %x "
  2179. "decrypt_err: %x "
  2180. "unencrypted_frame_err: %x "
  2181. "fcs_err: %x "
  2182. "flow_idx_timeout: %x "
  2183. "flow_idx_invalid: %x "
  2184. "wifi_parser_error: %x "
  2185. "amsdu_parser_error: %x "
  2186. "sa_idx_timeout: %x "
  2187. "da_idx_timeout: %x "
  2188. "msdu_limit_error: %x "
  2189. "da_is_valid: %x "
  2190. "da_is_mcbc: %x "
  2191. "sa_is_valid: %x "
  2192. "decrypt_status_code: %x "
  2193. "rx_bitmap_not_updated: %x "
  2194. "reserved_2: %x "
  2195. "msdu_done: %x ",
  2196. rx_attn->encrypt_required,
  2197. rx_attn->directed,
  2198. rx_attn->buffer_fragment,
  2199. rx_attn->mpdu_length_err,
  2200. rx_attn->tkip_mic_err,
  2201. rx_attn->decrypt_err,
  2202. rx_attn->unencrypted_frame_err,
  2203. rx_attn->fcs_err,
  2204. rx_attn->flow_idx_timeout,
  2205. rx_attn->flow_idx_invalid,
  2206. rx_attn->wifi_parser_error,
  2207. rx_attn->amsdu_parser_error,
  2208. rx_attn->sa_idx_timeout,
  2209. rx_attn->da_idx_timeout,
  2210. rx_attn->msdu_limit_error,
  2211. rx_attn->da_is_valid,
  2212. rx_attn->da_is_mcbc,
  2213. rx_attn->sa_is_valid,
  2214. rx_attn->decrypt_status_code,
  2215. rx_attn->rx_bitmap_not_updated,
  2216. rx_attn->reserved_2,
  2217. rx_attn->msdu_done);
  2218. }
  2219. static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start,
  2220. uint8_t dbg_level,
  2221. struct hal_soc *hal)
  2222. {
  2223. hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level);
  2224. }
  2225. /**
  2226. * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured
  2227. * human readable format.
  2228. * @ msdu_end: pointer the msdu_end TLV in pkt.
  2229. * @ dbg_level: log level.
  2230. *
  2231. * Return: void
  2232. */
  2233. static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc,
  2234. struct rx_msdu_end *msdu_end,
  2235. uint8_t dbg_level)
  2236. {
  2237. hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level);
  2238. }
  2239. /**
  2240. * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured
  2241. * human readable format.
  2242. * @ mpdu_end: pointer the mpdu_end TLV in pkt.
  2243. * @ dbg_level: log level.
  2244. *
  2245. * Return: void
  2246. */
  2247. static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end,
  2248. uint8_t dbg_level)
  2249. {
  2250. hal_verbose_debug(
  2251. "rx_mpdu_end tlv - "
  2252. "rxpcu_mpdu_filter_in_category: %x "
  2253. "sw_frame_group_id: %x "
  2254. "phy_ppdu_id: %x "
  2255. "unsup_ktype_short_frame: %x "
  2256. "rx_in_tx_decrypt_byp: %x "
  2257. "overflow_err: %x "
  2258. "mpdu_length_err: %x "
  2259. "tkip_mic_err: %x "
  2260. "decrypt_err: %x "
  2261. "unencrypted_frame_err: %x "
  2262. "pn_fields_contain_valid_info: %x "
  2263. "fcs_err: %x "
  2264. "msdu_length_err: %x "
  2265. "rxdma0_destination_ring: %x "
  2266. "rxdma1_destination_ring: %x "
  2267. "decrypt_status_code: %x "
  2268. "rx_bitmap_not_updated: %x ",
  2269. mpdu_end->rxpcu_mpdu_filter_in_category,
  2270. mpdu_end->sw_frame_group_id,
  2271. mpdu_end->phy_ppdu_id,
  2272. mpdu_end->unsup_ktype_short_frame,
  2273. mpdu_end->rx_in_tx_decrypt_byp,
  2274. mpdu_end->overflow_err,
  2275. mpdu_end->mpdu_length_err,
  2276. mpdu_end->tkip_mic_err,
  2277. mpdu_end->decrypt_err,
  2278. mpdu_end->unencrypted_frame_err,
  2279. mpdu_end->pn_fields_contain_valid_info,
  2280. mpdu_end->fcs_err,
  2281. mpdu_end->msdu_length_err,
  2282. mpdu_end->rxdma0_destination_ring,
  2283. mpdu_end->rxdma1_destination_ring,
  2284. mpdu_end->decrypt_status_code,
  2285. mpdu_end->rx_bitmap_not_updated);
  2286. }
  2287. #ifdef NO_RX_PKT_HDR_TLV
  2288. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  2289. uint8_t dbg_level)
  2290. {
  2291. }
  2292. #else
  2293. /**
  2294. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  2295. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  2296. * @ dbg_level: log level.
  2297. *
  2298. * Return: void
  2299. */
  2300. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  2301. uint8_t dbg_level)
  2302. {
  2303. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  2304. hal_verbose_debug(
  2305. "\n---------------\n"
  2306. "rx_pkt_hdr_tlv \n"
  2307. "---------------\n"
  2308. "phy_ppdu_id %d ",
  2309. pkt_hdr_tlv->phy_ppdu_id);
  2310. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
  2311. }
  2312. #endif
  2313. /**
  2314. * hal_srng_ring_id_get: API to retrieve ring id from hal ring
  2315. * structure
  2316. * @hal_ring: pointer to hal_srng structure
  2317. *
  2318. * Return: ring_id
  2319. */
  2320. static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl)
  2321. {
  2322. return ((struct hal_srng *)hal_ring_hdl)->ring_id;
  2323. }
  2324. /* Rx MSDU link pointer info */
  2325. struct hal_rx_msdu_link_ptr_info {
  2326. struct rx_msdu_link msdu_link;
  2327. struct hal_buf_info msdu_link_buf_info;
  2328. };
  2329. /**
  2330. * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf
  2331. *
  2332. * @nbuf: Pointer to data buffer field
  2333. * Returns: pointer to rx_pkt_tlvs
  2334. */
  2335. static inline
  2336. struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start)
  2337. {
  2338. return (struct rx_pkt_tlvs *)rx_buf_start;
  2339. }
  2340. /**
  2341. * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs
  2342. *
  2343. * @pkt_tlvs: Pointer to pkt_tlvs
  2344. * Returns: pointer to rx_mpdu_info structure
  2345. */
  2346. static inline
  2347. struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs)
  2348. {
  2349. return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  2350. }
  2351. #define DOT11_SEQ_FRAG_MASK 0x000f
  2352. #define DOT11_FC1_MORE_FRAG_OFFSET 0x04
  2353. /**
  2354. * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number
  2355. *
  2356. * @nbuf: Network buffer
  2357. * Returns: rx fragment number
  2358. */
  2359. static inline
  2360. uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc,
  2361. uint8_t *buf)
  2362. {
  2363. return hal_soc->ops->hal_rx_get_rx_fragment_number(buf);
  2364. }
  2365. #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \
  2366. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  2367. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \
  2368. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \
  2369. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB))
  2370. /**
  2371. * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit
  2372. *
  2373. * @nbuf: Network buffer
  2374. * Returns: rx more fragment bit
  2375. */
  2376. static inline
  2377. uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf)
  2378. {
  2379. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  2380. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  2381. uint16_t frame_ctrl = 0;
  2382. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >>
  2383. DOT11_FC1_MORE_FRAG_OFFSET;
  2384. /* more fragment bit if at offset bit 4 */
  2385. return frame_ctrl;
  2386. }
  2387. /**
  2388. * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field
  2389. *
  2390. * @nbuf: Network buffer
  2391. * Returns: rx more fragment bit
  2392. *
  2393. */
  2394. static inline
  2395. uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf)
  2396. {
  2397. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  2398. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  2399. uint16_t frame_ctrl = 0;
  2400. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
  2401. return frame_ctrl;
  2402. }
  2403. /*
  2404. * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address
  2405. *
  2406. * @nbuf: Network buffer
  2407. * Returns: flag to indicate whether the nbuf has MC/BC address
  2408. */
  2409. static inline
  2410. uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf)
  2411. {
  2412. uint8 *buf = qdf_nbuf_data(nbuf);
  2413. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2414. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  2415. return rx_attn->mcast_bcast;
  2416. }
  2417. /*
  2418. * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid
  2419. * @hal_soc_hdl: hal soc handle
  2420. * @nbuf: Network buffer
  2421. *
  2422. * Return: value of sequence control valid field
  2423. */
  2424. static inline
  2425. uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl,
  2426. uint8_t *buf)
  2427. {
  2428. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2429. return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf);
  2430. }
  2431. /*
  2432. * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid
  2433. * @hal_soc_hdl: hal soc handle
  2434. * @nbuf: Network buffer
  2435. *
  2436. * Returns: value of frame control valid field
  2437. */
  2438. static inline
  2439. uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl,
  2440. uint8_t *buf)
  2441. {
  2442. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2443. return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf);
  2444. }
  2445. /**
  2446. * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid
  2447. * @hal_soc_hdl: hal soc handle
  2448. * @nbuf: Network buffer
  2449. * Returns: value of mpdu 4th address valid field
  2450. */
  2451. static inline
  2452. bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl,
  2453. uint8_t *buf)
  2454. {
  2455. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2456. return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf);
  2457. }
  2458. /*
  2459. * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info
  2460. *
  2461. * @rx_mpdu_desc_info: HAL view of rx mpdu desc info
  2462. * Returns: None
  2463. */
  2464. static inline
  2465. void hal_rx_clear_mpdu_desc_info(
  2466. struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info)
  2467. {
  2468. qdf_mem_zero(rx_mpdu_desc_info,
  2469. sizeof(*rx_mpdu_desc_info));
  2470. }
  2471. /*
  2472. * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr
  2473. *
  2474. * @msdu_link_ptr: HAL view of msdu link ptr
  2475. * @size: number of msdu link pointers
  2476. * Returns: None
  2477. */
  2478. static inline
  2479. void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr,
  2480. int size)
  2481. {
  2482. qdf_mem_zero(msdu_link_ptr,
  2483. (sizeof(*msdu_link_ptr) * size));
  2484. }
  2485. /*
  2486. * hal_rx_chain_msdu_links() - Chains msdu link pointers
  2487. * @msdu_link_ptr: msdu link pointer
  2488. * @mpdu_desc_info: mpdu descriptor info
  2489. *
  2490. * Build a list of msdus using msdu link pointer. If the
  2491. * number of msdus are more, chain them together
  2492. *
  2493. * Returns: Number of processed msdus
  2494. */
  2495. static inline
  2496. int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu,
  2497. struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info,
  2498. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  2499. {
  2500. int j;
  2501. struct rx_msdu_link *msdu_link_ptr =
  2502. &msdu_link_ptr_info->msdu_link;
  2503. struct rx_msdu_link *prev_msdu_link_ptr = NULL;
  2504. struct rx_msdu_details *msdu_details =
  2505. hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc);
  2506. uint8_t num_msdus = mpdu_desc_info->msdu_count;
  2507. struct rx_msdu_desc_info *msdu_desc_info;
  2508. uint8_t fragno, more_frag;
  2509. uint8_t *rx_desc_info;
  2510. struct hal_rx_msdu_list msdu_list;
  2511. for (j = 0; j < num_msdus; j++) {
  2512. msdu_desc_info =
  2513. hal_rx_msdu_desc_info_get_ptr(&msdu_details[j],
  2514. hal_soc);
  2515. msdu_list.msdu_info[j].msdu_flags =
  2516. HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  2517. msdu_list.msdu_info[j].msdu_len =
  2518. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  2519. msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET(
  2520. &msdu_details[j].buffer_addr_info_details);
  2521. }
  2522. /* Chain msdu links together */
  2523. if (prev_msdu_link_ptr) {
  2524. /* 31-0 bits of the physical address */
  2525. prev_msdu_link_ptr->
  2526. next_msdu_link_desc_addr_info.buffer_addr_31_0 =
  2527. msdu_link_ptr_info->msdu_link_buf_info.paddr &
  2528. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK;
  2529. /* 39-32 bits of the physical address */
  2530. prev_msdu_link_ptr->
  2531. next_msdu_link_desc_addr_info.buffer_addr_39_32
  2532. = ((msdu_link_ptr_info->msdu_link_buf_info.paddr
  2533. >> 32) &
  2534. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK);
  2535. prev_msdu_link_ptr->
  2536. next_msdu_link_desc_addr_info.sw_buffer_cookie =
  2537. msdu_link_ptr_info->msdu_link_buf_info.sw_cookie;
  2538. }
  2539. /* There is space for only 6 MSDUs in a MSDU link descriptor */
  2540. if (num_msdus < HAL_RX_NUM_MSDU_DESC) {
  2541. /* mark first and last MSDUs */
  2542. rx_desc_info = qdf_nbuf_data(msdu);
  2543. fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info);
  2544. more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info);
  2545. /* TODO: create skb->fragslist[] */
  2546. if (more_frag == 0) {
  2547. msdu_list.msdu_info[num_msdus].msdu_flags |=
  2548. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK;
  2549. } else if (fragno == 1) {
  2550. msdu_list.msdu_info[num_msdus].msdu_flags |=
  2551. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK;
  2552. msdu_list.msdu_info[num_msdus].msdu_flags |=
  2553. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK;
  2554. }
  2555. num_msdus++;
  2556. /* Number of MSDUs per mpdu descriptor is updated */
  2557. mpdu_desc_info->msdu_count += num_msdus;
  2558. } else {
  2559. num_msdus = 0;
  2560. prev_msdu_link_ptr = msdu_link_ptr;
  2561. }
  2562. return num_msdus;
  2563. }
  2564. /*
  2565. * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc
  2566. *
  2567. * @ring_desc: HAL view of ring descriptor
  2568. * @mpdu_des_info: saved mpdu desc info
  2569. * @msdu_link_ptr: saved msdu link ptr
  2570. *
  2571. * API used explicitly for rx defrag to update ring desc with
  2572. * mpdu desc info and msdu link ptr before reinjecting the
  2573. * packet back to REO
  2574. *
  2575. * Returns: None
  2576. */
  2577. static inline
  2578. void hal_rx_defrag_update_src_ring_desc(
  2579. hal_ring_desc_t ring_desc,
  2580. void *saved_mpdu_desc_info,
  2581. struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr)
  2582. {
  2583. struct reo_entrance_ring *reo_ent_ring;
  2584. struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info;
  2585. struct hal_buf_info buf_info;
  2586. reo_ent_ring = (struct reo_entrance_ring *)ring_desc;
  2587. reo_ring_mpdu_desc_info = &reo_ent_ring->
  2588. reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  2589. qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info,
  2590. sizeof(*reo_ring_mpdu_desc_info));
  2591. /*
  2592. * TODO: Check for additional fields that need configuration in
  2593. * reo_ring_mpdu_desc_info
  2594. */
  2595. /* Update msdu_link_ptr in the reo entrance ring */
  2596. hal_rx_reo_buf_paddr_get(ring_desc, &buf_info);
  2597. buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr;
  2598. buf_info.sw_cookie =
  2599. saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie;
  2600. }
  2601. /*
  2602. * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc
  2603. *
  2604. * @msdu_link_desc_va: msdu link descriptor handle
  2605. * @msdu_link_ptr_info: HAL view of msdu link pointer info
  2606. *
  2607. * API used to save msdu link information along with physical
  2608. * address. The API also copues the sw cookie.
  2609. *
  2610. * Returns: None
  2611. */
  2612. static inline
  2613. void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va,
  2614. struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info,
  2615. struct hal_buf_info *hbi)
  2616. {
  2617. struct rx_msdu_link *msdu_link_ptr =
  2618. (struct rx_msdu_link *)msdu_link_desc_va;
  2619. qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr,
  2620. sizeof(struct rx_msdu_link));
  2621. msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr;
  2622. msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie;
  2623. }
  2624. /*
  2625. * hal_rx_get_desc_len(): Returns rx descriptor length
  2626. *
  2627. * Returns the size of rx_pkt_tlvs which follows the
  2628. * data in the nbuf
  2629. *
  2630. * Returns: Length of rx descriptor
  2631. */
  2632. static inline
  2633. uint16_t hal_rx_get_desc_len(void)
  2634. {
  2635. return SIZE_OF_DATA_RX_TLV;
  2636. }
  2637. /*
  2638. * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from
  2639. * reo_entrance_ring descriptor
  2640. *
  2641. * @reo_ent_desc: reo_entrance_ring descriptor
  2642. * Returns: value of rxdma_push_reason
  2643. */
  2644. static inline
  2645. uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc)
  2646. {
  2647. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  2648. REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)),
  2649. REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK,
  2650. REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB);
  2651. }
  2652. /**
  2653. * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from
  2654. * reo_entrance_ring descriptor
  2655. * @reo_ent_desc: reo_entrance_ring descriptor
  2656. * Return: value of rxdma_error_code
  2657. */
  2658. static inline
  2659. uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc)
  2660. {
  2661. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  2662. REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)),
  2663. REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK,
  2664. REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB);
  2665. }
  2666. /**
  2667. * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and
  2668. * save it to hal_wbm_err_desc_info structure passed by caller
  2669. * @wbm_desc: wbm ring descriptor
  2670. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  2671. * Return: void
  2672. */
  2673. static inline void hal_rx_wbm_err_info_get(void *wbm_desc,
  2674. struct hal_wbm_err_desc_info *wbm_er_info,
  2675. hal_soc_handle_t hal_soc_hdl)
  2676. {
  2677. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2678. hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info);
  2679. }
  2680. /**
  2681. * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to
  2682. * the reserved bytes of rx_tlv_hdr
  2683. * @buf: start of rx_tlv_hdr
  2684. * @wbm_er_info: hal_wbm_err_desc_info structure
  2685. * Return: void
  2686. */
  2687. static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf,
  2688. struct hal_wbm_err_desc_info *wbm_er_info)
  2689. {
  2690. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2691. qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info,
  2692. sizeof(struct hal_wbm_err_desc_info));
  2693. }
  2694. /**
  2695. * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from
  2696. * the reserved bytes of rx_tlv_hdr.
  2697. * @buf: start of rx_tlv_hdr
  2698. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  2699. * Return: void
  2700. */
  2701. static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf,
  2702. struct hal_wbm_err_desc_info *wbm_er_info)
  2703. {
  2704. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2705. qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0,
  2706. sizeof(struct hal_wbm_err_desc_info));
  2707. }
  2708. /**
  2709. * hal_rx_mon_dest_set_buffer_info_to_tlv(): Save the mon dest frame info
  2710. * into the reserved bytes of rx_tlv_hdr.
  2711. * @buf: start of rx_tlv_hdr
  2712. * @buf_info: hal_rx_mon_dest_buf_info structure
  2713. *
  2714. * Return: void
  2715. */
  2716. static inline
  2717. void hal_rx_mon_dest_set_buffer_info_to_tlv(uint8_t *buf,
  2718. struct hal_rx_mon_dest_buf_info *buf_info)
  2719. {
  2720. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2721. qdf_mem_copy(pkt_tlvs->rx_padding0, buf_info,
  2722. sizeof(struct hal_rx_mon_dest_buf_info));
  2723. }
  2724. /**
  2725. * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info
  2726. * from the reserved bytes of rx_tlv_hdr.
  2727. * @buf: start of rx_tlv_hdr
  2728. * @buf_info: hal_rx_mon_dest_buf_info structure
  2729. *
  2730. * Return: void
  2731. */
  2732. static inline
  2733. void hal_rx_mon_dest_get_buffer_info_from_tlv(uint8_t *buf,
  2734. struct hal_rx_mon_dest_buf_info *buf_info)
  2735. {
  2736. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2737. qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0,
  2738. sizeof(struct hal_rx_mon_dest_buf_info));
  2739. }
  2740. /**
  2741. * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation
  2742. * bit from wbm release ring descriptor
  2743. * @wbm_desc: wbm ring descriptor
  2744. * Return: uint8_t
  2745. */
  2746. static inline
  2747. uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl,
  2748. void *wbm_desc)
  2749. {
  2750. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2751. return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc);
  2752. }
  2753. #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \
  2754. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  2755. RX_MSDU_START_5_NSS_OFFSET)), \
  2756. RX_MSDU_START_5_NSS_MASK, \
  2757. RX_MSDU_START_5_NSS_LSB))
  2758. /**
  2759. * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status
  2760. *
  2761. * @ hal_soc: HAL version of the SOC pointer
  2762. * @ hw_desc_addr: Start address of Rx HW TLVs
  2763. * @ rs: Status for monitor mode
  2764. *
  2765. * Return: void
  2766. */
  2767. static inline
  2768. void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl,
  2769. void *hw_desc_addr,
  2770. struct mon_rx_status *rs)
  2771. {
  2772. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2773. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs);
  2774. }
  2775. /*
  2776. * hal_rx_get_tlv(): API to get the tlv
  2777. *
  2778. * @hal_soc: HAL version of the SOC pointer
  2779. * @rx_tlv: TLV data extracted from the rx packet
  2780. * Return: uint8_t
  2781. */
  2782. static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv)
  2783. {
  2784. return hal_soc->ops->hal_rx_get_tlv(rx_tlv);
  2785. }
  2786. /*
  2787. * hal_rx_msdu_start_nss_get(): API to get the NSS
  2788. * Interval from rx_msdu_start
  2789. *
  2790. * @hal_soc: HAL version of the SOC pointer
  2791. * @buf: pointer to the start of RX PKT TLV header
  2792. * Return: uint32_t(nss)
  2793. */
  2794. static inline
  2795. uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2796. {
  2797. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2798. return hal_soc->ops->hal_rx_msdu_start_nss_get(buf);
  2799. }
  2800. /**
  2801. * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured
  2802. * human readable format.
  2803. * @ msdu_start: pointer the msdu_start TLV in pkt.
  2804. * @ dbg_level: log level.
  2805. *
  2806. * Return: void
  2807. */
  2808. static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc,
  2809. struct rx_msdu_start *msdu_start,
  2810. uint8_t dbg_level)
  2811. {
  2812. hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level);
  2813. }
  2814. /**
  2815. * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start
  2816. * info details
  2817. *
  2818. * @ buf - Pointer to buffer containing rx pkt tlvs.
  2819. *
  2820. *
  2821. */
  2822. static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl,
  2823. uint8_t *buf)
  2824. {
  2825. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2826. return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf);
  2827. }
  2828. /*
  2829. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  2830. * Interval from rx_msdu_start
  2831. *
  2832. * @buf: pointer to the start of RX PKT TLV header
  2833. * Return: uint32_t(reception_type)
  2834. */
  2835. static inline
  2836. uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl,
  2837. uint8_t *buf)
  2838. {
  2839. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2840. return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf);
  2841. }
  2842. /**
  2843. * hal_rx_dump_pkt_tlvs: API to print all member elements of
  2844. * RX TLVs
  2845. * @ buf: pointer the pkt buffer.
  2846. * @ dbg_level: log level.
  2847. *
  2848. * Return: void
  2849. */
  2850. static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl,
  2851. uint8_t *buf, uint8_t dbg_level)
  2852. {
  2853. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2854. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  2855. struct rx_mpdu_start *mpdu_start =
  2856. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  2857. struct rx_msdu_start *msdu_start =
  2858. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  2859. struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  2860. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  2861. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2862. hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level);
  2863. hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc);
  2864. hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level);
  2865. hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level);
  2866. hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level);
  2867. hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level);
  2868. }
  2869. /**
  2870. * hal_reo_status_get_header_generic - Process reo desc info
  2871. * @d - Pointer to reo descriptior
  2872. * @b - tlv type info
  2873. * @h - Pointer to hal_reo_status_header where info to be stored
  2874. * @hal- pointer to hal_soc structure
  2875. * Return - none.
  2876. *
  2877. */
  2878. static inline
  2879. void hal_reo_status_get_header(uint32_t *d, int b,
  2880. void *h, struct hal_soc *hal_soc)
  2881. {
  2882. hal_soc->ops->hal_reo_status_get_header(d, b, h);
  2883. }
  2884. /**
  2885. * hal_rx_desc_is_first_msdu() - Check if first msdu
  2886. *
  2887. * @hal_soc_hdl: hal_soc handle
  2888. * @hw_desc_addr: hardware descriptor address
  2889. *
  2890. * Return: 0 - success/ non-zero failure
  2891. */
  2892. static inline
  2893. uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl,
  2894. void *hw_desc_addr)
  2895. {
  2896. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2897. return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr);
  2898. }
  2899. static inline
  2900. uint32_t
  2901. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  2902. struct rx_msdu_start *rx_msdu_start;
  2903. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  2904. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  2905. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  2906. }
  2907. #ifdef NO_RX_PKT_HDR_TLV
  2908. static inline
  2909. uint8_t *
  2910. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  2911. uint8_t *rx_pkt_hdr;
  2912. struct rx_mon_pkt_tlvs *rx_desc =
  2913. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  2914. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  2915. return rx_pkt_hdr;
  2916. }
  2917. #else
  2918. static inline
  2919. uint8_t *
  2920. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  2921. uint8_t *rx_pkt_hdr;
  2922. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  2923. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  2924. return rx_pkt_hdr;
  2925. }
  2926. #endif
  2927. static inline
  2928. bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl,
  2929. uint8_t *rx_tlv_hdr)
  2930. {
  2931. uint8_t decap_format;
  2932. if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) {
  2933. decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr);
  2934. if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW)
  2935. return true;
  2936. }
  2937. return false;
  2938. }
  2939. /**
  2940. * hal_rx_msdu_fse_metadata_get: API to get FSE metadata
  2941. * from rx_msdu_end TLV
  2942. * @buf: pointer to the start of RX PKT TLV headers
  2943. *
  2944. * Return: fse metadata value from MSDU END TLV
  2945. */
  2946. static inline uint32_t
  2947. hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl,
  2948. uint8_t *buf)
  2949. {
  2950. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2951. return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf);
  2952. }
  2953. /**
  2954. * hal_rx_msdu_flow_idx_get: API to get flow index
  2955. * from rx_msdu_end TLV
  2956. * @buf: pointer to the start of RX PKT TLV headers
  2957. *
  2958. * Return: flow index value from MSDU END TLV
  2959. */
  2960. static inline uint32_t
  2961. hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl,
  2962. uint8_t *buf)
  2963. {
  2964. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2965. return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf);
  2966. }
  2967. /**
  2968. * hal_rx_msdu_get_reo_destination_indication: API to get reo
  2969. * destination index from rx_msdu_end TLV
  2970. * @buf: pointer to the start of RX PKT TLV headers
  2971. * @reo_destination_indication: pointer to return value of
  2972. * reo_destination_indication
  2973. *
  2974. * Return: reo_destination_indication value from MSDU END TLV
  2975. */
  2976. static inline void
  2977. hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl,
  2978. uint8_t *buf,
  2979. uint32_t *reo_destination_indication)
  2980. {
  2981. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2982. if ((!hal_soc) || (!hal_soc->ops)) {
  2983. hal_err("hal handle is NULL");
  2984. QDF_BUG(0);
  2985. return;
  2986. }
  2987. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf,
  2988. reo_destination_indication);
  2989. }
  2990. /**
  2991. * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout
  2992. * from rx_msdu_end TLV
  2993. * @buf: pointer to the start of RX PKT TLV headers
  2994. *
  2995. * Return: flow index timeout value from MSDU END TLV
  2996. */
  2997. static inline bool
  2998. hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl,
  2999. uint8_t *buf)
  3000. {
  3001. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3002. return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf);
  3003. }
  3004. /**
  3005. * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid
  3006. * from rx_msdu_end TLV
  3007. * @buf: pointer to the start of RX PKT TLV headers
  3008. *
  3009. * Return: flow index invalid value from MSDU END TLV
  3010. */
  3011. static inline bool
  3012. hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl,
  3013. uint8_t *buf)
  3014. {
  3015. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3016. return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf);
  3017. }
  3018. /**
  3019. * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id
  3020. * @hal_soc_hdl: hal_soc handle
  3021. * @rx_tlv_hdr: Rx_tlv_hdr
  3022. * @rxdma_dst_ring_desc: Rx HW descriptor
  3023. *
  3024. * Return: ppdu id
  3025. */
  3026. static inline
  3027. uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl,
  3028. void *rx_tlv_hdr,
  3029. void *rxdma_dst_ring_desc)
  3030. {
  3031. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3032. return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr,
  3033. rxdma_dst_ring_desc);
  3034. }
  3035. /**
  3036. * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id
  3037. * @hal_soc_hdl: hal_soc handle
  3038. * @buf: rx tlv address
  3039. *
  3040. * Return: sw peer id
  3041. */
  3042. static inline
  3043. uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  3044. uint8_t *buf)
  3045. {
  3046. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3047. if ((!hal_soc) || (!hal_soc->ops)) {
  3048. hal_err("hal handle is NULL");
  3049. QDF_BUG(0);
  3050. return QDF_STATUS_E_INVAL;
  3051. }
  3052. if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get)
  3053. return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf);
  3054. return QDF_STATUS_E_INVAL;
  3055. }
  3056. static inline
  3057. void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl,
  3058. void *link_desc_addr)
  3059. {
  3060. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3061. return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr);
  3062. }
  3063. static inline
  3064. void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl,
  3065. void *msdu_addr)
  3066. {
  3067. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3068. return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr);
  3069. }
  3070. static inline
  3071. void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  3072. void *hw_addr)
  3073. {
  3074. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3075. return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr);
  3076. }
  3077. static inline
  3078. void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  3079. void *hw_addr)
  3080. {
  3081. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3082. return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr);
  3083. }
  3084. static inline
  3085. uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl,
  3086. uint8_t *buf)
  3087. {
  3088. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3089. return hal_soc->ops->hal_rx_get_fc_valid(buf);
  3090. }
  3091. static inline
  3092. uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  3093. {
  3094. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3095. return hal_soc->ops->hal_rx_get_to_ds_flag(buf);
  3096. }
  3097. static inline
  3098. uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl,
  3099. uint8_t *buf)
  3100. {
  3101. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3102. return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf);
  3103. }
  3104. static inline
  3105. uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl,
  3106. uint8_t *buf)
  3107. {
  3108. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3109. return hal_soc->ops->hal_rx_get_filter_category(buf);
  3110. }
  3111. static inline
  3112. uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl,
  3113. uint8_t *buf)
  3114. {
  3115. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3116. return hal_soc->ops->hal_rx_get_ppdu_id(buf);
  3117. }
  3118. /**
  3119. * hal_reo_config(): Set reo config parameters
  3120. * @soc: hal soc handle
  3121. * @reg_val: value to be set
  3122. * @reo_params: reo parameters
  3123. *
  3124. * Return: void
  3125. */
  3126. static inline
  3127. void hal_reo_config(struct hal_soc *hal_soc,
  3128. uint32_t reg_val,
  3129. struct hal_reo_params *reo_params)
  3130. {
  3131. hal_soc->ops->hal_reo_config(hal_soc,
  3132. reg_val,
  3133. reo_params);
  3134. }
  3135. /**
  3136. * hal_rx_msdu_get_flow_params: API to get flow index,
  3137. * flow index invalid and flow index timeout from rx_msdu_end TLV
  3138. * @buf: pointer to the start of RX PKT TLV headers
  3139. * @flow_invalid: pointer to return value of flow_idx_valid
  3140. * @flow_timeout: pointer to return value of flow_idx_timeout
  3141. * @flow_index: pointer to return value of flow_idx
  3142. *
  3143. * Return: none
  3144. */
  3145. static inline void
  3146. hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl,
  3147. uint8_t *buf,
  3148. bool *flow_invalid,
  3149. bool *flow_timeout,
  3150. uint32_t *flow_index)
  3151. {
  3152. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3153. if ((!hal_soc) || (!hal_soc->ops)) {
  3154. hal_err("hal handle is NULL");
  3155. QDF_BUG(0);
  3156. return;
  3157. }
  3158. if (hal_soc->ops->hal_rx_msdu_get_flow_params)
  3159. hal_soc->ops->
  3160. hal_rx_msdu_get_flow_params(buf,
  3161. flow_invalid,
  3162. flow_timeout,
  3163. flow_index);
  3164. }
  3165. static inline
  3166. uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl,
  3167. uint8_t *buf)
  3168. {
  3169. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3170. return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf);
  3171. }
  3172. static inline
  3173. uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl,
  3174. uint8_t *buf)
  3175. {
  3176. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3177. return hal_soc->ops->hal_rx_get_rx_sequence(buf);
  3178. }
  3179. static inline void
  3180. hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl,
  3181. void *rx_tlv,
  3182. void *ppdu_info)
  3183. {
  3184. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3185. if (hal_soc->ops->hal_rx_get_bb_info)
  3186. hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info);
  3187. }
  3188. static inline void
  3189. hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl,
  3190. void *rx_tlv,
  3191. void *ppdu_info)
  3192. {
  3193. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3194. if (hal_soc->ops->hal_rx_get_rtt_info)
  3195. hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info);
  3196. }
  3197. /**
  3198. * hal_rx_msdu_metadata_get(): API to get the
  3199. * fast path information from rx_msdu_end TLV
  3200. *
  3201. * @ hal_soc_hdl: DP soc handle
  3202. * @ buf: pointer to the start of RX PKT TLV headers
  3203. * @ msdu_metadata: Structure to hold msdu end information
  3204. * Return: none
  3205. */
  3206. static inline void
  3207. hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  3208. struct hal_rx_msdu_metadata *msdu_md)
  3209. {
  3210. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3211. return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md);
  3212. }
  3213. /**
  3214. * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum
  3215. * from rx_msdu_end TLV
  3216. * @buf: pointer to the start of RX PKT TLV headers
  3217. *
  3218. * Return: cumulative_l4_checksum
  3219. */
  3220. static inline uint16_t
  3221. hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl,
  3222. uint8_t *buf)
  3223. {
  3224. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3225. if (!hal_soc || !hal_soc->ops) {
  3226. hal_err("hal handle is NULL");
  3227. QDF_BUG(0);
  3228. return 0;
  3229. }
  3230. if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum)
  3231. return 0;
  3232. return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf);
  3233. }
  3234. /**
  3235. * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length
  3236. * from rx_msdu_end TLV
  3237. * @buf: pointer to the start of RX PKT TLV headers
  3238. *
  3239. * Return: cumulative_ip_length
  3240. */
  3241. static inline uint16_t
  3242. hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl,
  3243. uint8_t *buf)
  3244. {
  3245. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3246. if (!hal_soc || !hal_soc->ops) {
  3247. hal_err("hal handle is NULL");
  3248. QDF_BUG(0);
  3249. return 0;
  3250. }
  3251. if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length)
  3252. return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf);
  3253. return 0;
  3254. }
  3255. /**
  3256. * hal_rx_get_udp_proto: API to get UDP proto field
  3257. * from rx_msdu_start TLV
  3258. * @buf: pointer to the start of RX PKT TLV headers
  3259. *
  3260. * Return: UDP proto field value
  3261. */
  3262. static inline bool
  3263. hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  3264. {
  3265. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3266. if (!hal_soc || !hal_soc->ops) {
  3267. hal_err("hal handle is NULL");
  3268. QDF_BUG(0);
  3269. return 0;
  3270. }
  3271. if (hal_soc->ops->hal_rx_get_udp_proto)
  3272. return hal_soc->ops->hal_rx_get_udp_proto(buf);
  3273. return 0;
  3274. }
  3275. /**
  3276. * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation
  3277. * from rx_msdu_end TLV
  3278. * @buf: pointer to the start of RX PKT TLV headers
  3279. *
  3280. * Return: flow_agg_continuation bit field value
  3281. */
  3282. static inline bool
  3283. hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl,
  3284. uint8_t *buf)
  3285. {
  3286. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3287. if (!hal_soc || !hal_soc->ops) {
  3288. hal_err("hal handle is NULL");
  3289. QDF_BUG(0);
  3290. return 0;
  3291. }
  3292. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation)
  3293. return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf);
  3294. return 0;
  3295. }
  3296. /**
  3297. * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from
  3298. * rx_msdu_end TLV
  3299. * @buf: pointer to the start of RX PKT TLV headers
  3300. *
  3301. * Return: flow_agg count value
  3302. */
  3303. static inline uint8_t
  3304. hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl,
  3305. uint8_t *buf)
  3306. {
  3307. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3308. if (!hal_soc || !hal_soc->ops) {
  3309. hal_err("hal handle is NULL");
  3310. QDF_BUG(0);
  3311. return 0;
  3312. }
  3313. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count)
  3314. return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf);
  3315. return 0;
  3316. }
  3317. /**
  3318. * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV
  3319. * @buf: pointer to the start of RX PKT TLV headers
  3320. *
  3321. * Return: fisa flow_agg timeout bit value
  3322. */
  3323. static inline bool
  3324. hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  3325. {
  3326. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3327. if (!hal_soc || !hal_soc->ops) {
  3328. hal_err("hal handle is NULL");
  3329. QDF_BUG(0);
  3330. return 0;
  3331. }
  3332. if (hal_soc->ops->hal_rx_get_fisa_timeout)
  3333. return hal_soc->ops->hal_rx_get_fisa_timeout(buf);
  3334. return 0;
  3335. }
  3336. /**
  3337. * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv
  3338. * tag is valid
  3339. *
  3340. * @hal_soc_hdl: HAL SOC handle
  3341. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  3342. *
  3343. * Return: true if RX_MPDU_START tlv tag is valid, else false
  3344. */
  3345. static inline uint8_t
  3346. hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl,
  3347. void *rx_tlv_hdr)
  3348. {
  3349. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3350. if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid)
  3351. return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr);
  3352. return 0;
  3353. }
  3354. /**
  3355. * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from
  3356. * <struct buffer_addr_info> structure
  3357. * @buf_addr_info: pointer to <struct buffer_addr_info> structure
  3358. * @buf_info: structure to return the buffer information including
  3359. * paddr/cookie
  3360. *
  3361. * return: None
  3362. */
  3363. static inline
  3364. void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info,
  3365. struct hal_buf_info *buf_info)
  3366. {
  3367. buf_info->paddr =
  3368. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  3369. ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  3370. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  3371. }
  3372. /**
  3373. * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc
  3374. * buffer addr info
  3375. * @link_desc_va: pointer to current msdu link Desc
  3376. * @next_addr_info: buffer to save next msdu link Desc buffer addr info
  3377. *
  3378. * return: None
  3379. */
  3380. static inline
  3381. void hal_rx_get_next_msdu_link_desc_buf_addr_info(
  3382. void *link_desc_va,
  3383. struct buffer_addr_info *next_addr_info)
  3384. {
  3385. struct rx_msdu_link *msdu_link = link_desc_va;
  3386. if (!msdu_link) {
  3387. qdf_mem_zero(next_addr_info,
  3388. sizeof(struct buffer_addr_info));
  3389. return;
  3390. }
  3391. *next_addr_info = msdu_link->next_msdu_link_desc_addr_info;
  3392. }
  3393. /**
  3394. * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc
  3395. * buffer addr info
  3396. * @link_desc_va: pointer to current msdu link Desc
  3397. *
  3398. * return: None
  3399. */
  3400. static inline
  3401. void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va)
  3402. {
  3403. struct rx_msdu_link *msdu_link = link_desc_va;
  3404. if (msdu_link)
  3405. qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info,
  3406. sizeof(msdu_link->next_msdu_link_desc_addr_info));
  3407. }
  3408. /**
  3409. * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid
  3410. *
  3411. * @buf_addr_info: pointer to buf_addr_info structure
  3412. *
  3413. * return: true: has valid paddr, false: not.
  3414. */
  3415. static inline
  3416. bool hal_rx_is_buf_addr_info_valid(
  3417. struct buffer_addr_info *buf_addr_info)
  3418. {
  3419. return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ?
  3420. false : true;
  3421. }
  3422. /**
  3423. * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from
  3424. * rx_pkt_tlvs structure
  3425. *
  3426. * @hal_soc_hdl: HAL SOC handle
  3427. * return: msdu_end_tlv offset value
  3428. */
  3429. static inline
  3430. uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  3431. {
  3432. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3433. if (!hal_soc || !hal_soc->ops) {
  3434. hal_err("hal handle is NULL");
  3435. QDF_BUG(0);
  3436. return 0;
  3437. }
  3438. return hal_soc->ops->hal_rx_msdu_end_offset_get();
  3439. }
  3440. /**
  3441. * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from
  3442. * rx_pkt_tlvs structure
  3443. *
  3444. * @hal_soc_hdl: HAL SOC handle
  3445. * return: msdu_start_tlv offset value
  3446. */
  3447. static inline
  3448. uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  3449. {
  3450. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3451. if (!hal_soc || !hal_soc->ops) {
  3452. hal_err("hal handle is NULL");
  3453. QDF_BUG(0);
  3454. return 0;
  3455. }
  3456. return hal_soc->ops->hal_rx_msdu_start_offset_get();
  3457. }
  3458. /**
  3459. * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from
  3460. * rx_pkt_tlvs structure
  3461. *
  3462. * @hal_soc_hdl: HAL SOC handle
  3463. * return: mpdu_start_tlv offset value
  3464. */
  3465. static inline
  3466. uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  3467. {
  3468. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3469. if (!hal_soc || !hal_soc->ops) {
  3470. hal_err("hal handle is NULL");
  3471. QDF_BUG(0);
  3472. return 0;
  3473. }
  3474. return hal_soc->ops->hal_rx_mpdu_start_offset_get();
  3475. }
  3476. /**
  3477. * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from
  3478. * rx_pkt_tlvs structure
  3479. *
  3480. * @hal_soc_hdl: HAL SOC handle
  3481. * return: mpdu_end_tlv offset value
  3482. */
  3483. static inline
  3484. uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  3485. {
  3486. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3487. if (!hal_soc || !hal_soc->ops) {
  3488. hal_err("hal handle is NULL");
  3489. QDF_BUG(0);
  3490. return 0;
  3491. }
  3492. return hal_soc->ops->hal_rx_mpdu_end_offset_get();
  3493. }
  3494. /**
  3495. * hal_rx_attn_offset_get(): Get the ATTENTION offset from
  3496. * rx_pkt_tlvs structure
  3497. *
  3498. * @hal_soc_hdl: HAL SOC handle
  3499. * return: attn_tlv offset value
  3500. */
  3501. static inline
  3502. uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl)
  3503. {
  3504. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3505. if (!hal_soc || !hal_soc->ops) {
  3506. hal_err("hal handle is NULL");
  3507. QDF_BUG(0);
  3508. return 0;
  3509. }
  3510. return hal_soc->ops->hal_rx_attn_offset_get();
  3511. }
  3512. #endif /* _HAL_RX_H */