dp_tx.c 139 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  71. /**
  72. * dp_update_tx_desc_stats - Update the increase or decrease in
  73. * outstanding tx desc count
  74. * values on pdev and soc
  75. * @vdev: DP pdev handle
  76. *
  77. * Return: void
  78. */
  79. static inline void
  80. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  81. {
  82. int32_t tx_descs_cnt =
  83. qdf_atomic_read(&pdev->num_tx_outstanding);
  84. if (pdev->tx_descs_max < tx_descs_cnt)
  85. pdev->tx_descs_max = tx_descs_cnt;
  86. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  87. pdev->tx_descs_max);
  88. }
  89. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  90. static inline void
  91. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  92. {
  93. }
  94. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  95. #ifdef QCA_TX_LIMIT_CHECK
  96. /**
  97. * dp_tx_limit_check - Check if allocated tx descriptors reached
  98. * soc max limit and pdev max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  110. soc->num_tx_allowed) {
  111. dp_tx_info("queued packets are more than max tx, drop the frame");
  112. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  113. return true;
  114. }
  115. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  116. pdev->num_tx_allowed) {
  117. dp_tx_info("queued packets are more than max tx, drop the frame");
  118. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  119. return true;
  120. }
  121. return false;
  122. }
  123. /**
  124. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  125. * reached soc max limit
  126. * @vdev: DP vdev handle
  127. *
  128. * Return: true if allocated tx descriptors reached max configured value, else
  129. * false
  130. */
  131. static inline bool
  132. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  133. {
  134. struct dp_pdev *pdev = vdev->pdev;
  135. struct dp_soc *soc = pdev->soc;
  136. if (qdf_atomic_read(&soc->num_tx_exception) >=
  137. soc->num_msdu_exception_desc) {
  138. dp_info("exc packets are more than max drop the exc pkt");
  139. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  140. return true;
  141. }
  142. return false;
  143. }
  144. /**
  145. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  146. * @vdev: DP pdev handle
  147. *
  148. * Return: void
  149. */
  150. static inline void
  151. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  152. {
  153. struct dp_soc *soc = pdev->soc;
  154. qdf_atomic_inc(&pdev->num_tx_outstanding);
  155. qdf_atomic_inc(&soc->num_tx_outstanding);
  156. dp_update_tx_desc_stats(pdev);
  157. }
  158. /**
  159. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  160. * @vdev: DP pdev handle
  161. *
  162. * Return: void
  163. */
  164. static inline void
  165. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  166. {
  167. struct dp_soc *soc = pdev->soc;
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. qdf_atomic_dec(&soc->num_tx_outstanding);
  170. dp_update_tx_desc_stats(pdev);
  171. }
  172. #else //QCA_TX_LIMIT_CHECK
  173. static inline bool
  174. dp_tx_limit_check(struct dp_vdev *vdev)
  175. {
  176. return false;
  177. }
  178. static inline bool
  179. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  180. {
  181. return false;
  182. }
  183. static inline void
  184. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  185. {
  186. qdf_atomic_inc(&pdev->num_tx_outstanding);
  187. dp_update_tx_desc_stats(pdev);
  188. }
  189. static inline void
  190. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  191. {
  192. qdf_atomic_dec(&pdev->num_tx_outstanding);
  193. dp_update_tx_desc_stats(pdev);
  194. }
  195. #endif //QCA_TX_LIMIT_CHECK
  196. #if defined(FEATURE_TSO)
  197. /**
  198. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  199. *
  200. * @soc - core txrx main context
  201. * @seg_desc - tso segment descriptor
  202. * @num_seg_desc - tso number segment descriptor
  203. */
  204. static void dp_tx_tso_unmap_segment(
  205. struct dp_soc *soc,
  206. struct qdf_tso_seg_elem_t *seg_desc,
  207. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  208. {
  209. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  210. if (qdf_unlikely(!seg_desc)) {
  211. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  212. __func__, __LINE__);
  213. qdf_assert(0);
  214. } else if (qdf_unlikely(!num_seg_desc)) {
  215. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  216. __func__, __LINE__);
  217. qdf_assert(0);
  218. } else {
  219. bool is_last_seg;
  220. /* no tso segment left to do dma unmap */
  221. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  222. return;
  223. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  224. true : false;
  225. qdf_nbuf_unmap_tso_segment(soc->osdev,
  226. seg_desc, is_last_seg);
  227. num_seg_desc->num_seg.tso_cmn_num_seg--;
  228. }
  229. }
  230. /**
  231. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  232. * back to the freelist
  233. *
  234. * @soc - soc device handle
  235. * @tx_desc - Tx software descriptor
  236. */
  237. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  238. struct dp_tx_desc_s *tx_desc)
  239. {
  240. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  241. if (qdf_unlikely(!tx_desc->tso_desc)) {
  242. dp_tx_err("SO desc is NULL!");
  243. qdf_assert(0);
  244. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  245. dp_tx_err("TSO num desc is NULL!");
  246. qdf_assert(0);
  247. } else {
  248. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  249. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  250. /* Add the tso num segment into the free list */
  251. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  252. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  253. tx_desc->tso_num_desc);
  254. tx_desc->tso_num_desc = NULL;
  255. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  256. }
  257. /* Add the tso segment into the free list*/
  258. dp_tx_tso_desc_free(soc,
  259. tx_desc->pool_id, tx_desc->tso_desc);
  260. tx_desc->tso_desc = NULL;
  261. }
  262. }
  263. #else
  264. static void dp_tx_tso_unmap_segment(
  265. struct dp_soc *soc,
  266. struct qdf_tso_seg_elem_t *seg_desc,
  267. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  268. {
  269. }
  270. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  271. struct dp_tx_desc_s *tx_desc)
  272. {
  273. }
  274. #endif
  275. /**
  276. * dp_tx_desc_release() - Release Tx Descriptor
  277. * @tx_desc : Tx Descriptor
  278. * @desc_pool_id: Descriptor Pool ID
  279. *
  280. * Deallocate all resources attached to Tx descriptor and free the Tx
  281. * descriptor.
  282. *
  283. * Return:
  284. */
  285. static void
  286. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  287. {
  288. struct dp_pdev *pdev = tx_desc->pdev;
  289. struct dp_soc *soc;
  290. uint8_t comp_status = 0;
  291. qdf_assert(pdev);
  292. soc = pdev->soc;
  293. dp_tx_outstanding_dec(pdev);
  294. if (tx_desc->frm_type == dp_tx_frm_tso)
  295. dp_tx_tso_desc_release(soc, tx_desc);
  296. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  297. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  298. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  299. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  300. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  301. qdf_atomic_dec(&soc->num_tx_exception);
  302. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  303. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  304. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  305. soc->hal_soc);
  306. else
  307. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  308. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  309. tx_desc->id, comp_status,
  310. qdf_atomic_read(&pdev->num_tx_outstanding));
  311. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  312. return;
  313. }
  314. /**
  315. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  316. * @vdev: DP vdev Handle
  317. * @nbuf: skb
  318. * @msdu_info: msdu_info required to create HTT metadata
  319. *
  320. * Prepares and fills HTT metadata in the frame pre-header for special frames
  321. * that should be transmitted using varying transmit parameters.
  322. * There are 2 VDEV modes that currently needs this special metadata -
  323. * 1) Mesh Mode
  324. * 2) DSRC Mode
  325. *
  326. * Return: HTT metadata size
  327. *
  328. */
  329. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  330. struct dp_tx_msdu_info_s *msdu_info)
  331. {
  332. uint32_t *meta_data = msdu_info->meta_data;
  333. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  334. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  335. uint8_t htt_desc_size;
  336. /* Size rounded of multiple of 8 bytes */
  337. uint8_t htt_desc_size_aligned;
  338. uint8_t *hdr = NULL;
  339. /*
  340. * Metadata - HTT MSDU Extension header
  341. */
  342. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  343. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  344. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  345. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  346. meta_data[0])) {
  347. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  348. htt_desc_size_aligned)) {
  349. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  350. htt_desc_size_aligned);
  351. if (!nbuf) {
  352. /*
  353. * qdf_nbuf_realloc_headroom won't do skb_clone
  354. * as skb_realloc_headroom does. so, no free is
  355. * needed here.
  356. */
  357. DP_STATS_INC(vdev,
  358. tx_i.dropped.headroom_insufficient,
  359. 1);
  360. qdf_print(" %s[%d] skb_realloc_headroom failed",
  361. __func__, __LINE__);
  362. return 0;
  363. }
  364. }
  365. /* Fill and add HTT metaheader */
  366. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  367. if (!hdr) {
  368. dp_tx_err("Error in filling HTT metadata");
  369. return 0;
  370. }
  371. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  372. } else if (vdev->opmode == wlan_op_mode_ocb) {
  373. /* Todo - Add support for DSRC */
  374. }
  375. return htt_desc_size_aligned;
  376. }
  377. /**
  378. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  379. * @tso_seg: TSO segment to process
  380. * @ext_desc: Pointer to MSDU extension descriptor
  381. *
  382. * Return: void
  383. */
  384. #if defined(FEATURE_TSO)
  385. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  386. void *ext_desc)
  387. {
  388. uint8_t num_frag;
  389. uint32_t tso_flags;
  390. /*
  391. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  392. * tcp_flag_mask
  393. *
  394. * Checksum enable flags are set in TCL descriptor and not in Extension
  395. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  396. */
  397. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  398. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  399. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  400. tso_seg->tso_flags.ip_len);
  401. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  402. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  403. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  404. uint32_t lo = 0;
  405. uint32_t hi = 0;
  406. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  407. (tso_seg->tso_frags[num_frag].length));
  408. qdf_dmaaddr_to_32s(
  409. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  410. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  411. tso_seg->tso_frags[num_frag].length);
  412. }
  413. return;
  414. }
  415. #else
  416. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  417. void *ext_desc)
  418. {
  419. return;
  420. }
  421. #endif
  422. #if defined(FEATURE_TSO)
  423. /**
  424. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  425. * allocated and free them
  426. *
  427. * @soc: soc handle
  428. * @free_seg: list of tso segments
  429. * @msdu_info: msdu descriptor
  430. *
  431. * Return - void
  432. */
  433. static void dp_tx_free_tso_seg_list(
  434. struct dp_soc *soc,
  435. struct qdf_tso_seg_elem_t *free_seg,
  436. struct dp_tx_msdu_info_s *msdu_info)
  437. {
  438. struct qdf_tso_seg_elem_t *next_seg;
  439. while (free_seg) {
  440. next_seg = free_seg->next;
  441. dp_tx_tso_desc_free(soc,
  442. msdu_info->tx_queue.desc_pool_id,
  443. free_seg);
  444. free_seg = next_seg;
  445. }
  446. }
  447. /**
  448. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  449. * allocated and free them
  450. *
  451. * @soc: soc handle
  452. * @free_num_seg: list of tso number segments
  453. * @msdu_info: msdu descriptor
  454. * Return - void
  455. */
  456. static void dp_tx_free_tso_num_seg_list(
  457. struct dp_soc *soc,
  458. struct qdf_tso_num_seg_elem_t *free_num_seg,
  459. struct dp_tx_msdu_info_s *msdu_info)
  460. {
  461. struct qdf_tso_num_seg_elem_t *next_num_seg;
  462. while (free_num_seg) {
  463. next_num_seg = free_num_seg->next;
  464. dp_tso_num_seg_free(soc,
  465. msdu_info->tx_queue.desc_pool_id,
  466. free_num_seg);
  467. free_num_seg = next_num_seg;
  468. }
  469. }
  470. /**
  471. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  472. * do dma unmap for each segment
  473. *
  474. * @soc: soc handle
  475. * @free_seg: list of tso segments
  476. * @num_seg_desc: tso number segment descriptor
  477. *
  478. * Return - void
  479. */
  480. static void dp_tx_unmap_tso_seg_list(
  481. struct dp_soc *soc,
  482. struct qdf_tso_seg_elem_t *free_seg,
  483. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  484. {
  485. struct qdf_tso_seg_elem_t *next_seg;
  486. if (qdf_unlikely(!num_seg_desc)) {
  487. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  488. return;
  489. }
  490. while (free_seg) {
  491. next_seg = free_seg->next;
  492. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  493. free_seg = next_seg;
  494. }
  495. }
  496. #ifdef FEATURE_TSO_STATS
  497. /**
  498. * dp_tso_get_stats_idx: Retrieve the tso packet id
  499. * @pdev - pdev handle
  500. *
  501. * Return: id
  502. */
  503. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  504. {
  505. uint32_t stats_idx;
  506. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  507. % CDP_MAX_TSO_PACKETS);
  508. return stats_idx;
  509. }
  510. #else
  511. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  512. {
  513. return 0;
  514. }
  515. #endif /* FEATURE_TSO_STATS */
  516. /**
  517. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  518. * free the tso segments descriptor and
  519. * tso num segments descriptor
  520. *
  521. * @soc: soc handle
  522. * @msdu_info: msdu descriptor
  523. * @tso_seg_unmap: flag to show if dma unmap is necessary
  524. *
  525. * Return - void
  526. */
  527. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  528. struct dp_tx_msdu_info_s *msdu_info,
  529. bool tso_seg_unmap)
  530. {
  531. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  532. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  533. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  534. tso_info->tso_num_seg_list;
  535. /* do dma unmap for each segment */
  536. if (tso_seg_unmap)
  537. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  538. /* free all tso number segment descriptor though looks only have 1 */
  539. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  540. /* free all tso segment descriptor */
  541. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  542. }
  543. /**
  544. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  545. * @vdev: virtual device handle
  546. * @msdu: network buffer
  547. * @msdu_info: meta data associated with the msdu
  548. *
  549. * Return: QDF_STATUS_SUCCESS success
  550. */
  551. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  552. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  553. {
  554. struct qdf_tso_seg_elem_t *tso_seg;
  555. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  556. struct dp_soc *soc = vdev->pdev->soc;
  557. struct dp_pdev *pdev = vdev->pdev;
  558. struct qdf_tso_info_t *tso_info;
  559. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  560. tso_info = &msdu_info->u.tso_info;
  561. tso_info->curr_seg = NULL;
  562. tso_info->tso_seg_list = NULL;
  563. tso_info->num_segs = num_seg;
  564. msdu_info->frm_type = dp_tx_frm_tso;
  565. tso_info->tso_num_seg_list = NULL;
  566. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  567. while (num_seg) {
  568. tso_seg = dp_tx_tso_desc_alloc(
  569. soc, msdu_info->tx_queue.desc_pool_id);
  570. if (tso_seg) {
  571. tso_seg->next = tso_info->tso_seg_list;
  572. tso_info->tso_seg_list = tso_seg;
  573. num_seg--;
  574. } else {
  575. dp_err_rl("Failed to alloc tso seg desc");
  576. DP_STATS_INC_PKT(vdev->pdev,
  577. tso_stats.tso_no_mem_dropped, 1,
  578. qdf_nbuf_len(msdu));
  579. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  580. return QDF_STATUS_E_NOMEM;
  581. }
  582. }
  583. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  584. tso_num_seg = dp_tso_num_seg_alloc(soc,
  585. msdu_info->tx_queue.desc_pool_id);
  586. if (tso_num_seg) {
  587. tso_num_seg->next = tso_info->tso_num_seg_list;
  588. tso_info->tso_num_seg_list = tso_num_seg;
  589. } else {
  590. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  591. __func__);
  592. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  593. return QDF_STATUS_E_NOMEM;
  594. }
  595. msdu_info->num_seg =
  596. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  597. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  598. msdu_info->num_seg);
  599. if (!(msdu_info->num_seg)) {
  600. /*
  601. * Free allocated TSO seg desc and number seg desc,
  602. * do unmap for segments if dma map has done.
  603. */
  604. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  605. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  606. return QDF_STATUS_E_INVAL;
  607. }
  608. tso_info->curr_seg = tso_info->tso_seg_list;
  609. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  610. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  611. msdu, msdu_info->num_seg);
  612. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  613. tso_info->msdu_stats_idx);
  614. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  615. return QDF_STATUS_SUCCESS;
  616. }
  617. #else
  618. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  619. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  620. {
  621. return QDF_STATUS_E_NOMEM;
  622. }
  623. #endif
  624. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  625. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  626. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  627. /**
  628. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  629. * @vdev: DP Vdev handle
  630. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  631. * @desc_pool_id: Descriptor Pool ID
  632. *
  633. * Return:
  634. */
  635. static
  636. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  637. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  638. {
  639. uint8_t i;
  640. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  641. struct dp_tx_seg_info_s *seg_info;
  642. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  643. struct dp_soc *soc = vdev->pdev->soc;
  644. /* Allocate an extension descriptor */
  645. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  646. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  647. if (!msdu_ext_desc) {
  648. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  649. return NULL;
  650. }
  651. if (msdu_info->exception_fw &&
  652. qdf_unlikely(vdev->mesh_vdev)) {
  653. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  654. &msdu_info->meta_data[0],
  655. sizeof(struct htt_tx_msdu_desc_ext2_t));
  656. qdf_atomic_inc(&soc->num_tx_exception);
  657. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  658. }
  659. switch (msdu_info->frm_type) {
  660. case dp_tx_frm_sg:
  661. case dp_tx_frm_me:
  662. case dp_tx_frm_raw:
  663. seg_info = msdu_info->u.sg_info.curr_seg;
  664. /* Update the buffer pointers in MSDU Extension Descriptor */
  665. for (i = 0; i < seg_info->frag_cnt; i++) {
  666. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  667. seg_info->frags[i].paddr_lo,
  668. seg_info->frags[i].paddr_hi,
  669. seg_info->frags[i].len);
  670. }
  671. break;
  672. case dp_tx_frm_tso:
  673. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  674. &cached_ext_desc[0]);
  675. break;
  676. default:
  677. break;
  678. }
  679. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  680. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  681. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  682. msdu_ext_desc->vaddr);
  683. return msdu_ext_desc;
  684. }
  685. /**
  686. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  687. *
  688. * @skb: skb to be traced
  689. * @msdu_id: msdu_id of the packet
  690. * @vdev_id: vdev_id of the packet
  691. *
  692. * Return: None
  693. */
  694. #ifdef DP_DISABLE_TX_PKT_TRACE
  695. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  696. uint8_t vdev_id)
  697. {
  698. }
  699. #else
  700. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  701. uint8_t vdev_id)
  702. {
  703. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  704. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  705. DPTRACE(qdf_dp_trace_ptr(skb,
  706. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  707. QDF_TRACE_DEFAULT_PDEV_ID,
  708. qdf_nbuf_data_addr(skb),
  709. sizeof(qdf_nbuf_data(skb)),
  710. msdu_id, vdev_id, 0));
  711. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  712. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  713. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  714. msdu_id, QDF_TX));
  715. }
  716. #endif
  717. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  718. /**
  719. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  720. * exception by the upper layer (OS_IF)
  721. * @soc: DP soc handle
  722. * @nbuf: packet to be transmitted
  723. *
  724. * Returns: 1 if the packet is marked as exception,
  725. * 0, if the packet is not marked as exception.
  726. */
  727. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  728. qdf_nbuf_t nbuf)
  729. {
  730. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  731. }
  732. #else
  733. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  734. qdf_nbuf_t nbuf)
  735. {
  736. return 0;
  737. }
  738. #endif
  739. /**
  740. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  741. * @vdev: DP vdev handle
  742. * @nbuf: skb
  743. * @desc_pool_id: Descriptor pool ID
  744. * @meta_data: Metadata to the fw
  745. * @tx_exc_metadata: Handle that holds exception path metadata
  746. * Allocate and prepare Tx descriptor with msdu information.
  747. *
  748. * Return: Pointer to Tx Descriptor on success,
  749. * NULL on failure
  750. */
  751. static
  752. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  753. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  754. struct dp_tx_msdu_info_s *msdu_info,
  755. struct cdp_tx_exception_metadata *tx_exc_metadata)
  756. {
  757. uint8_t align_pad;
  758. uint8_t is_exception = 0;
  759. uint8_t htt_hdr_size;
  760. struct dp_tx_desc_s *tx_desc;
  761. struct dp_pdev *pdev = vdev->pdev;
  762. struct dp_soc *soc = pdev->soc;
  763. if (dp_tx_limit_check(vdev))
  764. return NULL;
  765. /* Allocate software Tx descriptor */
  766. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  767. if (qdf_unlikely(!tx_desc)) {
  768. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  769. return NULL;
  770. }
  771. dp_tx_outstanding_inc(pdev);
  772. /* Initialize the SW tx descriptor */
  773. tx_desc->nbuf = nbuf;
  774. tx_desc->frm_type = dp_tx_frm_std;
  775. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  776. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  777. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  778. tx_desc->vdev_id = vdev->vdev_id;
  779. tx_desc->pdev = pdev;
  780. tx_desc->msdu_ext_desc = NULL;
  781. tx_desc->pkt_offset = 0;
  782. tx_desc->length = qdf_nbuf_headlen(nbuf);
  783. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  784. if (qdf_unlikely(vdev->multipass_en)) {
  785. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  786. goto failure;
  787. }
  788. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  789. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  790. is_exception = 1;
  791. /*
  792. * For special modes (vdev_type == ocb or mesh), data frames should be
  793. * transmitted using varying transmit parameters (tx spec) which include
  794. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  795. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  796. * These frames are sent as exception packets to firmware.
  797. *
  798. * HW requirement is that metadata should always point to a
  799. * 8-byte aligned address. So we add alignment pad to start of buffer.
  800. * HTT Metadata should be ensured to be multiple of 8-bytes,
  801. * to get 8-byte aligned start address along with align_pad added
  802. *
  803. * |-----------------------------|
  804. * | |
  805. * |-----------------------------| <-----Buffer Pointer Address given
  806. * | | ^ in HW descriptor (aligned)
  807. * | HTT Metadata | |
  808. * | | |
  809. * | | | Packet Offset given in descriptor
  810. * | | |
  811. * |-----------------------------| |
  812. * | Alignment Pad | v
  813. * |-----------------------------| <----- Actual buffer start address
  814. * | SKB Data | (Unaligned)
  815. * | |
  816. * | |
  817. * | |
  818. * | |
  819. * | |
  820. * |-----------------------------|
  821. */
  822. if (qdf_unlikely((msdu_info->exception_fw)) ||
  823. (vdev->opmode == wlan_op_mode_ocb) ||
  824. (tx_exc_metadata &&
  825. tx_exc_metadata->is_tx_sniffer)) {
  826. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  827. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  828. DP_STATS_INC(vdev,
  829. tx_i.dropped.headroom_insufficient, 1);
  830. goto failure;
  831. }
  832. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  833. dp_tx_err("qdf_nbuf_push_head failed");
  834. goto failure;
  835. }
  836. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  837. msdu_info);
  838. if (htt_hdr_size == 0)
  839. goto failure;
  840. tx_desc->length = qdf_nbuf_headlen(nbuf);
  841. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  842. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  843. is_exception = 1;
  844. tx_desc->length -= tx_desc->pkt_offset;
  845. }
  846. #if !TQM_BYPASS_WAR
  847. if (is_exception || tx_exc_metadata)
  848. #endif
  849. {
  850. /* Temporary WAR due to TQM VP issues */
  851. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  852. qdf_atomic_inc(&soc->num_tx_exception);
  853. }
  854. return tx_desc;
  855. failure:
  856. dp_tx_desc_release(tx_desc, desc_pool_id);
  857. return NULL;
  858. }
  859. /**
  860. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  861. * @vdev: DP vdev handle
  862. * @nbuf: skb
  863. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  864. * @desc_pool_id : Descriptor Pool ID
  865. *
  866. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  867. * information. For frames wth fragments, allocate and prepare
  868. * an MSDU extension descriptor
  869. *
  870. * Return: Pointer to Tx Descriptor on success,
  871. * NULL on failure
  872. */
  873. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  874. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  875. uint8_t desc_pool_id)
  876. {
  877. struct dp_tx_desc_s *tx_desc;
  878. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  879. struct dp_pdev *pdev = vdev->pdev;
  880. struct dp_soc *soc = pdev->soc;
  881. if (dp_tx_limit_check(vdev))
  882. return NULL;
  883. /* Allocate software Tx descriptor */
  884. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  885. if (!tx_desc) {
  886. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  887. return NULL;
  888. }
  889. dp_tx_outstanding_inc(pdev);
  890. /* Initialize the SW tx descriptor */
  891. tx_desc->nbuf = nbuf;
  892. tx_desc->frm_type = msdu_info->frm_type;
  893. tx_desc->tx_encap_type = vdev->tx_encap_type;
  894. tx_desc->vdev_id = vdev->vdev_id;
  895. tx_desc->pdev = pdev;
  896. tx_desc->pkt_offset = 0;
  897. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  898. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  899. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  900. /* Handle scattered frames - TSO/SG/ME */
  901. /* Allocate and prepare an extension descriptor for scattered frames */
  902. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  903. if (!msdu_ext_desc) {
  904. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  905. goto failure;
  906. }
  907. #if TQM_BYPASS_WAR
  908. /* Temporary WAR due to TQM VP issues */
  909. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  910. qdf_atomic_inc(&soc->num_tx_exception);
  911. #endif
  912. if (qdf_unlikely(msdu_info->exception_fw))
  913. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  914. tx_desc->msdu_ext_desc = msdu_ext_desc;
  915. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  916. tx_desc->dma_addr = msdu_ext_desc->paddr;
  917. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  918. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  919. else
  920. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  921. return tx_desc;
  922. failure:
  923. dp_tx_desc_release(tx_desc, desc_pool_id);
  924. return NULL;
  925. }
  926. /**
  927. * dp_tx_prepare_raw() - Prepare RAW packet TX
  928. * @vdev: DP vdev handle
  929. * @nbuf: buffer pointer
  930. * @seg_info: Pointer to Segment info Descriptor to be prepared
  931. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  932. * descriptor
  933. *
  934. * Return:
  935. */
  936. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  937. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  938. {
  939. qdf_nbuf_t curr_nbuf = NULL;
  940. uint16_t total_len = 0;
  941. qdf_dma_addr_t paddr;
  942. int32_t i;
  943. int32_t mapped_buf_num = 0;
  944. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  945. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  946. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  947. /* Continue only if frames are of DATA type */
  948. if (!DP_FRAME_IS_DATA(qos_wh)) {
  949. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  950. dp_tx_debug("Pkt. recd is of not data type");
  951. goto error;
  952. }
  953. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  954. if (vdev->raw_mode_war &&
  955. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  956. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  957. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  958. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  959. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  960. /*
  961. * Number of nbuf's must not exceed the size of the frags
  962. * array in seg_info.
  963. */
  964. if (i >= DP_TX_MAX_NUM_FRAGS) {
  965. dp_err_rl("nbuf cnt exceeds the max number of segs");
  966. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  967. goto error;
  968. }
  969. if (QDF_STATUS_SUCCESS !=
  970. qdf_nbuf_map_nbytes_single(vdev->osdev,
  971. curr_nbuf,
  972. QDF_DMA_TO_DEVICE,
  973. curr_nbuf->len)) {
  974. dp_tx_err("%s dma map error ", __func__);
  975. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  976. goto error;
  977. }
  978. /* Update the count of mapped nbuf's */
  979. mapped_buf_num++;
  980. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  981. seg_info->frags[i].paddr_lo = paddr;
  982. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  983. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  984. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  985. total_len += qdf_nbuf_len(curr_nbuf);
  986. }
  987. seg_info->frag_cnt = i;
  988. seg_info->total_len = total_len;
  989. seg_info->next = NULL;
  990. sg_info->curr_seg = seg_info;
  991. msdu_info->frm_type = dp_tx_frm_raw;
  992. msdu_info->num_seg = 1;
  993. return nbuf;
  994. error:
  995. i = 0;
  996. while (nbuf) {
  997. curr_nbuf = nbuf;
  998. if (i < mapped_buf_num) {
  999. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1000. QDF_DMA_TO_DEVICE,
  1001. curr_nbuf->len);
  1002. i++;
  1003. }
  1004. nbuf = qdf_nbuf_next(nbuf);
  1005. qdf_nbuf_free(curr_nbuf);
  1006. }
  1007. return NULL;
  1008. }
  1009. /**
  1010. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1011. * @soc: DP soc handle
  1012. * @nbuf: Buffer pointer
  1013. *
  1014. * unmap the chain of nbufs that belong to this RAW frame.
  1015. *
  1016. * Return: None
  1017. */
  1018. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1019. qdf_nbuf_t nbuf)
  1020. {
  1021. qdf_nbuf_t cur_nbuf = nbuf;
  1022. do {
  1023. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1024. QDF_DMA_TO_DEVICE,
  1025. cur_nbuf->len);
  1026. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1027. } while (cur_nbuf);
  1028. }
  1029. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1030. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1031. { \
  1032. qdf_nbuf_t nbuf_local; \
  1033. struct dp_vdev *vdev_local = vdev_hdl; \
  1034. do { \
  1035. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1036. break; \
  1037. nbuf_local = nbuf; \
  1038. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1039. htt_cmn_pkt_type_raw)) \
  1040. break; \
  1041. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1042. break; \
  1043. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1044. break; \
  1045. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1046. (nbuf_local), \
  1047. NULL, 1, 0); \
  1048. } while (0); \
  1049. }
  1050. #else
  1051. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1052. #endif
  1053. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1054. /**
  1055. * dp_tx_update_stats() - Update soc level tx stats
  1056. * @soc: DP soc handle
  1057. * @nbuf: packet being transmitted
  1058. *
  1059. * Returns: none
  1060. */
  1061. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1062. qdf_nbuf_t nbuf)
  1063. {
  1064. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1065. }
  1066. /**
  1067. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1068. * @soc: Datapath soc handle
  1069. * @tx_desc: tx packet descriptor
  1070. * @tid: TID for pkt transmission
  1071. *
  1072. * Returns: 1, if coalescing is to be done
  1073. * 0, if coalescing is not to be done
  1074. */
  1075. static inline int
  1076. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1077. struct dp_tx_desc_s *tx_desc,
  1078. uint8_t tid)
  1079. {
  1080. struct dp_swlm *swlm = &soc->swlm;
  1081. union swlm_data swlm_query_data;
  1082. struct dp_swlm_tcl_data tcl_data;
  1083. QDF_STATUS status;
  1084. int ret;
  1085. if (qdf_unlikely(!swlm->is_enabled))
  1086. return 0;
  1087. tcl_data.nbuf = tx_desc->nbuf;
  1088. tcl_data.tid = tid;
  1089. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1090. swlm_query_data.tcl_data = &tcl_data;
  1091. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1092. if (QDF_IS_STATUS_ERROR(status)) {
  1093. dp_swlm_tcl_reset_session_data(soc);
  1094. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1095. return 0;
  1096. }
  1097. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1098. if (ret) {
  1099. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1100. } else {
  1101. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1102. }
  1103. return ret;
  1104. }
  1105. /**
  1106. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1107. * @soc: Datapath soc handle
  1108. * @hal_ring_hdl: HAL ring handle
  1109. * @coalesce: Coalesce the current write or not
  1110. *
  1111. * Returns: none
  1112. */
  1113. static inline void
  1114. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1115. int coalesce)
  1116. {
  1117. if (coalesce)
  1118. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1119. else
  1120. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1121. }
  1122. #else
  1123. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1124. qdf_nbuf_t nbuf)
  1125. {
  1126. }
  1127. static inline int
  1128. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1129. struct dp_tx_desc_s *tx_desc,
  1130. uint8_t tid)
  1131. {
  1132. return 0;
  1133. }
  1134. static inline void
  1135. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1136. int coalesce)
  1137. {
  1138. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1139. }
  1140. #endif
  1141. /**
  1142. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1143. * @soc: DP Soc Handle
  1144. * @vdev: DP vdev handle
  1145. * @tx_desc: Tx Descriptor Handle
  1146. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1147. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1148. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1149. * @tx_exc_metadata: Handle that holds exception path meta data
  1150. *
  1151. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1152. * from software Tx descriptor
  1153. *
  1154. * Return: QDF_STATUS_SUCCESS: success
  1155. * QDF_STATUS_E_RESOURCES: Error return
  1156. */
  1157. static QDF_STATUS
  1158. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1159. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1160. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1161. struct dp_tx_msdu_info_s *msdu_info)
  1162. {
  1163. void *hal_tx_desc;
  1164. uint32_t *hal_tx_desc_cached;
  1165. int coalesce = 0;
  1166. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1167. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1168. uint8_t tid = msdu_info->tid;
  1169. /*
  1170. * Setting it initialization statically here to avoid
  1171. * a memset call jump with qdf_mem_set call
  1172. */
  1173. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1174. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1175. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1176. tx_exc_metadata->sec_type : vdev->sec_type);
  1177. /* Return Buffer Manager ID */
  1178. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1179. hal_ring_handle_t hal_ring_hdl = NULL;
  1180. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1181. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1182. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1183. return QDF_STATUS_E_RESOURCES;
  1184. }
  1185. hal_tx_desc_cached = (void *) cached_desc;
  1186. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1187. tx_desc->dma_addr, bm_id, tx_desc->id,
  1188. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1189. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1190. vdev->lmac_id);
  1191. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1192. vdev->search_type);
  1193. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1194. vdev->bss_ast_idx);
  1195. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1196. vdev->dscp_tid_map_id);
  1197. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1198. sec_type_map[sec_type]);
  1199. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1200. (vdev->bss_ast_hash & 0xF));
  1201. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1202. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1203. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1204. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1205. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1206. vdev->hal_desc_addr_search_flags);
  1207. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1208. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1209. /* verify checksum offload configuration*/
  1210. if (vdev->csum_enabled &&
  1211. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1212. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1213. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1214. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1215. }
  1216. if (tid != HTT_TX_EXT_TID_INVALID)
  1217. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1218. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1219. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1220. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1221. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1222. soc->wlan_cfg_ctx)))
  1223. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1224. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1225. tx_desc->length,
  1226. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  1227. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  1228. tx_desc->id);
  1229. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1230. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1231. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1232. "%s %d : HAL RING Access Failed -- %pK",
  1233. __func__, __LINE__, hal_ring_hdl);
  1234. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1235. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1236. return status;
  1237. }
  1238. /* Sync cached descriptor with HW */
  1239. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1240. if (qdf_unlikely(!hal_tx_desc)) {
  1241. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1242. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1243. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1244. goto ring_access_fail;
  1245. }
  1246. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1247. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1248. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1249. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1250. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1251. dp_tx_update_stats(soc, tx_desc->nbuf);
  1252. status = QDF_STATUS_SUCCESS;
  1253. ring_access_fail:
  1254. if (hif_pm_runtime_get(soc->hif_handle,
  1255. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1256. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1257. hif_pm_runtime_put(soc->hif_handle,
  1258. RTPM_ID_DW_TX_HW_ENQUEUE);
  1259. } else {
  1260. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1261. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1262. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1263. }
  1264. return status;
  1265. }
  1266. /**
  1267. * dp_cce_classify() - Classify the frame based on CCE rules
  1268. * @vdev: DP vdev handle
  1269. * @nbuf: skb
  1270. *
  1271. * Classify frames based on CCE rules
  1272. * Return: bool( true if classified,
  1273. * else false)
  1274. */
  1275. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1276. {
  1277. qdf_ether_header_t *eh = NULL;
  1278. uint16_t ether_type;
  1279. qdf_llc_t *llcHdr;
  1280. qdf_nbuf_t nbuf_clone = NULL;
  1281. qdf_dot3_qosframe_t *qos_wh = NULL;
  1282. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1283. /*
  1284. * In case of mesh packets or hlos tid override enabled,
  1285. * don't do any classification
  1286. */
  1287. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1288. & DP_TX_SKIP_CCE_CLASSIFY))
  1289. return false;
  1290. }
  1291. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1292. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1293. ether_type = eh->ether_type;
  1294. llcHdr = (qdf_llc_t *)(nbuf->data +
  1295. sizeof(qdf_ether_header_t));
  1296. } else {
  1297. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1298. /* For encrypted packets don't do any classification */
  1299. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1300. return false;
  1301. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1302. if (qdf_unlikely(
  1303. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1304. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1305. ether_type = *(uint16_t *)(nbuf->data
  1306. + QDF_IEEE80211_4ADDR_HDR_LEN
  1307. + sizeof(qdf_llc_t)
  1308. - sizeof(ether_type));
  1309. llcHdr = (qdf_llc_t *)(nbuf->data +
  1310. QDF_IEEE80211_4ADDR_HDR_LEN);
  1311. } else {
  1312. ether_type = *(uint16_t *)(nbuf->data
  1313. + QDF_IEEE80211_3ADDR_HDR_LEN
  1314. + sizeof(qdf_llc_t)
  1315. - sizeof(ether_type));
  1316. llcHdr = (qdf_llc_t *)(nbuf->data +
  1317. QDF_IEEE80211_3ADDR_HDR_LEN);
  1318. }
  1319. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1320. && (ether_type ==
  1321. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1322. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1323. return true;
  1324. }
  1325. }
  1326. return false;
  1327. }
  1328. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1329. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1330. sizeof(*llcHdr));
  1331. nbuf_clone = qdf_nbuf_clone(nbuf);
  1332. if (qdf_unlikely(nbuf_clone)) {
  1333. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1334. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1335. qdf_nbuf_pull_head(nbuf_clone,
  1336. sizeof(qdf_net_vlanhdr_t));
  1337. }
  1338. }
  1339. } else {
  1340. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1341. nbuf_clone = qdf_nbuf_clone(nbuf);
  1342. if (qdf_unlikely(nbuf_clone)) {
  1343. qdf_nbuf_pull_head(nbuf_clone,
  1344. sizeof(qdf_net_vlanhdr_t));
  1345. }
  1346. }
  1347. }
  1348. if (qdf_unlikely(nbuf_clone))
  1349. nbuf = nbuf_clone;
  1350. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1351. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1352. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1353. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1354. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1355. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1356. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1357. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1358. if (qdf_unlikely(nbuf_clone))
  1359. qdf_nbuf_free(nbuf_clone);
  1360. return true;
  1361. }
  1362. if (qdf_unlikely(nbuf_clone))
  1363. qdf_nbuf_free(nbuf_clone);
  1364. return false;
  1365. }
  1366. /**
  1367. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1368. * @vdev: DP vdev handle
  1369. * @nbuf: skb
  1370. *
  1371. * Extract the DSCP or PCP information from frame and map into TID value.
  1372. *
  1373. * Return: void
  1374. */
  1375. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1376. struct dp_tx_msdu_info_s *msdu_info)
  1377. {
  1378. uint8_t tos = 0, dscp_tid_override = 0;
  1379. uint8_t *hdr_ptr, *L3datap;
  1380. uint8_t is_mcast = 0;
  1381. qdf_ether_header_t *eh = NULL;
  1382. qdf_ethervlan_header_t *evh = NULL;
  1383. uint16_t ether_type;
  1384. qdf_llc_t *llcHdr;
  1385. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1386. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1387. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1388. eh = (qdf_ether_header_t *)nbuf->data;
  1389. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1390. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1391. } else {
  1392. qdf_dot3_qosframe_t *qos_wh =
  1393. (qdf_dot3_qosframe_t *) nbuf->data;
  1394. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1395. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1396. return;
  1397. }
  1398. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1399. ether_type = eh->ether_type;
  1400. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1401. /*
  1402. * Check if packet is dot3 or eth2 type.
  1403. */
  1404. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1405. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1406. sizeof(*llcHdr));
  1407. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1408. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1409. sizeof(*llcHdr);
  1410. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1411. + sizeof(*llcHdr) +
  1412. sizeof(qdf_net_vlanhdr_t));
  1413. } else {
  1414. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1415. sizeof(*llcHdr);
  1416. }
  1417. } else {
  1418. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1419. evh = (qdf_ethervlan_header_t *) eh;
  1420. ether_type = evh->ether_type;
  1421. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1422. }
  1423. }
  1424. /*
  1425. * Find priority from IP TOS DSCP field
  1426. */
  1427. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1428. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1429. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1430. /* Only for unicast frames */
  1431. if (!is_mcast) {
  1432. /* send it on VO queue */
  1433. msdu_info->tid = DP_VO_TID;
  1434. }
  1435. } else {
  1436. /*
  1437. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1438. * from TOS byte.
  1439. */
  1440. tos = ip->ip_tos;
  1441. dscp_tid_override = 1;
  1442. }
  1443. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1444. /* TODO
  1445. * use flowlabel
  1446. *igmpmld cases to be handled in phase 2
  1447. */
  1448. unsigned long ver_pri_flowlabel;
  1449. unsigned long pri;
  1450. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1451. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1452. DP_IPV6_PRIORITY_SHIFT;
  1453. tos = pri;
  1454. dscp_tid_override = 1;
  1455. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1456. msdu_info->tid = DP_VO_TID;
  1457. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1458. /* Only for unicast frames */
  1459. if (!is_mcast) {
  1460. /* send ucast arp on VO queue */
  1461. msdu_info->tid = DP_VO_TID;
  1462. }
  1463. }
  1464. /*
  1465. * Assign all MCAST packets to BE
  1466. */
  1467. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1468. if (is_mcast) {
  1469. tos = 0;
  1470. dscp_tid_override = 1;
  1471. }
  1472. }
  1473. if (dscp_tid_override == 1) {
  1474. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1475. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1476. }
  1477. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1478. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1479. return;
  1480. }
  1481. /**
  1482. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1483. * @vdev: DP vdev handle
  1484. * @nbuf: skb
  1485. *
  1486. * Software based TID classification is required when more than 2 DSCP-TID
  1487. * mapping tables are needed.
  1488. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1489. *
  1490. * Return: void
  1491. */
  1492. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1493. struct dp_tx_msdu_info_s *msdu_info)
  1494. {
  1495. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1496. /*
  1497. * skip_sw_tid_classification flag will set in below cases-
  1498. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1499. * 2. hlos_tid_override enabled for vdev
  1500. * 3. mesh mode enabled for vdev
  1501. */
  1502. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1503. /* Update tid in msdu_info from skb priority */
  1504. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1505. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1506. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1507. return;
  1508. }
  1509. return;
  1510. }
  1511. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1512. }
  1513. #ifdef FEATURE_WLAN_TDLS
  1514. /**
  1515. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1516. * @soc: datapath SOC
  1517. * @vdev: datapath vdev
  1518. * @tx_desc: TX descriptor
  1519. *
  1520. * Return: None
  1521. */
  1522. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1523. struct dp_vdev *vdev,
  1524. struct dp_tx_desc_s *tx_desc)
  1525. {
  1526. if (vdev) {
  1527. if (vdev->is_tdls_frame) {
  1528. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1529. vdev->is_tdls_frame = false;
  1530. }
  1531. }
  1532. }
  1533. /**
  1534. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1535. * @soc: dp_soc handle
  1536. * @tx_desc: TX descriptor
  1537. * @vdev: datapath vdev handle
  1538. *
  1539. * Return: None
  1540. */
  1541. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1542. struct dp_tx_desc_s *tx_desc)
  1543. {
  1544. struct hal_tx_completion_status ts = {0};
  1545. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1546. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1547. DP_MOD_ID_TDLS);
  1548. if (qdf_unlikely(!vdev)) {
  1549. dp_err_rl("vdev is null!");
  1550. goto error;
  1551. }
  1552. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1553. if (vdev->tx_non_std_data_callback.func) {
  1554. qdf_nbuf_set_next(nbuf, NULL);
  1555. vdev->tx_non_std_data_callback.func(
  1556. vdev->tx_non_std_data_callback.ctxt,
  1557. nbuf, ts.status);
  1558. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1559. return;
  1560. } else {
  1561. dp_err_rl("callback func is null");
  1562. }
  1563. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1564. error:
  1565. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1566. qdf_nbuf_free(nbuf);
  1567. }
  1568. /**
  1569. * dp_tx_msdu_single_map() - do nbuf map
  1570. * @vdev: DP vdev handle
  1571. * @tx_desc: DP TX descriptor pointer
  1572. * @nbuf: skb pointer
  1573. *
  1574. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1575. * operation done in other component.
  1576. *
  1577. * Return: QDF_STATUS
  1578. */
  1579. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1580. struct dp_tx_desc_s *tx_desc,
  1581. qdf_nbuf_t nbuf)
  1582. {
  1583. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1584. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1585. nbuf,
  1586. QDF_DMA_TO_DEVICE,
  1587. nbuf->len);
  1588. else
  1589. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1590. QDF_DMA_TO_DEVICE);
  1591. }
  1592. #else
  1593. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1594. struct dp_vdev *vdev,
  1595. struct dp_tx_desc_s *tx_desc)
  1596. {
  1597. }
  1598. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1599. struct dp_tx_desc_s *tx_desc)
  1600. {
  1601. }
  1602. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1603. struct dp_tx_desc_s *tx_desc,
  1604. qdf_nbuf_t nbuf)
  1605. {
  1606. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1607. nbuf,
  1608. QDF_DMA_TO_DEVICE,
  1609. nbuf->len);
  1610. }
  1611. #endif
  1612. #ifdef MESH_MODE_SUPPORT
  1613. /**
  1614. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1615. * @soc: datapath SOC
  1616. * @vdev: datapath vdev
  1617. * @tx_desc: TX descriptor
  1618. *
  1619. * Return: None
  1620. */
  1621. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1622. struct dp_vdev *vdev,
  1623. struct dp_tx_desc_s *tx_desc)
  1624. {
  1625. if (qdf_unlikely(vdev->mesh_vdev))
  1626. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1627. }
  1628. /**
  1629. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1630. * @soc: dp_soc handle
  1631. * @tx_desc: TX descriptor
  1632. * @vdev: datapath vdev handle
  1633. *
  1634. * Return: None
  1635. */
  1636. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1637. struct dp_tx_desc_s *tx_desc)
  1638. {
  1639. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1640. struct dp_vdev *vdev = NULL;
  1641. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1642. qdf_nbuf_free(nbuf);
  1643. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1644. } else {
  1645. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1646. DP_MOD_ID_MESH);
  1647. if (vdev && vdev->osif_tx_free_ext)
  1648. vdev->osif_tx_free_ext((nbuf));
  1649. else
  1650. qdf_nbuf_free(nbuf);
  1651. if (vdev)
  1652. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1653. }
  1654. }
  1655. #else
  1656. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1657. struct dp_vdev *vdev,
  1658. struct dp_tx_desc_s *tx_desc)
  1659. {
  1660. }
  1661. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1662. struct dp_tx_desc_s *tx_desc)
  1663. {
  1664. }
  1665. #endif
  1666. /**
  1667. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1668. * @vdev: DP vdev handle
  1669. * @nbuf: skb
  1670. *
  1671. * Return: 1 if frame needs to be dropped else 0
  1672. */
  1673. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1674. {
  1675. struct dp_pdev *pdev = NULL;
  1676. struct dp_ast_entry *src_ast_entry = NULL;
  1677. struct dp_ast_entry *dst_ast_entry = NULL;
  1678. struct dp_soc *soc = NULL;
  1679. qdf_assert(vdev);
  1680. pdev = vdev->pdev;
  1681. qdf_assert(pdev);
  1682. soc = pdev->soc;
  1683. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1684. (soc, dstmac, vdev->pdev->pdev_id);
  1685. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1686. (soc, srcmac, vdev->pdev->pdev_id);
  1687. if (dst_ast_entry && src_ast_entry) {
  1688. if (dst_ast_entry->peer_id ==
  1689. src_ast_entry->peer_id)
  1690. return 1;
  1691. }
  1692. return 0;
  1693. }
  1694. /**
  1695. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1696. * @vdev: DP vdev handle
  1697. * @nbuf: skb
  1698. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1699. * @meta_data: Metadata to the fw
  1700. * @tx_q: Tx queue to be used for this Tx frame
  1701. * @peer_id: peer_id of the peer in case of NAWDS frames
  1702. * @tx_exc_metadata: Handle that holds exception path metadata
  1703. *
  1704. * Return: NULL on success,
  1705. * nbuf when it fails to send
  1706. */
  1707. qdf_nbuf_t
  1708. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1709. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1710. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1711. {
  1712. struct dp_pdev *pdev = vdev->pdev;
  1713. struct dp_soc *soc = pdev->soc;
  1714. struct dp_tx_desc_s *tx_desc;
  1715. QDF_STATUS status;
  1716. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1717. uint16_t htt_tcl_metadata = 0;
  1718. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1719. uint8_t tid = msdu_info->tid;
  1720. struct cdp_tid_tx_stats *tid_stats = NULL;
  1721. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1722. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1723. msdu_info, tx_exc_metadata);
  1724. if (!tx_desc) {
  1725. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1726. vdev, tx_q->desc_pool_id);
  1727. drop_code = TX_DESC_ERR;
  1728. goto fail_return;
  1729. }
  1730. if (qdf_unlikely(soc->cce_disable)) {
  1731. if (dp_cce_classify(vdev, nbuf) == true) {
  1732. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1733. tid = DP_VO_TID;
  1734. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1735. }
  1736. }
  1737. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1738. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1739. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1740. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1741. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1742. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1743. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1744. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1745. peer_id);
  1746. } else
  1747. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1748. if (msdu_info->exception_fw)
  1749. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1750. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1751. !pdev->enhanced_stats_en);
  1752. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1753. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1754. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1755. /* Handle failure */
  1756. dp_err("qdf_nbuf_map failed");
  1757. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1758. drop_code = TX_DMA_MAP_ERR;
  1759. goto release_desc;
  1760. }
  1761. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1762. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1763. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1764. tx_exc_metadata, msdu_info);
  1765. if (status != QDF_STATUS_SUCCESS) {
  1766. dp_tx_err("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1767. tx_desc, tx_q->ring_id);
  1768. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1769. QDF_DMA_TO_DEVICE,
  1770. nbuf->len);
  1771. drop_code = TX_HW_ENQUEUE;
  1772. goto release_desc;
  1773. }
  1774. return NULL;
  1775. release_desc:
  1776. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1777. fail_return:
  1778. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1779. tid_stats = &pdev->stats.tid_stats.
  1780. tid_tx_stats[tx_q->ring_id][tid];
  1781. tid_stats->swdrop_cnt[drop_code]++;
  1782. return nbuf;
  1783. }
  1784. /**
  1785. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1786. * @soc: Soc handle
  1787. * @desc: software Tx descriptor to be processed
  1788. *
  1789. * Return: none
  1790. */
  1791. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1792. struct dp_tx_desc_s *desc)
  1793. {
  1794. qdf_nbuf_t nbuf = desc->nbuf;
  1795. /* nbuf already freed in vdev detach path */
  1796. if (!nbuf)
  1797. return;
  1798. /* If it is TDLS mgmt, don't unmap or free the frame */
  1799. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1800. return dp_non_std_tx_comp_free_buff(soc, desc);
  1801. /* 0 : MSDU buffer, 1 : MLE */
  1802. if (desc->msdu_ext_desc) {
  1803. /* TSO free */
  1804. if (hal_tx_ext_desc_get_tso_enable(
  1805. desc->msdu_ext_desc->vaddr)) {
  1806. /* unmap eash TSO seg before free the nbuf */
  1807. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1808. desc->tso_num_desc);
  1809. qdf_nbuf_free(nbuf);
  1810. return;
  1811. }
  1812. }
  1813. /* If it's ME frame, dont unmap the cloned nbuf's */
  1814. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1815. goto nbuf_free;
  1816. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1817. QDF_DMA_TO_DEVICE, nbuf->len);
  1818. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1819. return dp_mesh_tx_comp_free_buff(soc, desc);
  1820. nbuf_free:
  1821. qdf_nbuf_free(nbuf);
  1822. }
  1823. /**
  1824. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1825. * @vdev: DP vdev handle
  1826. * @nbuf: skb
  1827. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1828. *
  1829. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1830. *
  1831. * Return: NULL on success,
  1832. * nbuf when it fails to send
  1833. */
  1834. #if QDF_LOCK_STATS
  1835. noinline
  1836. #else
  1837. #endif
  1838. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1839. struct dp_tx_msdu_info_s *msdu_info)
  1840. {
  1841. uint32_t i;
  1842. struct dp_pdev *pdev = vdev->pdev;
  1843. struct dp_soc *soc = pdev->soc;
  1844. struct dp_tx_desc_s *tx_desc;
  1845. bool is_cce_classified = false;
  1846. QDF_STATUS status;
  1847. uint16_t htt_tcl_metadata = 0;
  1848. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1849. struct cdp_tid_tx_stats *tid_stats = NULL;
  1850. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1851. if (qdf_unlikely(soc->cce_disable)) {
  1852. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1853. if (is_cce_classified) {
  1854. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1855. msdu_info->tid = DP_VO_TID;
  1856. }
  1857. }
  1858. if (msdu_info->frm_type == dp_tx_frm_me)
  1859. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1860. i = 0;
  1861. /* Print statement to track i and num_seg */
  1862. /*
  1863. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1864. * descriptors using information in msdu_info
  1865. */
  1866. while (i < msdu_info->num_seg) {
  1867. /*
  1868. * Setup Tx descriptor for an MSDU, and MSDU extension
  1869. * descriptor
  1870. */
  1871. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1872. tx_q->desc_pool_id);
  1873. if (!tx_desc) {
  1874. if (msdu_info->frm_type == dp_tx_frm_me) {
  1875. prep_desc_fail++;
  1876. dp_tx_me_free_buf(pdev,
  1877. (void *)(msdu_info->u.sg_info
  1878. .curr_seg->frags[0].vaddr));
  1879. if (prep_desc_fail == msdu_info->num_seg) {
  1880. /*
  1881. * Unmap is needed only if descriptor
  1882. * preparation failed for all segments.
  1883. */
  1884. qdf_nbuf_unmap(soc->osdev,
  1885. msdu_info->u.sg_info.
  1886. curr_seg->nbuf,
  1887. QDF_DMA_TO_DEVICE);
  1888. }
  1889. /*
  1890. * Free the nbuf for the current segment
  1891. * and make it point to the next in the list.
  1892. * For me, there are as many segments as there
  1893. * are no of clients.
  1894. */
  1895. qdf_nbuf_free(msdu_info->u.sg_info
  1896. .curr_seg->nbuf);
  1897. if (msdu_info->u.sg_info.curr_seg->next) {
  1898. msdu_info->u.sg_info.curr_seg =
  1899. msdu_info->u.sg_info
  1900. .curr_seg->next;
  1901. nbuf = msdu_info->u.sg_info
  1902. .curr_seg->nbuf;
  1903. }
  1904. i++;
  1905. continue;
  1906. }
  1907. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1908. dp_tx_tso_unmap_segment(soc,
  1909. msdu_info->u.tso_info.
  1910. curr_seg,
  1911. msdu_info->u.tso_info.
  1912. tso_num_seg_list);
  1913. if (msdu_info->u.tso_info.curr_seg->next) {
  1914. msdu_info->u.tso_info.curr_seg =
  1915. msdu_info->u.tso_info.curr_seg->next;
  1916. i++;
  1917. continue;
  1918. }
  1919. }
  1920. goto done;
  1921. }
  1922. if (msdu_info->frm_type == dp_tx_frm_me) {
  1923. tx_desc->me_buffer =
  1924. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1925. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1926. }
  1927. if (is_cce_classified)
  1928. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1929. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1930. if (msdu_info->exception_fw) {
  1931. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1932. }
  1933. /*
  1934. * For frames with multiple segments (TSO, ME), jump to next
  1935. * segment.
  1936. */
  1937. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1938. if (msdu_info->u.tso_info.curr_seg->next) {
  1939. msdu_info->u.tso_info.curr_seg =
  1940. msdu_info->u.tso_info.curr_seg->next;
  1941. /*
  1942. * If this is a jumbo nbuf, then increment the
  1943. * number of nbuf users for each additional
  1944. * segment of the msdu. This will ensure that
  1945. * the skb is freed only after receiving tx
  1946. * completion for all segments of an nbuf
  1947. */
  1948. qdf_nbuf_inc_users(nbuf);
  1949. /* Check with MCL if this is needed */
  1950. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1951. */
  1952. }
  1953. }
  1954. /*
  1955. * Enqueue the Tx MSDU descriptor to HW for transmit
  1956. */
  1957. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1958. NULL, msdu_info);
  1959. if (status != QDF_STATUS_SUCCESS) {
  1960. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1961. tx_desc, tx_q->ring_id);
  1962. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1963. tid_stats = &pdev->stats.tid_stats.
  1964. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1965. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1966. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1967. if (msdu_info->frm_type == dp_tx_frm_me) {
  1968. hw_enq_fail++;
  1969. if (hw_enq_fail == msdu_info->num_seg) {
  1970. /*
  1971. * Unmap is needed only if enqueue
  1972. * failed for all segments.
  1973. */
  1974. qdf_nbuf_unmap(soc->osdev,
  1975. msdu_info->u.sg_info.
  1976. curr_seg->nbuf,
  1977. QDF_DMA_TO_DEVICE);
  1978. }
  1979. /*
  1980. * Free the nbuf for the current segment
  1981. * and make it point to the next in the list.
  1982. * For me, there are as many segments as there
  1983. * are no of clients.
  1984. */
  1985. qdf_nbuf_free(msdu_info->u.sg_info
  1986. .curr_seg->nbuf);
  1987. if (msdu_info->u.sg_info.curr_seg->next) {
  1988. msdu_info->u.sg_info.curr_seg =
  1989. msdu_info->u.sg_info
  1990. .curr_seg->next;
  1991. nbuf = msdu_info->u.sg_info
  1992. .curr_seg->nbuf;
  1993. }
  1994. i++;
  1995. continue;
  1996. }
  1997. /*
  1998. * For TSO frames, the nbuf users increment done for
  1999. * the current segment has to be reverted, since the
  2000. * hw enqueue for this segment failed
  2001. */
  2002. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2003. msdu_info->u.tso_info.curr_seg) {
  2004. /*
  2005. * unmap and free current,
  2006. * retransmit remaining segments
  2007. */
  2008. dp_tx_comp_free_buf(soc, tx_desc);
  2009. i++;
  2010. continue;
  2011. }
  2012. goto done;
  2013. }
  2014. /*
  2015. * TODO
  2016. * if tso_info structure can be modified to have curr_seg
  2017. * as first element, following 2 blocks of code (for TSO and SG)
  2018. * can be combined into 1
  2019. */
  2020. /*
  2021. * For Multicast-Unicast converted packets,
  2022. * each converted frame (for a client) is represented as
  2023. * 1 segment
  2024. */
  2025. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2026. (msdu_info->frm_type == dp_tx_frm_me)) {
  2027. if (msdu_info->u.sg_info.curr_seg->next) {
  2028. msdu_info->u.sg_info.curr_seg =
  2029. msdu_info->u.sg_info.curr_seg->next;
  2030. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2031. }
  2032. }
  2033. i++;
  2034. }
  2035. nbuf = NULL;
  2036. done:
  2037. return nbuf;
  2038. }
  2039. /**
  2040. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2041. * for SG frames
  2042. * @vdev: DP vdev handle
  2043. * @nbuf: skb
  2044. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2045. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2046. *
  2047. * Return: NULL on success,
  2048. * nbuf when it fails to send
  2049. */
  2050. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2051. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2052. {
  2053. uint32_t cur_frag, nr_frags, i;
  2054. qdf_dma_addr_t paddr;
  2055. struct dp_tx_sg_info_s *sg_info;
  2056. sg_info = &msdu_info->u.sg_info;
  2057. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2058. if (QDF_STATUS_SUCCESS !=
  2059. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2060. QDF_DMA_TO_DEVICE,
  2061. qdf_nbuf_headlen(nbuf))) {
  2062. dp_tx_err("dma map error");
  2063. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2064. qdf_nbuf_free(nbuf);
  2065. return NULL;
  2066. }
  2067. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2068. seg_info->frags[0].paddr_lo = paddr;
  2069. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2070. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2071. seg_info->frags[0].vaddr = (void *) nbuf;
  2072. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2073. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2074. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2075. dp_tx_err("frag dma map error");
  2076. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2077. goto map_err;
  2078. }
  2079. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2080. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2081. seg_info->frags[cur_frag + 1].paddr_hi =
  2082. ((uint64_t) paddr) >> 32;
  2083. seg_info->frags[cur_frag + 1].len =
  2084. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2085. }
  2086. seg_info->frag_cnt = (cur_frag + 1);
  2087. seg_info->total_len = qdf_nbuf_len(nbuf);
  2088. seg_info->next = NULL;
  2089. sg_info->curr_seg = seg_info;
  2090. msdu_info->frm_type = dp_tx_frm_sg;
  2091. msdu_info->num_seg = 1;
  2092. return nbuf;
  2093. map_err:
  2094. /* restore paddr into nbuf before calling unmap */
  2095. qdf_nbuf_mapped_paddr_set(nbuf,
  2096. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2097. ((uint64_t)
  2098. seg_info->frags[0].paddr_hi) << 32));
  2099. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2100. QDF_DMA_TO_DEVICE,
  2101. seg_info->frags[0].len);
  2102. for (i = 1; i <= cur_frag; i++) {
  2103. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2104. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2105. seg_info->frags[i].paddr_hi) << 32),
  2106. seg_info->frags[i].len,
  2107. QDF_DMA_TO_DEVICE);
  2108. }
  2109. qdf_nbuf_free(nbuf);
  2110. return NULL;
  2111. }
  2112. /**
  2113. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2114. * @vdev: DP vdev handle
  2115. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2116. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2117. *
  2118. * Return: NULL on failure,
  2119. * nbuf when extracted successfully
  2120. */
  2121. static
  2122. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2123. struct dp_tx_msdu_info_s *msdu_info,
  2124. uint16_t ppdu_cookie)
  2125. {
  2126. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2127. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2128. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2129. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2130. (msdu_info->meta_data[5], 1);
  2131. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2132. (msdu_info->meta_data[5], 1);
  2133. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2134. (msdu_info->meta_data[6], ppdu_cookie);
  2135. msdu_info->exception_fw = 1;
  2136. msdu_info->is_tx_sniffer = 1;
  2137. }
  2138. #ifdef MESH_MODE_SUPPORT
  2139. /**
  2140. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2141. and prepare msdu_info for mesh frames.
  2142. * @vdev: DP vdev handle
  2143. * @nbuf: skb
  2144. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2145. *
  2146. * Return: NULL on failure,
  2147. * nbuf when extracted successfully
  2148. */
  2149. static
  2150. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2151. struct dp_tx_msdu_info_s *msdu_info)
  2152. {
  2153. struct meta_hdr_s *mhdr;
  2154. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2155. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2156. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2157. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2158. msdu_info->exception_fw = 0;
  2159. goto remove_meta_hdr;
  2160. }
  2161. msdu_info->exception_fw = 1;
  2162. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2163. meta_data->host_tx_desc_pool = 1;
  2164. meta_data->update_peer_cache = 1;
  2165. meta_data->learning_frame = 1;
  2166. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2167. meta_data->power = mhdr->power;
  2168. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2169. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2170. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2171. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2172. meta_data->dyn_bw = 1;
  2173. meta_data->valid_pwr = 1;
  2174. meta_data->valid_mcs_mask = 1;
  2175. meta_data->valid_nss_mask = 1;
  2176. meta_data->valid_preamble_type = 1;
  2177. meta_data->valid_retries = 1;
  2178. meta_data->valid_bw_info = 1;
  2179. }
  2180. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2181. meta_data->encrypt_type = 0;
  2182. meta_data->valid_encrypt_type = 1;
  2183. meta_data->learning_frame = 0;
  2184. }
  2185. meta_data->valid_key_flags = 1;
  2186. meta_data->key_flags = (mhdr->keyix & 0x3);
  2187. remove_meta_hdr:
  2188. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2189. dp_tx_err("qdf_nbuf_pull_head failed");
  2190. qdf_nbuf_free(nbuf);
  2191. return NULL;
  2192. }
  2193. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2194. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2195. " tid %d to_fw %d",
  2196. msdu_info->meta_data[0],
  2197. msdu_info->meta_data[1],
  2198. msdu_info->meta_data[2],
  2199. msdu_info->meta_data[3],
  2200. msdu_info->meta_data[4],
  2201. msdu_info->meta_data[5],
  2202. msdu_info->tid, msdu_info->exception_fw);
  2203. return nbuf;
  2204. }
  2205. #else
  2206. static
  2207. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2208. struct dp_tx_msdu_info_s *msdu_info)
  2209. {
  2210. return nbuf;
  2211. }
  2212. #endif
  2213. /**
  2214. * dp_check_exc_metadata() - Checks if parameters are valid
  2215. * @tx_exc - holds all exception path parameters
  2216. *
  2217. * Returns true when all the parameters are valid else false
  2218. *
  2219. */
  2220. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2221. {
  2222. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2223. HTT_INVALID_TID);
  2224. bool invalid_encap_type =
  2225. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2226. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2227. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2228. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2229. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2230. tx_exc->ppdu_cookie == 0);
  2231. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2232. invalid_cookie) {
  2233. return false;
  2234. }
  2235. return true;
  2236. }
  2237. #ifdef ATH_SUPPORT_IQUE
  2238. /**
  2239. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2240. * @vdev: vdev handle
  2241. * @nbuf: skb
  2242. *
  2243. * Return: true on success,
  2244. * false on failure
  2245. */
  2246. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2247. {
  2248. qdf_ether_header_t *eh;
  2249. /* Mcast to Ucast Conversion*/
  2250. if (qdf_likely(!vdev->mcast_enhancement_en))
  2251. return true;
  2252. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2253. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2254. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2255. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2256. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2257. qdf_nbuf_len(nbuf));
  2258. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2259. QDF_STATUS_SUCCESS) {
  2260. return false;
  2261. }
  2262. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2263. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2264. QDF_STATUS_SUCCESS) {
  2265. return false;
  2266. }
  2267. }
  2268. }
  2269. return true;
  2270. }
  2271. #else
  2272. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2273. {
  2274. return true;
  2275. }
  2276. #endif
  2277. /**
  2278. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2279. * @nbuf: qdf_nbuf_t
  2280. * @vdev: struct dp_vdev *
  2281. *
  2282. * Allow packet for processing only if it is for peer client which is
  2283. * connected with same vap. Drop packet if client is connected to
  2284. * different vap.
  2285. *
  2286. * Return: QDF_STATUS
  2287. */
  2288. static inline QDF_STATUS
  2289. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2290. {
  2291. struct dp_ast_entry *dst_ast_entry = NULL;
  2292. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2293. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2294. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2295. return QDF_STATUS_SUCCESS;
  2296. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2297. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2298. eh->ether_dhost,
  2299. vdev->vdev_id);
  2300. /* If there is no ast entry, return failure */
  2301. if (qdf_unlikely(!dst_ast_entry)) {
  2302. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2303. return QDF_STATUS_E_FAILURE;
  2304. }
  2305. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2306. return QDF_STATUS_SUCCESS;
  2307. }
  2308. /**
  2309. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2310. * @soc: DP soc handle
  2311. * @vdev_id: id of DP vdev handle
  2312. * @nbuf: skb
  2313. * @tx_exc_metadata: Handle that holds exception path meta data
  2314. *
  2315. * Entry point for Core Tx layer (DP_TX) invoked from
  2316. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2317. *
  2318. * Return: NULL on success,
  2319. * nbuf when it fails to send
  2320. */
  2321. qdf_nbuf_t
  2322. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2323. qdf_nbuf_t nbuf,
  2324. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2325. {
  2326. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2327. qdf_ether_header_t *eh = NULL;
  2328. struct dp_tx_msdu_info_s msdu_info;
  2329. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2330. DP_MOD_ID_TX_EXCEPTION);
  2331. if (qdf_unlikely(!vdev))
  2332. goto fail;
  2333. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2334. if (!tx_exc_metadata)
  2335. goto fail;
  2336. msdu_info.tid = tx_exc_metadata->tid;
  2337. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2338. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2339. QDF_MAC_ADDR_REF(nbuf->data));
  2340. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2341. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2342. dp_tx_err("Invalid parameters in exception path");
  2343. goto fail;
  2344. }
  2345. /* Basic sanity checks for unsupported packets */
  2346. /* MESH mode */
  2347. if (qdf_unlikely(vdev->mesh_vdev)) {
  2348. dp_tx_err("Mesh mode is not supported in exception path");
  2349. goto fail;
  2350. }
  2351. /*
  2352. * Classify the frame and call corresponding
  2353. * "prepare" function which extracts the segment (TSO)
  2354. * and fragmentation information (for TSO , SG, ME, or Raw)
  2355. * into MSDU_INFO structure which is later used to fill
  2356. * SW and HW descriptors.
  2357. */
  2358. if (qdf_nbuf_is_tso(nbuf)) {
  2359. dp_verbose_debug("TSO frame %pK", vdev);
  2360. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2361. qdf_nbuf_len(nbuf));
  2362. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2363. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2364. qdf_nbuf_len(nbuf));
  2365. goto fail;
  2366. }
  2367. goto send_multiple;
  2368. }
  2369. /* SG */
  2370. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2371. struct dp_tx_seg_info_s seg_info = {0};
  2372. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2373. if (!nbuf)
  2374. goto fail;
  2375. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2376. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2377. qdf_nbuf_len(nbuf));
  2378. goto send_multiple;
  2379. }
  2380. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2381. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2382. qdf_nbuf_len(nbuf));
  2383. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2384. tx_exc_metadata->ppdu_cookie);
  2385. }
  2386. /*
  2387. * Get HW Queue to use for this frame.
  2388. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2389. * dedicated for data and 1 for command.
  2390. * "queue_id" maps to one hardware ring.
  2391. * With each ring, we also associate a unique Tx descriptor pool
  2392. * to minimize lock contention for these resources.
  2393. */
  2394. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2395. /*
  2396. * Check exception descriptors
  2397. */
  2398. if (dp_tx_exception_limit_check(vdev))
  2399. goto fail;
  2400. /* Single linear frame */
  2401. /*
  2402. * If nbuf is a simple linear frame, use send_single function to
  2403. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2404. * SRNG. There is no need to setup a MSDU extension descriptor.
  2405. */
  2406. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2407. tx_exc_metadata->peer_id, tx_exc_metadata);
  2408. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2409. return nbuf;
  2410. send_multiple:
  2411. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2412. fail:
  2413. if (vdev)
  2414. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2415. dp_verbose_debug("pkt send failed");
  2416. return nbuf;
  2417. }
  2418. /**
  2419. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2420. * in exception path in special case to avoid regular exception path chk.
  2421. * @soc: DP soc handle
  2422. * @vdev_id: id of DP vdev handle
  2423. * @nbuf: skb
  2424. * @tx_exc_metadata: Handle that holds exception path meta data
  2425. *
  2426. * Entry point for Core Tx layer (DP_TX) invoked from
  2427. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2428. *
  2429. * Return: NULL on success,
  2430. * nbuf when it fails to send
  2431. */
  2432. qdf_nbuf_t
  2433. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2434. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2435. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2436. {
  2437. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2438. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2439. DP_MOD_ID_TX_EXCEPTION);
  2440. if (qdf_unlikely(!vdev))
  2441. goto fail;
  2442. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2443. == QDF_STATUS_E_FAILURE)) {
  2444. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2445. goto fail;
  2446. }
  2447. /* Unref count as it will agin be taken inside dp_tx_exception */
  2448. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2449. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2450. fail:
  2451. if (vdev)
  2452. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2453. dp_verbose_debug("pkt send failed");
  2454. return nbuf;
  2455. }
  2456. /**
  2457. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2458. * @soc: DP soc handle
  2459. * @vdev_id: DP vdev handle
  2460. * @nbuf: skb
  2461. *
  2462. * Entry point for Core Tx layer (DP_TX) invoked from
  2463. * hard_start_xmit in OSIF/HDD
  2464. *
  2465. * Return: NULL on success,
  2466. * nbuf when it fails to send
  2467. */
  2468. #ifdef MESH_MODE_SUPPORT
  2469. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2470. qdf_nbuf_t nbuf)
  2471. {
  2472. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2473. struct meta_hdr_s *mhdr;
  2474. qdf_nbuf_t nbuf_mesh = NULL;
  2475. qdf_nbuf_t nbuf_clone = NULL;
  2476. struct dp_vdev *vdev;
  2477. uint8_t no_enc_frame = 0;
  2478. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2479. if (!nbuf_mesh) {
  2480. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2481. "qdf_nbuf_unshare failed");
  2482. return nbuf;
  2483. }
  2484. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2485. if (!vdev) {
  2486. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2487. "vdev is NULL for vdev_id %d", vdev_id);
  2488. return nbuf;
  2489. }
  2490. nbuf = nbuf_mesh;
  2491. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2492. if ((vdev->sec_type != cdp_sec_type_none) &&
  2493. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2494. no_enc_frame = 1;
  2495. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2496. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2497. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2498. !no_enc_frame) {
  2499. nbuf_clone = qdf_nbuf_clone(nbuf);
  2500. if (!nbuf_clone) {
  2501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2502. "qdf_nbuf_clone failed");
  2503. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2504. return nbuf;
  2505. }
  2506. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2507. }
  2508. if (nbuf_clone) {
  2509. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2510. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2511. } else {
  2512. qdf_nbuf_free(nbuf_clone);
  2513. }
  2514. }
  2515. if (no_enc_frame)
  2516. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2517. else
  2518. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2519. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2520. if ((!nbuf) && no_enc_frame) {
  2521. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2522. }
  2523. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2524. return nbuf;
  2525. }
  2526. #else
  2527. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2528. qdf_nbuf_t nbuf)
  2529. {
  2530. return dp_tx_send(soc, vdev_id, nbuf);
  2531. }
  2532. #endif
  2533. /**
  2534. * dp_tx_nawds_handler() - NAWDS handler
  2535. *
  2536. * @soc: DP soc handle
  2537. * @vdev_id: id of DP vdev handle
  2538. * @msdu_info: msdu_info required to create HTT metadata
  2539. * @nbuf: skb
  2540. *
  2541. * This API transfers the multicast frames with the peer id
  2542. * on NAWDS enabled peer.
  2543. * Return: none
  2544. */
  2545. static inline
  2546. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2547. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2548. {
  2549. struct dp_peer *peer = NULL;
  2550. qdf_nbuf_t nbuf_clone = NULL;
  2551. uint16_t peer_id = DP_INVALID_PEER;
  2552. uint16_t sa_peer_id = DP_INVALID_PEER;
  2553. struct dp_ast_entry *ast_entry = NULL;
  2554. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2555. qdf_spin_lock_bh(&soc->ast_lock);
  2556. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2557. (soc,
  2558. (uint8_t *)(eh->ether_shost),
  2559. vdev->pdev->pdev_id);
  2560. if (ast_entry)
  2561. sa_peer_id = ast_entry->peer_id;
  2562. qdf_spin_unlock_bh(&soc->ast_lock);
  2563. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2564. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2565. if (!peer->bss_peer && peer->nawds_enabled) {
  2566. peer_id = peer->peer_id;
  2567. /* Multicast packets needs to be
  2568. * dropped in case of intra bss forwarding
  2569. */
  2570. if (sa_peer_id == peer->peer_id) {
  2571. QDF_TRACE(QDF_MODULE_ID_DP,
  2572. QDF_TRACE_LEVEL_DEBUG,
  2573. " %s: multicast packet", __func__);
  2574. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2575. continue;
  2576. }
  2577. nbuf_clone = qdf_nbuf_clone(nbuf);
  2578. if (!nbuf_clone) {
  2579. QDF_TRACE(QDF_MODULE_ID_DP,
  2580. QDF_TRACE_LEVEL_ERROR,
  2581. FL("nbuf clone failed"));
  2582. break;
  2583. }
  2584. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2585. msdu_info, peer_id,
  2586. NULL);
  2587. if (nbuf_clone) {
  2588. QDF_TRACE(QDF_MODULE_ID_DP,
  2589. QDF_TRACE_LEVEL_DEBUG,
  2590. FL("pkt send failed"));
  2591. qdf_nbuf_free(nbuf_clone);
  2592. } else {
  2593. if (peer_id != DP_INVALID_PEER)
  2594. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2595. 1, qdf_nbuf_len(nbuf));
  2596. }
  2597. }
  2598. }
  2599. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2600. }
  2601. /**
  2602. * dp_tx_send() - Transmit a frame on a given VAP
  2603. * @soc: DP soc handle
  2604. * @vdev_id: id of DP vdev handle
  2605. * @nbuf: skb
  2606. *
  2607. * Entry point for Core Tx layer (DP_TX) invoked from
  2608. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2609. * cases
  2610. *
  2611. * Return: NULL on success,
  2612. * nbuf when it fails to send
  2613. */
  2614. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2615. qdf_nbuf_t nbuf)
  2616. {
  2617. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2618. uint16_t peer_id = HTT_INVALID_PEER;
  2619. /*
  2620. * doing a memzero is causing additional function call overhead
  2621. * so doing static stack clearing
  2622. */
  2623. struct dp_tx_msdu_info_s msdu_info = {0};
  2624. struct dp_vdev *vdev = NULL;
  2625. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2626. return nbuf;
  2627. /*
  2628. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2629. * this in per packet path.
  2630. *
  2631. * As in this path vdev memory is already protected with netdev
  2632. * tx lock
  2633. */
  2634. vdev = soc->vdev_id_map[vdev_id];
  2635. if (qdf_unlikely(!vdev))
  2636. return nbuf;
  2637. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2638. QDF_MAC_ADDR_REF(nbuf->data));
  2639. /*
  2640. * Set Default Host TID value to invalid TID
  2641. * (TID override disabled)
  2642. */
  2643. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2644. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2645. if (qdf_unlikely(vdev->mesh_vdev)) {
  2646. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2647. &msdu_info);
  2648. if (!nbuf_mesh) {
  2649. dp_verbose_debug("Extracting mesh metadata failed");
  2650. return nbuf;
  2651. }
  2652. nbuf = nbuf_mesh;
  2653. }
  2654. /*
  2655. * Get HW Queue to use for this frame.
  2656. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2657. * dedicated for data and 1 for command.
  2658. * "queue_id" maps to one hardware ring.
  2659. * With each ring, we also associate a unique Tx descriptor pool
  2660. * to minimize lock contention for these resources.
  2661. */
  2662. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2663. /*
  2664. * TCL H/W supports 2 DSCP-TID mapping tables.
  2665. * Table 1 - Default DSCP-TID mapping table
  2666. * Table 2 - 1 DSCP-TID override table
  2667. *
  2668. * If we need a different DSCP-TID mapping for this vap,
  2669. * call tid_classify to extract DSCP/ToS from frame and
  2670. * map to a TID and store in msdu_info. This is later used
  2671. * to fill in TCL Input descriptor (per-packet TID override).
  2672. */
  2673. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2674. /*
  2675. * Classify the frame and call corresponding
  2676. * "prepare" function which extracts the segment (TSO)
  2677. * and fragmentation information (for TSO , SG, ME, or Raw)
  2678. * into MSDU_INFO structure which is later used to fill
  2679. * SW and HW descriptors.
  2680. */
  2681. if (qdf_nbuf_is_tso(nbuf)) {
  2682. dp_verbose_debug("TSO frame %pK", vdev);
  2683. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2684. qdf_nbuf_len(nbuf));
  2685. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2686. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2687. qdf_nbuf_len(nbuf));
  2688. return nbuf;
  2689. }
  2690. goto send_multiple;
  2691. }
  2692. /* SG */
  2693. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2694. struct dp_tx_seg_info_s seg_info = {0};
  2695. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2696. if (!nbuf)
  2697. return NULL;
  2698. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2699. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2700. qdf_nbuf_len(nbuf));
  2701. goto send_multiple;
  2702. }
  2703. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2704. return NULL;
  2705. /* RAW */
  2706. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2707. struct dp_tx_seg_info_s seg_info = {0};
  2708. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2709. if (!nbuf)
  2710. return NULL;
  2711. dp_verbose_debug("Raw frame %pK", vdev);
  2712. goto send_multiple;
  2713. }
  2714. if (qdf_unlikely(vdev->nawds_enabled)) {
  2715. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2716. qdf_nbuf_data(nbuf);
  2717. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2718. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2719. peer_id = DP_INVALID_PEER;
  2720. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2721. 1, qdf_nbuf_len(nbuf));
  2722. }
  2723. /* Single linear frame */
  2724. /*
  2725. * If nbuf is a simple linear frame, use send_single function to
  2726. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2727. * SRNG. There is no need to setup a MSDU extension descriptor.
  2728. */
  2729. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2730. return nbuf;
  2731. send_multiple:
  2732. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2733. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2734. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2735. return nbuf;
  2736. }
  2737. /**
  2738. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2739. * case to vaoid check in perpkt path.
  2740. * @soc: DP soc handle
  2741. * @vdev_id: id of DP vdev handle
  2742. * @nbuf: skb
  2743. *
  2744. * Entry point for Core Tx layer (DP_TX) invoked from
  2745. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2746. * with special condition to avoid per pkt check in dp_tx_send
  2747. *
  2748. * Return: NULL on success,
  2749. * nbuf when it fails to send
  2750. */
  2751. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2752. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2753. {
  2754. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2755. struct dp_vdev *vdev = NULL;
  2756. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2757. return nbuf;
  2758. /*
  2759. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2760. * this in per packet path.
  2761. *
  2762. * As in this path vdev memory is already protected with netdev
  2763. * tx lock
  2764. */
  2765. vdev = soc->vdev_id_map[vdev_id];
  2766. if (qdf_unlikely(!vdev))
  2767. return nbuf;
  2768. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2769. == QDF_STATUS_E_FAILURE)) {
  2770. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2771. return nbuf;
  2772. }
  2773. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2774. }
  2775. /**
  2776. * dp_tx_reinject_handler() - Tx Reinject Handler
  2777. * @soc: datapath soc handle
  2778. * @vdev: datapath vdev handle
  2779. * @tx_desc: software descriptor head pointer
  2780. * @status : Tx completion status from HTT descriptor
  2781. *
  2782. * This function reinjects frames back to Target.
  2783. * Todo - Host queue needs to be added
  2784. *
  2785. * Return: none
  2786. */
  2787. static
  2788. void dp_tx_reinject_handler(struct dp_soc *soc,
  2789. struct dp_vdev *vdev,
  2790. struct dp_tx_desc_s *tx_desc,
  2791. uint8_t *status)
  2792. {
  2793. struct dp_peer *peer = NULL;
  2794. uint32_t peer_id = HTT_INVALID_PEER;
  2795. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2796. qdf_nbuf_t nbuf_copy = NULL;
  2797. struct dp_tx_msdu_info_s msdu_info;
  2798. #ifdef WDS_VENDOR_EXTENSION
  2799. int is_mcast = 0, is_ucast = 0;
  2800. int num_peers_3addr = 0;
  2801. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2802. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2803. #endif
  2804. qdf_assert(vdev);
  2805. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2806. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2807. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2808. "%s Tx reinject path", __func__);
  2809. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2810. qdf_nbuf_len(tx_desc->nbuf));
  2811. #ifdef WDS_VENDOR_EXTENSION
  2812. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2813. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2814. } else {
  2815. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2816. }
  2817. is_ucast = !is_mcast;
  2818. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2819. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2820. if (peer->bss_peer)
  2821. continue;
  2822. /* Detect wds peers that use 3-addr framing for mcast.
  2823. * if there are any, the bss_peer is used to send the
  2824. * the mcast frame using 3-addr format. all wds enabled
  2825. * peers that use 4-addr framing for mcast frames will
  2826. * be duplicated and sent as 4-addr frames below.
  2827. */
  2828. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2829. num_peers_3addr = 1;
  2830. break;
  2831. }
  2832. }
  2833. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2834. #endif
  2835. if (qdf_unlikely(vdev->mesh_vdev)) {
  2836. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2837. } else {
  2838. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2839. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2840. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2841. #ifdef WDS_VENDOR_EXTENSION
  2842. /*
  2843. * . if 3-addr STA, then send on BSS Peer
  2844. * . if Peer WDS enabled and accept 4-addr mcast,
  2845. * send mcast on that peer only
  2846. * . if Peer WDS enabled and accept 4-addr ucast,
  2847. * send ucast on that peer only
  2848. */
  2849. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2850. (peer->wds_enabled &&
  2851. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2852. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2853. #else
  2854. ((peer->bss_peer &&
  2855. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2856. #endif
  2857. peer_id = DP_INVALID_PEER;
  2858. nbuf_copy = qdf_nbuf_copy(nbuf);
  2859. if (!nbuf_copy) {
  2860. QDF_TRACE(QDF_MODULE_ID_DP,
  2861. QDF_TRACE_LEVEL_DEBUG,
  2862. FL("nbuf copy failed"));
  2863. break;
  2864. }
  2865. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2866. nbuf_copy,
  2867. &msdu_info,
  2868. peer_id,
  2869. NULL);
  2870. if (nbuf_copy) {
  2871. QDF_TRACE(QDF_MODULE_ID_DP,
  2872. QDF_TRACE_LEVEL_DEBUG,
  2873. FL("pkt send failed"));
  2874. qdf_nbuf_free(nbuf_copy);
  2875. }
  2876. }
  2877. }
  2878. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2879. }
  2880. qdf_nbuf_free(nbuf);
  2881. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2882. }
  2883. /**
  2884. * dp_tx_inspect_handler() - Tx Inspect Handler
  2885. * @soc: datapath soc handle
  2886. * @vdev: datapath vdev handle
  2887. * @tx_desc: software descriptor head pointer
  2888. * @status : Tx completion status from HTT descriptor
  2889. *
  2890. * Handles Tx frames sent back to Host for inspection
  2891. * (ProxyARP)
  2892. *
  2893. * Return: none
  2894. */
  2895. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2896. struct dp_vdev *vdev,
  2897. struct dp_tx_desc_s *tx_desc,
  2898. uint8_t *status)
  2899. {
  2900. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2901. "%s Tx inspect path",
  2902. __func__);
  2903. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2904. qdf_nbuf_len(tx_desc->nbuf));
  2905. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2906. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2907. }
  2908. #ifdef MESH_MODE_SUPPORT
  2909. /**
  2910. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2911. * in mesh meta header
  2912. * @tx_desc: software descriptor head pointer
  2913. * @ts: pointer to tx completion stats
  2914. * Return: none
  2915. */
  2916. static
  2917. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2918. struct hal_tx_completion_status *ts)
  2919. {
  2920. struct meta_hdr_s *mhdr;
  2921. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2922. if (!tx_desc->msdu_ext_desc) {
  2923. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2924. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2925. "netbuf %pK offset %d",
  2926. netbuf, tx_desc->pkt_offset);
  2927. return;
  2928. }
  2929. }
  2930. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2932. "netbuf %pK offset %lu", netbuf,
  2933. sizeof(struct meta_hdr_s));
  2934. return;
  2935. }
  2936. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2937. mhdr->rssi = ts->ack_frame_rssi;
  2938. mhdr->band = tx_desc->pdev->operating_channel.band;
  2939. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2940. }
  2941. #else
  2942. static
  2943. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2944. struct hal_tx_completion_status *ts)
  2945. {
  2946. }
  2947. #endif
  2948. #ifdef QCA_PEER_EXT_STATS
  2949. /*
  2950. * dp_tx_compute_tid_delay() - Compute per TID delay
  2951. * @stats: Per TID delay stats
  2952. * @tx_desc: Software Tx descriptor
  2953. *
  2954. * Compute the software enqueue and hw enqueue delays and
  2955. * update the respective histograms
  2956. *
  2957. * Return: void
  2958. */
  2959. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2960. struct dp_tx_desc_s *tx_desc)
  2961. {
  2962. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2963. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2964. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2965. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2966. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2967. timestamp_hw_enqueue = tx_desc->timestamp;
  2968. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2969. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2970. timestamp_hw_enqueue);
  2971. /*
  2972. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2973. */
  2974. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2975. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2976. }
  2977. /*
  2978. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2979. * @peer: DP peer context
  2980. * @tx_desc: Tx software descriptor
  2981. * @tid: Transmission ID
  2982. * @ring_id: Rx CPU context ID/CPU_ID
  2983. *
  2984. * Update the peer extended stats. These are enhanced other
  2985. * delay stats per msdu level.
  2986. *
  2987. * Return: void
  2988. */
  2989. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2990. struct dp_tx_desc_s *tx_desc,
  2991. uint8_t tid, uint8_t ring_id)
  2992. {
  2993. struct dp_pdev *pdev = peer->vdev->pdev;
  2994. struct dp_soc *soc = NULL;
  2995. struct cdp_peer_ext_stats *pext_stats = NULL;
  2996. soc = pdev->soc;
  2997. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2998. return;
  2999. pext_stats = peer->pext_stats;
  3000. qdf_assert(pext_stats);
  3001. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3002. /*
  3003. * For non-TID packets use the TID 9
  3004. */
  3005. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3006. tid = CDP_MAX_DATA_TIDS - 1;
  3007. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3008. tx_desc);
  3009. }
  3010. #else
  3011. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3012. struct dp_tx_desc_s *tx_desc,
  3013. uint8_t tid, uint8_t ring_id)
  3014. {
  3015. }
  3016. #endif
  3017. /**
  3018. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3019. * to pass in correct fields
  3020. *
  3021. * @vdev: pdev handle
  3022. * @tx_desc: tx descriptor
  3023. * @tid: tid value
  3024. * @ring_id: TCL or WBM ring number for transmit path
  3025. * Return: none
  3026. */
  3027. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3028. struct dp_tx_desc_s *tx_desc,
  3029. uint8_t tid, uint8_t ring_id)
  3030. {
  3031. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3032. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3033. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3034. return;
  3035. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3036. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3037. timestamp_hw_enqueue = tx_desc->timestamp;
  3038. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3039. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3040. timestamp_hw_enqueue);
  3041. interframe_delay = (uint32_t)(timestamp_ingress -
  3042. vdev->prev_tx_enq_tstamp);
  3043. /*
  3044. * Delay in software enqueue
  3045. */
  3046. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3047. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3048. /*
  3049. * Delay between packet enqueued to HW and Tx completion
  3050. */
  3051. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3052. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3053. /*
  3054. * Update interframe delay stats calculated at hardstart receive point.
  3055. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3056. * interframe delay will not be calculate correctly for 1st frame.
  3057. * On the other side, this will help in avoiding extra per packet check
  3058. * of !vdev->prev_tx_enq_tstamp.
  3059. */
  3060. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3061. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3062. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3063. }
  3064. #ifdef DISABLE_DP_STATS
  3065. static
  3066. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3067. {
  3068. }
  3069. #else
  3070. static
  3071. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3072. {
  3073. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3074. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3075. if (subtype != QDF_PROTO_INVALID)
  3076. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3077. }
  3078. #endif
  3079. /**
  3080. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3081. * per wbm ring
  3082. *
  3083. * @tx_desc: software descriptor head pointer
  3084. * @ts: Tx completion status
  3085. * @peer: peer handle
  3086. * @ring_id: ring number
  3087. *
  3088. * Return: None
  3089. */
  3090. static inline void
  3091. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3092. struct hal_tx_completion_status *ts,
  3093. struct dp_peer *peer, uint8_t ring_id)
  3094. {
  3095. struct dp_pdev *pdev = peer->vdev->pdev;
  3096. struct dp_soc *soc = NULL;
  3097. uint8_t mcs, pkt_type;
  3098. uint8_t tid = ts->tid;
  3099. uint32_t length;
  3100. struct cdp_tid_tx_stats *tid_stats;
  3101. if (!pdev)
  3102. return;
  3103. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3104. tid = CDP_MAX_DATA_TIDS - 1;
  3105. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3106. soc = pdev->soc;
  3107. mcs = ts->mcs;
  3108. pkt_type = ts->pkt_type;
  3109. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3110. dp_err("Release source is not from TQM");
  3111. return;
  3112. }
  3113. length = qdf_nbuf_len(tx_desc->nbuf);
  3114. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3115. if (qdf_unlikely(pdev->delay_stats_flag))
  3116. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3117. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3118. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3119. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3120. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3121. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3122. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3123. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3124. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3125. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3126. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3127. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3128. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3129. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3130. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3131. /*
  3132. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3133. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3134. * are no completions for failed cases. Hence updating tx_failed from
  3135. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3136. * then this has to be removed
  3137. */
  3138. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3139. peer->stats.tx.dropped.fw_rem_notx +
  3140. peer->stats.tx.dropped.fw_rem_tx +
  3141. peer->stats.tx.dropped.age_out +
  3142. peer->stats.tx.dropped.fw_reason1 +
  3143. peer->stats.tx.dropped.fw_reason2 +
  3144. peer->stats.tx.dropped.fw_reason3;
  3145. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3146. tid_stats->tqm_status_cnt[ts->status]++;
  3147. }
  3148. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3149. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3150. return;
  3151. }
  3152. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3153. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3154. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3155. /*
  3156. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3157. * Return from here if HTT PPDU events are enabled.
  3158. */
  3159. if (!(soc->process_tx_status))
  3160. return;
  3161. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3162. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3163. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3164. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3165. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3166. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3167. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3168. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3169. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3170. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3171. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3172. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3173. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3174. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3175. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3176. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3177. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3178. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3179. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3180. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3181. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3182. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3183. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3184. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3185. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3186. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3187. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3188. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3189. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3190. &peer->stats, ts->peer_id,
  3191. UPDATE_PEER_STATS, pdev->pdev_id);
  3192. #endif
  3193. }
  3194. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3195. /**
  3196. * dp_tx_flow_pool_lock() - take flow pool lock
  3197. * @soc: core txrx main context
  3198. * @tx_desc: tx desc
  3199. *
  3200. * Return: None
  3201. */
  3202. static inline
  3203. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3204. struct dp_tx_desc_s *tx_desc)
  3205. {
  3206. struct dp_tx_desc_pool_s *pool;
  3207. uint8_t desc_pool_id;
  3208. desc_pool_id = tx_desc->pool_id;
  3209. pool = &soc->tx_desc[desc_pool_id];
  3210. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3211. }
  3212. /**
  3213. * dp_tx_flow_pool_unlock() - release flow pool lock
  3214. * @soc: core txrx main context
  3215. * @tx_desc: tx desc
  3216. *
  3217. * Return: None
  3218. */
  3219. static inline
  3220. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3221. struct dp_tx_desc_s *tx_desc)
  3222. {
  3223. struct dp_tx_desc_pool_s *pool;
  3224. uint8_t desc_pool_id;
  3225. desc_pool_id = tx_desc->pool_id;
  3226. pool = &soc->tx_desc[desc_pool_id];
  3227. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3228. }
  3229. #else
  3230. static inline
  3231. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3232. {
  3233. }
  3234. static inline
  3235. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3236. {
  3237. }
  3238. #endif
  3239. /**
  3240. * dp_tx_notify_completion() - Notify tx completion for this desc
  3241. * @soc: core txrx main context
  3242. * @vdev: datapath vdev handle
  3243. * @tx_desc: tx desc
  3244. * @netbuf: buffer
  3245. * @status: tx status
  3246. *
  3247. * Return: none
  3248. */
  3249. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3250. struct dp_vdev *vdev,
  3251. struct dp_tx_desc_s *tx_desc,
  3252. qdf_nbuf_t netbuf,
  3253. uint8_t status)
  3254. {
  3255. void *osif_dev;
  3256. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3257. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3258. qdf_assert(tx_desc);
  3259. dp_tx_flow_pool_lock(soc, tx_desc);
  3260. if (!vdev ||
  3261. !vdev->osif_vdev) {
  3262. dp_tx_flow_pool_unlock(soc, tx_desc);
  3263. return;
  3264. }
  3265. osif_dev = vdev->osif_vdev;
  3266. tx_compl_cbk = vdev->tx_comp;
  3267. dp_tx_flow_pool_unlock(soc, tx_desc);
  3268. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3269. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3270. if (tx_compl_cbk)
  3271. tx_compl_cbk(netbuf, osif_dev, flag);
  3272. }
  3273. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3274. * @pdev: pdev handle
  3275. * @tid: tid value
  3276. * @txdesc_ts: timestamp from txdesc
  3277. * @ppdu_id: ppdu id
  3278. *
  3279. * Return: none
  3280. */
  3281. #ifdef FEATURE_PERPKT_INFO
  3282. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3283. struct dp_peer *peer,
  3284. uint8_t tid,
  3285. uint64_t txdesc_ts,
  3286. uint32_t ppdu_id)
  3287. {
  3288. uint64_t delta_ms;
  3289. struct cdp_tx_sojourn_stats *sojourn_stats;
  3290. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3291. return;
  3292. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3293. tid >= CDP_DATA_TID_MAX))
  3294. return;
  3295. if (qdf_unlikely(!pdev->sojourn_buf))
  3296. return;
  3297. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3298. qdf_nbuf_data(pdev->sojourn_buf);
  3299. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3300. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3301. txdesc_ts;
  3302. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3303. delta_ms);
  3304. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3305. sojourn_stats->num_msdus[tid] = 1;
  3306. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3307. peer->avg_sojourn_msdu[tid].internal;
  3308. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3309. pdev->sojourn_buf, HTT_INVALID_PEER,
  3310. WDI_NO_VAL, pdev->pdev_id);
  3311. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3312. sojourn_stats->num_msdus[tid] = 0;
  3313. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3314. }
  3315. #else
  3316. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3317. struct dp_peer *peer,
  3318. uint8_t tid,
  3319. uint64_t txdesc_ts,
  3320. uint32_t ppdu_id)
  3321. {
  3322. }
  3323. #endif
  3324. #ifdef WLAN_FEATURE_PKT_CAPTURE_LITHIUM
  3325. /**
  3326. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3327. * @soc: dp_soc handle
  3328. * @desc: Tx Descriptor
  3329. * @ts: HAL Tx completion descriptor contents
  3330. *
  3331. * This function is used to send tx completion to packet capture
  3332. */
  3333. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3334. struct dp_tx_desc_s *desc,
  3335. struct hal_tx_completion_status *ts)
  3336. {
  3337. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3338. desc, ts->peer_id,
  3339. WDI_NO_VAL, desc->pdev->pdev_id);
  3340. }
  3341. #endif
  3342. /**
  3343. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3344. * @soc: DP Soc handle
  3345. * @tx_desc: software Tx descriptor
  3346. * @ts : Tx completion status from HAL/HTT descriptor
  3347. *
  3348. * Return: none
  3349. */
  3350. static inline void
  3351. dp_tx_comp_process_desc(struct dp_soc *soc,
  3352. struct dp_tx_desc_s *desc,
  3353. struct hal_tx_completion_status *ts,
  3354. struct dp_peer *peer)
  3355. {
  3356. uint64_t time_latency = 0;
  3357. /*
  3358. * m_copy/tx_capture modes are not supported for
  3359. * scatter gather packets
  3360. */
  3361. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3362. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3363. desc->timestamp);
  3364. }
  3365. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3366. if (!(desc->msdu_ext_desc)) {
  3367. if (QDF_STATUS_SUCCESS ==
  3368. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3369. return;
  3370. }
  3371. if (QDF_STATUS_SUCCESS ==
  3372. dp_get_completion_indication_for_stack(soc,
  3373. desc->pdev,
  3374. peer, ts,
  3375. desc->nbuf,
  3376. time_latency)) {
  3377. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3378. QDF_DMA_TO_DEVICE,
  3379. desc->nbuf->len);
  3380. dp_send_completion_to_stack(soc,
  3381. desc->pdev,
  3382. ts->peer_id,
  3383. ts->ppdu_id,
  3384. desc->nbuf);
  3385. return;
  3386. }
  3387. }
  3388. dp_tx_comp_free_buf(soc, desc);
  3389. }
  3390. #ifdef DISABLE_DP_STATS
  3391. /**
  3392. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3393. * @soc: core txrx main context
  3394. * @tx_desc: tx desc
  3395. * @status: tx status
  3396. *
  3397. * Return: none
  3398. */
  3399. static inline
  3400. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3401. struct dp_vdev *vdev,
  3402. struct dp_tx_desc_s *tx_desc,
  3403. uint8_t status)
  3404. {
  3405. }
  3406. #else
  3407. static inline
  3408. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3409. struct dp_vdev *vdev,
  3410. struct dp_tx_desc_s *tx_desc,
  3411. uint8_t status)
  3412. {
  3413. void *osif_dev;
  3414. ol_txrx_stats_rx_fp stats_cbk;
  3415. uint8_t pkt_type;
  3416. qdf_assert(tx_desc);
  3417. if (!vdev ||
  3418. !vdev->osif_vdev ||
  3419. !vdev->stats_cb)
  3420. return;
  3421. osif_dev = vdev->osif_vdev;
  3422. stats_cbk = vdev->stats_cb;
  3423. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3424. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3425. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3426. &pkt_type);
  3427. }
  3428. #endif
  3429. /**
  3430. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3431. * @soc: DP soc handle
  3432. * @tx_desc: software descriptor head pointer
  3433. * @ts: Tx completion status
  3434. * @peer: peer handle
  3435. * @ring_id: ring number
  3436. *
  3437. * Return: none
  3438. */
  3439. static inline
  3440. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3441. struct dp_tx_desc_s *tx_desc,
  3442. struct hal_tx_completion_status *ts,
  3443. struct dp_peer *peer, uint8_t ring_id)
  3444. {
  3445. uint32_t length;
  3446. qdf_ether_header_t *eh;
  3447. struct dp_vdev *vdev = NULL;
  3448. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3449. enum qdf_dp_tx_rx_status dp_status;
  3450. if (!nbuf) {
  3451. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3452. goto out;
  3453. }
  3454. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3455. length = qdf_nbuf_len(nbuf);
  3456. dp_status = dp_tx_hw_to_qdf(ts->status);
  3457. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3458. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3459. QDF_TRACE_DEFAULT_PDEV_ID,
  3460. qdf_nbuf_data_addr(nbuf),
  3461. sizeof(qdf_nbuf_data(nbuf)),
  3462. tx_desc->id, ts->status, dp_status));
  3463. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3464. "-------------------- \n"
  3465. "Tx Completion Stats: \n"
  3466. "-------------------- \n"
  3467. "ack_frame_rssi = %d \n"
  3468. "first_msdu = %d \n"
  3469. "last_msdu = %d \n"
  3470. "msdu_part_of_amsdu = %d \n"
  3471. "rate_stats valid = %d \n"
  3472. "bw = %d \n"
  3473. "pkt_type = %d \n"
  3474. "stbc = %d \n"
  3475. "ldpc = %d \n"
  3476. "sgi = %d \n"
  3477. "mcs = %d \n"
  3478. "ofdma = %d \n"
  3479. "tones_in_ru = %d \n"
  3480. "tsf = %d \n"
  3481. "ppdu_id = %d \n"
  3482. "transmit_cnt = %d \n"
  3483. "tid = %d \n"
  3484. "peer_id = %d\n",
  3485. ts->ack_frame_rssi, ts->first_msdu,
  3486. ts->last_msdu, ts->msdu_part_of_amsdu,
  3487. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3488. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3489. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3490. ts->transmit_cnt, ts->tid, ts->peer_id);
  3491. /* Update SoC level stats */
  3492. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3493. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3494. if (!peer) {
  3495. dp_info_rl("peer is null or deletion in progress");
  3496. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3497. goto out;
  3498. }
  3499. vdev = peer->vdev;
  3500. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3501. /* Update per-packet stats for mesh mode */
  3502. if (qdf_unlikely(vdev->mesh_vdev) &&
  3503. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3504. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3505. /* Update peer level stats */
  3506. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3507. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3508. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3509. if ((peer->vdev->tx_encap_type ==
  3510. htt_cmn_pkt_type_ethernet) &&
  3511. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3512. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3513. }
  3514. }
  3515. } else {
  3516. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3517. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3518. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3519. if (qdf_unlikely(peer->in_twt)) {
  3520. DP_STATS_INC_PKT(peer,
  3521. tx.tx_success_twt,
  3522. 1, length);
  3523. }
  3524. }
  3525. }
  3526. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3527. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3528. #ifdef QCA_SUPPORT_RDK_STATS
  3529. if (soc->rdkstats_enabled)
  3530. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3531. tx_desc->timestamp,
  3532. ts->ppdu_id);
  3533. #endif
  3534. out:
  3535. return;
  3536. }
  3537. /**
  3538. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3539. * @soc: core txrx main context
  3540. * @comp_head: software descriptor head pointer
  3541. * @ring_id: ring number
  3542. *
  3543. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3544. * and release the software descriptors after processing is complete
  3545. *
  3546. * Return: none
  3547. */
  3548. static void
  3549. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3550. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3551. {
  3552. struct dp_tx_desc_s *desc;
  3553. struct dp_tx_desc_s *next;
  3554. struct hal_tx_completion_status ts;
  3555. struct dp_peer *peer = NULL;
  3556. uint16_t peer_id = DP_INVALID_PEER;
  3557. qdf_nbuf_t netbuf;
  3558. desc = comp_head;
  3559. while (desc) {
  3560. if (peer_id != desc->peer_id) {
  3561. if (peer)
  3562. dp_peer_unref_delete(peer,
  3563. DP_MOD_ID_TX_COMP);
  3564. peer_id = desc->peer_id;
  3565. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3566. DP_MOD_ID_TX_COMP);
  3567. }
  3568. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3569. struct dp_pdev *pdev = desc->pdev;
  3570. if (qdf_likely(peer)) {
  3571. /*
  3572. * Increment peer statistics
  3573. * Minimal statistics update done here
  3574. */
  3575. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3576. desc->length);
  3577. if (desc->tx_status !=
  3578. HAL_TX_TQM_RR_FRAME_ACKED)
  3579. DP_STATS_INC(peer, tx.tx_failed, 1);
  3580. }
  3581. qdf_assert(pdev);
  3582. dp_tx_outstanding_dec(pdev);
  3583. /*
  3584. * Calling a QDF WRAPPER here is creating signifcant
  3585. * performance impact so avoided the wrapper call here
  3586. */
  3587. next = desc->next;
  3588. qdf_mem_unmap_nbytes_single(soc->osdev,
  3589. desc->dma_addr,
  3590. QDF_DMA_TO_DEVICE,
  3591. desc->length);
  3592. qdf_nbuf_free(desc->nbuf);
  3593. dp_tx_desc_free(soc, desc, desc->pool_id);
  3594. desc = next;
  3595. continue;
  3596. }
  3597. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3598. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3599. netbuf = desc->nbuf;
  3600. /* check tx complete notification */
  3601. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3602. dp_tx_notify_completion(soc, peer->vdev, desc,
  3603. netbuf, ts.status);
  3604. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3605. next = desc->next;
  3606. dp_tx_desc_release(desc, desc->pool_id);
  3607. desc = next;
  3608. }
  3609. if (peer)
  3610. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3611. }
  3612. /**
  3613. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3614. * @soc: Handle to DP soc structure
  3615. * @tx_desc: software descriptor head pointer
  3616. * @status : Tx completion status from HTT descriptor
  3617. * @ring_id: ring number
  3618. *
  3619. * This function will process HTT Tx indication messages from Target
  3620. *
  3621. * Return: none
  3622. */
  3623. static
  3624. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3625. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3626. uint8_t ring_id)
  3627. {
  3628. uint8_t tx_status;
  3629. struct dp_pdev *pdev;
  3630. struct dp_vdev *vdev;
  3631. struct hal_tx_completion_status ts = {0};
  3632. uint32_t *htt_desc = (uint32_t *)status;
  3633. struct dp_peer *peer;
  3634. struct cdp_tid_tx_stats *tid_stats = NULL;
  3635. struct htt_soc *htt_handle;
  3636. uint8_t vdev_id;
  3637. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3638. htt_handle = (struct htt_soc *)soc->htt_handle;
  3639. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3640. /*
  3641. * There can be scenario where WBM consuming descriptor enqueued
  3642. * from TQM2WBM first and TQM completion can happen before MEC
  3643. * notification comes from FW2WBM. Avoid access any field of tx
  3644. * descriptor in case of MEC notify.
  3645. */
  3646. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3647. /*
  3648. * Get vdev id from HTT status word in case of MEC
  3649. * notification
  3650. */
  3651. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3652. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3653. return;
  3654. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3655. DP_MOD_ID_HTT_COMP);
  3656. if (!vdev)
  3657. return;
  3658. dp_tx_mec_handler(vdev, status);
  3659. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3660. return;
  3661. }
  3662. /*
  3663. * If the descriptor is already freed in vdev_detach,
  3664. * continue to next descriptor
  3665. */
  3666. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3667. QDF_TRACE(QDF_MODULE_ID_DP,
  3668. QDF_TRACE_LEVEL_INFO,
  3669. "Descriptor freed in vdev_detach %d",
  3670. tx_desc->id);
  3671. return;
  3672. }
  3673. pdev = tx_desc->pdev;
  3674. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3675. QDF_TRACE(QDF_MODULE_ID_DP,
  3676. QDF_TRACE_LEVEL_INFO,
  3677. "pdev in down state %d",
  3678. tx_desc->id);
  3679. dp_tx_comp_free_buf(soc, tx_desc);
  3680. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3681. return;
  3682. }
  3683. qdf_assert(tx_desc->pdev);
  3684. vdev_id = tx_desc->vdev_id;
  3685. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3686. DP_MOD_ID_HTT_COMP);
  3687. if (!vdev)
  3688. return;
  3689. switch (tx_status) {
  3690. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3691. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3692. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3693. {
  3694. uint8_t tid;
  3695. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3696. ts.peer_id =
  3697. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3698. htt_desc[2]);
  3699. ts.tid =
  3700. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3701. htt_desc[2]);
  3702. } else {
  3703. ts.peer_id = HTT_INVALID_PEER;
  3704. ts.tid = HTT_INVALID_TID;
  3705. }
  3706. ts.ppdu_id =
  3707. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3708. htt_desc[1]);
  3709. ts.ack_frame_rssi =
  3710. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3711. htt_desc[1]);
  3712. ts.tsf = htt_desc[3];
  3713. ts.first_msdu = 1;
  3714. ts.last_msdu = 1;
  3715. tid = ts.tid;
  3716. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3717. tid = CDP_MAX_DATA_TIDS - 1;
  3718. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3719. if (qdf_unlikely(pdev->delay_stats_flag))
  3720. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3721. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3722. tid_stats->htt_status_cnt[tx_status]++;
  3723. }
  3724. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3725. DP_MOD_ID_HTT_COMP);
  3726. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3727. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3728. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3729. if (qdf_likely(peer))
  3730. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3731. break;
  3732. }
  3733. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3734. {
  3735. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3736. break;
  3737. }
  3738. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3739. {
  3740. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3741. break;
  3742. }
  3743. default:
  3744. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3745. "%s Invalid HTT tx_status %d\n",
  3746. __func__, tx_status);
  3747. break;
  3748. }
  3749. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3750. }
  3751. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3752. static inline
  3753. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3754. {
  3755. bool limit_hit = false;
  3756. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3757. limit_hit =
  3758. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3759. if (limit_hit)
  3760. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3761. return limit_hit;
  3762. }
  3763. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3764. {
  3765. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3766. }
  3767. #else
  3768. static inline
  3769. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3770. {
  3771. return false;
  3772. }
  3773. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3774. {
  3775. return false;
  3776. }
  3777. #endif
  3778. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3779. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3780. uint32_t quota)
  3781. {
  3782. void *tx_comp_hal_desc;
  3783. uint8_t buffer_src;
  3784. uint8_t pool_id;
  3785. uint32_t tx_desc_id;
  3786. struct dp_tx_desc_s *tx_desc = NULL;
  3787. struct dp_tx_desc_s *head_desc = NULL;
  3788. struct dp_tx_desc_s *tail_desc = NULL;
  3789. uint32_t num_processed = 0;
  3790. uint32_t count;
  3791. uint32_t num_avail_for_reap = 0;
  3792. bool force_break = false;
  3793. DP_HIST_INIT();
  3794. more_data:
  3795. /* Re-initialize local variables to be re-used */
  3796. head_desc = NULL;
  3797. tail_desc = NULL;
  3798. count = 0;
  3799. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3800. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3801. return 0;
  3802. }
  3803. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3804. if (num_avail_for_reap >= quota)
  3805. num_avail_for_reap = quota;
  3806. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3807. /* Find head descriptor from completion ring */
  3808. while (qdf_likely(num_avail_for_reap)) {
  3809. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3810. if (qdf_unlikely(!tx_comp_hal_desc))
  3811. break;
  3812. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3813. /* If this buffer was not released by TQM or FW, then it is not
  3814. * Tx completion indication, assert */
  3815. if (qdf_unlikely(buffer_src !=
  3816. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3817. (qdf_unlikely(buffer_src !=
  3818. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3819. uint8_t wbm_internal_error;
  3820. dp_err_rl(
  3821. "Tx comp release_src != TQM | FW but from %d",
  3822. buffer_src);
  3823. hal_dump_comp_desc(tx_comp_hal_desc);
  3824. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3825. /* When WBM sees NULL buffer_addr_info in any of
  3826. * ingress rings it sends an error indication,
  3827. * with wbm_internal_error=1, to a specific ring.
  3828. * The WBM2SW ring used to indicate these errors is
  3829. * fixed in HW, and that ring is being used as Tx
  3830. * completion ring. These errors are not related to
  3831. * Tx completions, and should just be ignored
  3832. */
  3833. wbm_internal_error = hal_get_wbm_internal_error(
  3834. soc->hal_soc,
  3835. tx_comp_hal_desc);
  3836. if (wbm_internal_error) {
  3837. dp_err_rl("Tx comp wbm_internal_error!!");
  3838. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3839. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3840. buffer_src)
  3841. dp_handle_wbm_internal_error(
  3842. soc,
  3843. tx_comp_hal_desc,
  3844. hal_tx_comp_get_buffer_type(
  3845. tx_comp_hal_desc));
  3846. } else {
  3847. dp_err_rl("Tx comp wbm_internal_error false");
  3848. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3849. }
  3850. continue;
  3851. }
  3852. /* Get descriptor id */
  3853. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3854. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3855. DP_TX_DESC_ID_POOL_OS;
  3856. /* Find Tx descriptor */
  3857. tx_desc = dp_tx_desc_find(soc, pool_id,
  3858. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3859. DP_TX_DESC_ID_PAGE_OS,
  3860. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3861. DP_TX_DESC_ID_OFFSET_OS);
  3862. /*
  3863. * If the release source is FW, process the HTT status
  3864. */
  3865. if (qdf_unlikely(buffer_src ==
  3866. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3867. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3868. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3869. htt_tx_status);
  3870. dp_tx_process_htt_completion(soc, tx_desc,
  3871. htt_tx_status, ring_id);
  3872. } else {
  3873. tx_desc->peer_id =
  3874. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3875. tx_desc->tx_status =
  3876. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3877. /*
  3878. * If the fast completion mode is enabled extended
  3879. * metadata from descriptor is not copied
  3880. */
  3881. if (qdf_likely(tx_desc->flags &
  3882. DP_TX_DESC_FLAG_SIMPLE))
  3883. goto add_to_pool;
  3884. /*
  3885. * If the descriptor is already freed in vdev_detach,
  3886. * continue to next descriptor
  3887. */
  3888. if (qdf_unlikely
  3889. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3890. !tx_desc->flags)) {
  3891. dp_tx_comp_info("Descriptor freed in vdev_detach %d",
  3892. tx_desc_id);
  3893. continue;
  3894. }
  3895. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3896. dp_tx_comp_info("pdev in down state %d",
  3897. tx_desc_id);
  3898. dp_tx_comp_free_buf(soc, tx_desc);
  3899. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3900. goto next_desc;
  3901. }
  3902. /* Pool id is not matching. Error */
  3903. if (tx_desc->pool_id != pool_id) {
  3904. dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
  3905. pool_id, tx_desc->pool_id);
  3906. qdf_assert_always(0);
  3907. }
  3908. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3909. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3910. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  3911. tx_desc->flags, tx_desc_id);
  3912. qdf_assert_always(0);
  3913. }
  3914. /* Collect hw completion contents */
  3915. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3916. &tx_desc->comp, 1);
  3917. add_to_pool:
  3918. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3919. /* First ring descriptor on the cycle */
  3920. if (!head_desc) {
  3921. head_desc = tx_desc;
  3922. tail_desc = tx_desc;
  3923. }
  3924. tail_desc->next = tx_desc;
  3925. tx_desc->next = NULL;
  3926. tail_desc = tx_desc;
  3927. }
  3928. next_desc:
  3929. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3930. /*
  3931. * Processed packet count is more than given quota
  3932. * stop to processing
  3933. */
  3934. count++;
  3935. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3936. break;
  3937. }
  3938. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3939. /* Process the reaped descriptors */
  3940. if (head_desc)
  3941. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3942. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3943. if (num_processed >= quota)
  3944. force_break = true;
  3945. if (!force_break &&
  3946. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3947. hal_ring_hdl)) {
  3948. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3949. if (!hif_exec_should_yield(soc->hif_handle,
  3950. int_ctx->dp_intr_id))
  3951. goto more_data;
  3952. }
  3953. }
  3954. DP_TX_HIST_STATS_PER_PDEV();
  3955. return num_processed;
  3956. }
  3957. #ifdef FEATURE_WLAN_TDLS
  3958. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3959. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3960. {
  3961. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3962. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3963. DP_MOD_ID_TDLS);
  3964. if (!vdev) {
  3965. dp_err("vdev handle for id %d is NULL", vdev_id);
  3966. return NULL;
  3967. }
  3968. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3969. vdev->is_tdls_frame = true;
  3970. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  3971. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3972. }
  3973. #endif
  3974. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3975. {
  3976. struct wlan_cfg_dp_soc_ctxt *cfg;
  3977. struct dp_soc *soc;
  3978. soc = vdev->pdev->soc;
  3979. if (!soc)
  3980. return;
  3981. cfg = soc->wlan_cfg_ctx;
  3982. if (!cfg)
  3983. return;
  3984. if (vdev->opmode == wlan_op_mode_ndi)
  3985. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3986. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3987. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3988. (vdev->subtype == wlan_op_subtype_p2p_go))
  3989. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3990. else
  3991. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3992. }
  3993. /**
  3994. * dp_tx_vdev_attach() - attach vdev to dp tx
  3995. * @vdev: virtual device instance
  3996. *
  3997. * Return: QDF_STATUS_SUCCESS: success
  3998. * QDF_STATUS_E_RESOURCES: Error return
  3999. */
  4000. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4001. {
  4002. int pdev_id;
  4003. /*
  4004. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4005. */
  4006. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4007. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4008. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4009. vdev->vdev_id);
  4010. pdev_id =
  4011. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4012. vdev->pdev->pdev_id);
  4013. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4014. /*
  4015. * Set HTT Extension Valid bit to 0 by default
  4016. */
  4017. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4018. dp_tx_vdev_update_search_flags(vdev);
  4019. dp_tx_vdev_update_feature_flags(vdev);
  4020. return QDF_STATUS_SUCCESS;
  4021. }
  4022. #ifndef FEATURE_WDS
  4023. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4024. {
  4025. return false;
  4026. }
  4027. #endif
  4028. /**
  4029. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4030. * @vdev: virtual device instance
  4031. *
  4032. * Return: void
  4033. *
  4034. */
  4035. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4036. {
  4037. struct dp_soc *soc = vdev->pdev->soc;
  4038. /*
  4039. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4040. * for TDLS link
  4041. *
  4042. * Enable AddrY (SA based search) only for non-WDS STA and
  4043. * ProxySTA VAP (in HKv1) modes.
  4044. *
  4045. * In all other VAP modes, only DA based search should be
  4046. * enabled
  4047. */
  4048. if (vdev->opmode == wlan_op_mode_sta &&
  4049. vdev->tdls_link_connected)
  4050. vdev->hal_desc_addr_search_flags =
  4051. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4052. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4053. !dp_tx_da_search_override(vdev))
  4054. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4055. else
  4056. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4057. /* Set search type only when peer map v2 messaging is enabled
  4058. * as we will have the search index (AST hash) only when v2 is
  4059. * enabled
  4060. */
  4061. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4062. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4063. else
  4064. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4065. }
  4066. static inline bool
  4067. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4068. struct dp_vdev *vdev,
  4069. struct dp_tx_desc_s *tx_desc)
  4070. {
  4071. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4072. return false;
  4073. /*
  4074. * if vdev is given, then only check whether desc
  4075. * vdev match. if vdev is NULL, then check whether
  4076. * desc pdev match.
  4077. */
  4078. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4079. (tx_desc->pdev == pdev);
  4080. }
  4081. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4082. /**
  4083. * dp_tx_desc_flush() - release resources associated
  4084. * to TX Desc
  4085. *
  4086. * @dp_pdev: Handle to DP pdev structure
  4087. * @vdev: virtual device instance
  4088. * NULL: no specific Vdev is required and check all allcated TX desc
  4089. * on this pdev.
  4090. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4091. *
  4092. * @force_free:
  4093. * true: flush the TX desc.
  4094. * false: only reset the Vdev in each allocated TX desc
  4095. * that associated to current Vdev.
  4096. *
  4097. * This function will go through the TX desc pool to flush
  4098. * the outstanding TX data or reset Vdev to NULL in associated TX
  4099. * Desc.
  4100. */
  4101. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4102. bool force_free)
  4103. {
  4104. uint8_t i;
  4105. uint32_t j;
  4106. uint32_t num_desc, page_id, offset;
  4107. uint16_t num_desc_per_page;
  4108. struct dp_soc *soc = pdev->soc;
  4109. struct dp_tx_desc_s *tx_desc = NULL;
  4110. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4111. if (!vdev && !force_free) {
  4112. dp_err("Reset TX desc vdev, Vdev param is required!");
  4113. return;
  4114. }
  4115. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4116. tx_desc_pool = &soc->tx_desc[i];
  4117. if (!(tx_desc_pool->pool_size) ||
  4118. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4119. !(tx_desc_pool->desc_pages.cacheable_pages))
  4120. continue;
  4121. /*
  4122. * Add flow pool lock protection in case pool is freed
  4123. * due to all tx_desc is recycled when handle TX completion.
  4124. * this is not necessary when do force flush as:
  4125. * a. double lock will happen if dp_tx_desc_release is
  4126. * also trying to acquire it.
  4127. * b. dp interrupt has been disabled before do force TX desc
  4128. * flush in dp_pdev_deinit().
  4129. */
  4130. if (!force_free)
  4131. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4132. num_desc = tx_desc_pool->pool_size;
  4133. num_desc_per_page =
  4134. tx_desc_pool->desc_pages.num_element_per_page;
  4135. for (j = 0; j < num_desc; j++) {
  4136. page_id = j / num_desc_per_page;
  4137. offset = j % num_desc_per_page;
  4138. if (qdf_unlikely(!(tx_desc_pool->
  4139. desc_pages.cacheable_pages)))
  4140. break;
  4141. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4142. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4143. /*
  4144. * Free TX desc if force free is
  4145. * required, otherwise only reset vdev
  4146. * in this TX desc.
  4147. */
  4148. if (force_free) {
  4149. dp_tx_comp_free_buf(soc, tx_desc);
  4150. dp_tx_desc_release(tx_desc, i);
  4151. } else {
  4152. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4153. }
  4154. }
  4155. }
  4156. if (!force_free)
  4157. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4158. }
  4159. }
  4160. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4161. /**
  4162. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4163. *
  4164. * @soc: Handle to DP soc structure
  4165. * @tx_desc: pointer of one TX desc
  4166. * @desc_pool_id: TX Desc pool id
  4167. */
  4168. static inline void
  4169. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4170. uint8_t desc_pool_id)
  4171. {
  4172. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4173. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4174. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4175. }
  4176. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4177. bool force_free)
  4178. {
  4179. uint8_t i, num_pool;
  4180. uint32_t j;
  4181. uint32_t num_desc, page_id, offset;
  4182. uint16_t num_desc_per_page;
  4183. struct dp_soc *soc = pdev->soc;
  4184. struct dp_tx_desc_s *tx_desc = NULL;
  4185. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4186. if (!vdev && !force_free) {
  4187. dp_err("Reset TX desc vdev, Vdev param is required!");
  4188. return;
  4189. }
  4190. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4191. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4192. for (i = 0; i < num_pool; i++) {
  4193. tx_desc_pool = &soc->tx_desc[i];
  4194. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4195. continue;
  4196. num_desc_per_page =
  4197. tx_desc_pool->desc_pages.num_element_per_page;
  4198. for (j = 0; j < num_desc; j++) {
  4199. page_id = j / num_desc_per_page;
  4200. offset = j % num_desc_per_page;
  4201. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4202. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4203. if (force_free) {
  4204. dp_tx_comp_free_buf(soc, tx_desc);
  4205. dp_tx_desc_release(tx_desc, i);
  4206. } else {
  4207. dp_tx_desc_reset_vdev(soc, tx_desc,
  4208. i);
  4209. }
  4210. }
  4211. }
  4212. }
  4213. }
  4214. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4215. /**
  4216. * dp_tx_vdev_detach() - detach vdev from dp tx
  4217. * @vdev: virtual device instance
  4218. *
  4219. * Return: QDF_STATUS_SUCCESS: success
  4220. * QDF_STATUS_E_RESOURCES: Error return
  4221. */
  4222. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4223. {
  4224. struct dp_pdev *pdev = vdev->pdev;
  4225. /* Reset TX desc associated to this Vdev as NULL */
  4226. dp_tx_desc_flush(pdev, vdev, false);
  4227. dp_tx_vdev_multipass_deinit(vdev);
  4228. return QDF_STATUS_SUCCESS;
  4229. }
  4230. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4231. /* Pools will be allocated dynamically */
  4232. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4233. int num_desc)
  4234. {
  4235. uint8_t i;
  4236. for (i = 0; i < num_pool; i++) {
  4237. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4238. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4239. }
  4240. return QDF_STATUS_SUCCESS;
  4241. }
  4242. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4243. int num_desc)
  4244. {
  4245. return QDF_STATUS_SUCCESS;
  4246. }
  4247. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4248. {
  4249. }
  4250. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4251. {
  4252. uint8_t i;
  4253. for (i = 0; i < num_pool; i++)
  4254. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4255. }
  4256. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4257. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4258. int num_desc)
  4259. {
  4260. uint8_t i, count;
  4261. /* Allocate software Tx descriptor pools */
  4262. for (i = 0; i < num_pool; i++) {
  4263. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4264. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4265. FL("Tx Desc Pool alloc %d failed %pK"),
  4266. i, soc);
  4267. goto fail;
  4268. }
  4269. }
  4270. return QDF_STATUS_SUCCESS;
  4271. fail:
  4272. for (count = 0; count < i; count++)
  4273. dp_tx_desc_pool_free(soc, count);
  4274. return QDF_STATUS_E_NOMEM;
  4275. }
  4276. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4277. int num_desc)
  4278. {
  4279. uint8_t i;
  4280. for (i = 0; i < num_pool; i++) {
  4281. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4282. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4283. FL("Tx Desc Pool init %d failed %pK"),
  4284. i, soc);
  4285. return QDF_STATUS_E_NOMEM;
  4286. }
  4287. }
  4288. return QDF_STATUS_SUCCESS;
  4289. }
  4290. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4291. {
  4292. uint8_t i;
  4293. for (i = 0; i < num_pool; i++)
  4294. dp_tx_desc_pool_deinit(soc, i);
  4295. }
  4296. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4297. {
  4298. uint8_t i;
  4299. for (i = 0; i < num_pool; i++)
  4300. dp_tx_desc_pool_free(soc, i);
  4301. }
  4302. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4303. /**
  4304. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4305. * @soc: core txrx main context
  4306. * @num_pool: number of pools
  4307. *
  4308. */
  4309. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4310. {
  4311. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4312. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4313. }
  4314. /**
  4315. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4316. * @soc: core txrx main context
  4317. * @num_pool: number of pools
  4318. *
  4319. */
  4320. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4321. {
  4322. dp_tx_tso_desc_pool_free(soc, num_pool);
  4323. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4324. }
  4325. /**
  4326. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4327. * @soc: core txrx main context
  4328. *
  4329. * This function frees all tx related descriptors as below
  4330. * 1. Regular TX descriptors (static pools)
  4331. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4332. * 3. TSO descriptors
  4333. *
  4334. */
  4335. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4336. {
  4337. uint8_t num_pool;
  4338. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4339. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4340. dp_tx_ext_desc_pool_free(soc, num_pool);
  4341. dp_tx_delete_static_pools(soc, num_pool);
  4342. }
  4343. /**
  4344. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4345. * @soc: core txrx main context
  4346. *
  4347. * This function de-initializes all tx related descriptors as below
  4348. * 1. Regular TX descriptors (static pools)
  4349. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4350. * 3. TSO descriptors
  4351. *
  4352. */
  4353. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4354. {
  4355. uint8_t num_pool;
  4356. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4357. dp_tx_flow_control_deinit(soc);
  4358. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4359. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4360. dp_tx_deinit_static_pools(soc, num_pool);
  4361. }
  4362. /**
  4363. * dp_tso_attach() - TSO attach handler
  4364. * @txrx_soc: Opaque Dp handle
  4365. *
  4366. * Reserve TSO descriptor buffers
  4367. *
  4368. * Return: QDF_STATUS_E_FAILURE on failure or
  4369. * QDF_STATUS_SUCCESS on success
  4370. */
  4371. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4372. uint8_t num_pool,
  4373. uint16_t num_desc)
  4374. {
  4375. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4376. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4377. return QDF_STATUS_E_FAILURE;
  4378. }
  4379. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4380. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4381. num_pool, soc);
  4382. return QDF_STATUS_E_FAILURE;
  4383. }
  4384. return QDF_STATUS_SUCCESS;
  4385. }
  4386. /**
  4387. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4388. * @soc: DP soc handle
  4389. * @num_pool: Number of pools
  4390. * @num_desc: Number of descriptors
  4391. *
  4392. * Initialize TSO descriptor pools
  4393. *
  4394. * Return: QDF_STATUS_E_FAILURE on failure or
  4395. * QDF_STATUS_SUCCESS on success
  4396. */
  4397. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4398. uint8_t num_pool,
  4399. uint16_t num_desc)
  4400. {
  4401. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4402. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4403. return QDF_STATUS_E_FAILURE;
  4404. }
  4405. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4406. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4407. num_pool, soc);
  4408. return QDF_STATUS_E_FAILURE;
  4409. }
  4410. return QDF_STATUS_SUCCESS;
  4411. }
  4412. /**
  4413. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4414. * @soc: core txrx main context
  4415. *
  4416. * This function allocates memory for following descriptor pools
  4417. * 1. regular sw tx descriptor pools (static pools)
  4418. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4419. * 3. TSO descriptor pools
  4420. *
  4421. * Return: QDF_STATUS_SUCCESS: success
  4422. * QDF_STATUS_E_RESOURCES: Error return
  4423. */
  4424. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4425. {
  4426. uint8_t num_pool;
  4427. uint32_t num_desc;
  4428. uint32_t num_ext_desc;
  4429. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4430. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4431. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4432. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4433. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4434. __func__, num_pool, num_desc);
  4435. if ((num_pool > MAX_TXDESC_POOLS) ||
  4436. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4437. goto fail1;
  4438. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4439. goto fail1;
  4440. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4441. goto fail2;
  4442. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4443. return QDF_STATUS_SUCCESS;
  4444. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4445. goto fail3;
  4446. return QDF_STATUS_SUCCESS;
  4447. fail3:
  4448. dp_tx_ext_desc_pool_free(soc, num_pool);
  4449. fail2:
  4450. dp_tx_delete_static_pools(soc, num_pool);
  4451. fail1:
  4452. return QDF_STATUS_E_RESOURCES;
  4453. }
  4454. /**
  4455. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4456. * @soc: core txrx main context
  4457. *
  4458. * This function initializes the following TX descriptor pools
  4459. * 1. regular sw tx descriptor pools (static pools)
  4460. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4461. * 3. TSO descriptor pools
  4462. *
  4463. * Return: QDF_STATUS_SUCCESS: success
  4464. * QDF_STATUS_E_RESOURCES: Error return
  4465. */
  4466. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4467. {
  4468. uint8_t num_pool;
  4469. uint32_t num_desc;
  4470. uint32_t num_ext_desc;
  4471. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4472. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4473. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4474. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4475. goto fail1;
  4476. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4477. goto fail2;
  4478. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4479. return QDF_STATUS_SUCCESS;
  4480. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4481. goto fail3;
  4482. dp_tx_flow_control_init(soc);
  4483. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4484. return QDF_STATUS_SUCCESS;
  4485. fail3:
  4486. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4487. fail2:
  4488. dp_tx_deinit_static_pools(soc, num_pool);
  4489. fail1:
  4490. return QDF_STATUS_E_RESOURCES;
  4491. }
  4492. /**
  4493. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4494. * @txrx_soc: dp soc handle
  4495. *
  4496. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4497. * QDF_STATUS_E_FAILURE
  4498. */
  4499. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4500. {
  4501. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4502. uint8_t num_pool;
  4503. uint32_t num_desc;
  4504. uint32_t num_ext_desc;
  4505. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4506. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4507. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4508. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4509. return QDF_STATUS_E_FAILURE;
  4510. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4511. return QDF_STATUS_E_FAILURE;
  4512. return QDF_STATUS_SUCCESS;
  4513. }
  4514. /**
  4515. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4516. * @txrx_soc: dp soc handle
  4517. *
  4518. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4519. */
  4520. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4521. {
  4522. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4523. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4524. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4525. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4526. return QDF_STATUS_SUCCESS;
  4527. }