sde_kms.c 117 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. if (sde_kms->catalog->qdss_count)
  133. debugfs_create_u32("qdss", 0600, debugfs_root,
  134. (u32 *)&sde_kms->qdss_enabled);
  135. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  136. (u32 *)&sde_kms->pm_suspend_clk_dump);
  137. return 0;
  138. }
  139. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  140. {
  141. struct sde_kms *sde_kms = to_sde_kms(kms);
  142. /* don't need to NULL check debugfs_root */
  143. if (sde_kms) {
  144. sde_debugfs_vbif_destroy(sde_kms);
  145. sde_debugfs_core_irq_destroy(sde_kms);
  146. }
  147. }
  148. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  149. {
  150. int i;
  151. struct device *dev = sde_kms->dev->dev;
  152. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  153. for (i = 0; i < sde_kms->dsi_display_count; i++)
  154. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  155. return 0;
  156. }
  157. #else
  158. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  159. {
  160. return 0;
  161. }
  162. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  163. {
  164. }
  165. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. #endif
  170. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  171. {
  172. int ret;
  173. if (!kms || !crtc)
  174. return -EINVAL;
  175. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  176. ret = sde_crtc_vblank(crtc, true);
  177. SDE_ATRACE_END("sde_kms_enable_vblank");
  178. return ret;
  179. }
  180. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  181. {
  182. if (!kms || !crtc)
  183. return;
  184. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  185. sde_crtc_vblank(crtc, false);
  186. SDE_ATRACE_END("sde_kms_disable_vblank");
  187. }
  188. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  189. struct drm_crtc *crtc)
  190. {
  191. struct drm_encoder *encoder;
  192. struct drm_device *dev;
  193. int ret;
  194. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  195. SDE_ERROR("invalid params\n");
  196. return;
  197. }
  198. if (!crtc->state->enable) {
  199. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  200. return;
  201. }
  202. if (!crtc->state->active) {
  203. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  204. return;
  205. }
  206. dev = crtc->dev;
  207. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  208. if (encoder->crtc != crtc)
  209. continue;
  210. /*
  211. * Video Mode - Wait for VSYNC
  212. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  213. * complete
  214. */
  215. SDE_EVT32_VERBOSE(DRMID(crtc));
  216. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  217. if (ret && ret != -EWOULDBLOCK) {
  218. SDE_ERROR(
  219. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  220. crtc->base.id, encoder->base.id, ret);
  221. break;
  222. }
  223. }
  224. }
  225. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  226. struct drm_crtc *crtc, bool enable)
  227. {
  228. struct drm_device *dev;
  229. struct msm_drm_private *priv;
  230. struct sde_mdss_cfg *sde_cfg;
  231. struct drm_plane *plane;
  232. int i, ret;
  233. dev = sde_kms->dev;
  234. priv = dev->dev_private;
  235. sde_cfg = sde_kms->catalog;
  236. ret = sde_vbif_halt_xin_mask(sde_kms,
  237. sde_cfg->sui_block_xin_mask, enable);
  238. if (ret) {
  239. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  240. return ret;
  241. }
  242. if (enable) {
  243. for (i = 0; i < priv->num_planes; i++) {
  244. plane = priv->planes[i];
  245. sde_plane_secure_ctrl_xin_client(plane, crtc);
  246. }
  247. }
  248. return 0;
  249. }
  250. /**
  251. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  252. * @sde_kms: Pointer to sde_kms struct
  253. * @vimd: switch the stage 2 translation to this VMID
  254. */
  255. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  256. {
  257. struct device dummy = {};
  258. dma_addr_t dma_handle;
  259. uint32_t num_sids;
  260. uint32_t *sec_sid;
  261. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  262. int ret = 0, i;
  263. struct qtee_shm shm;
  264. bool qtee_en = qtee_shmbridge_is_enabled();
  265. phys_addr_t mem_addr;
  266. u64 mem_size;
  267. num_sids = sde_cfg->sec_sid_mask_count;
  268. if (!num_sids) {
  269. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  270. return -EINVAL;
  271. }
  272. if (qtee_en) {
  273. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  274. &shm);
  275. if (ret)
  276. return -ENOMEM;
  277. sec_sid = (uint32_t *) shm.vaddr;
  278. mem_addr = shm.paddr;
  279. /**
  280. * SMMUSecureModeSwitch requires the size to be number of SID's
  281. * but shm allocates size in pages. Modify the args as per
  282. * client requirement.
  283. */
  284. mem_size = sizeof(uint32_t) * num_sids;
  285. } else {
  286. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  287. if (!sec_sid)
  288. return -ENOMEM;
  289. mem_addr = virt_to_phys(sec_sid);
  290. mem_size = sizeof(uint32_t) * num_sids;
  291. }
  292. for (i = 0; i < num_sids; i++) {
  293. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  294. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  295. }
  296. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  297. if (ret) {
  298. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  299. goto map_error;
  300. }
  301. set_dma_ops(&dummy, NULL);
  302. dma_handle = dma_map_single(&dummy, sec_sid,
  303. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  304. if (dma_mapping_error(&dummy, dma_handle)) {
  305. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  306. vmid);
  307. goto map_error;
  308. }
  309. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  310. vmid, num_sids, qtee_en);
  311. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  312. mem_size, vmid);
  313. if (ret)
  314. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  315. vmid, ret);
  316. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  317. vmid, qtee_en, num_sids, ret);
  318. dma_unmap_single(&dummy, dma_handle,
  319. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  320. map_error:
  321. if (qtee_en)
  322. qtee_shmbridge_free_shm(&shm);
  323. else
  324. kfree(sec_sid);
  325. return ret;
  326. }
  327. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  328. {
  329. u32 ret;
  330. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  331. return 0;
  332. /* detach_all_contexts */
  333. ret = sde_kms_mmu_detach(sde_kms, false);
  334. if (ret) {
  335. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  336. goto mmu_error;
  337. }
  338. ret = _sde_kms_scm_call(sde_kms, vmid);
  339. if (ret) {
  340. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  341. goto scm_error;
  342. }
  343. return 0;
  344. scm_error:
  345. sde_kms_mmu_attach(sde_kms, false);
  346. mmu_error:
  347. atomic_dec(&sde_kms->detach_all_cb);
  348. return ret;
  349. }
  350. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  351. u32 old_vmid)
  352. {
  353. u32 ret;
  354. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  355. return 0;
  356. ret = _sde_kms_scm_call(sde_kms, vmid);
  357. if (ret) {
  358. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  359. goto scm_error;
  360. }
  361. /* attach_all_contexts */
  362. ret = sde_kms_mmu_attach(sde_kms, false);
  363. if (ret) {
  364. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  365. goto mmu_error;
  366. }
  367. return 0;
  368. mmu_error:
  369. _sde_kms_scm_call(sde_kms, old_vmid);
  370. scm_error:
  371. atomic_inc(&sde_kms->detach_all_cb);
  372. return ret;
  373. }
  374. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  375. {
  376. u32 ret;
  377. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  378. return 0;
  379. /* detach secure_context */
  380. ret = sde_kms_mmu_detach(sde_kms, true);
  381. if (ret) {
  382. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  383. goto mmu_error;
  384. }
  385. ret = _sde_kms_scm_call(sde_kms, vmid);
  386. if (ret) {
  387. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  388. goto scm_error;
  389. }
  390. return 0;
  391. scm_error:
  392. sde_kms_mmu_attach(sde_kms, true);
  393. mmu_error:
  394. atomic_dec(&sde_kms->detach_sec_cb);
  395. return ret;
  396. }
  397. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  398. u32 old_vmid)
  399. {
  400. u32 ret;
  401. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  402. return 0;
  403. ret = _sde_kms_scm_call(sde_kms, vmid);
  404. if (ret) {
  405. goto scm_error;
  406. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  407. }
  408. ret = sde_kms_mmu_attach(sde_kms, true);
  409. if (ret) {
  410. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  411. goto mmu_error;
  412. }
  413. return 0;
  414. mmu_error:
  415. _sde_kms_scm_call(sde_kms, old_vmid);
  416. scm_error:
  417. atomic_inc(&sde_kms->detach_sec_cb);
  418. return ret;
  419. }
  420. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  421. struct drm_crtc *crtc, bool enable)
  422. {
  423. int ret;
  424. if (enable) {
  425. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  426. if (ret < 0) {
  427. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  428. return ret;
  429. }
  430. sde_crtc_misr_setup(crtc, true, 1);
  431. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  432. if (ret) {
  433. sde_crtc_misr_setup(crtc, false, 0);
  434. pm_runtime_put_sync(sde_kms->dev->dev);
  435. return ret;
  436. }
  437. } else {
  438. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  439. sde_crtc_misr_setup(crtc, false, 0);
  440. pm_runtime_put_sync(sde_kms->dev->dev);
  441. }
  442. return 0;
  443. }
  444. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  445. bool post_commit)
  446. {
  447. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  448. int old_smmu_state = smmu_state->state;
  449. int ret = 0;
  450. u32 vmid;
  451. if (!sde_kms || !crtc) {
  452. SDE_ERROR("invalid argument(s)\n");
  453. return -EINVAL;
  454. }
  455. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  456. post_commit, smmu_state->sui_misr_state,
  457. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  458. if ((!smmu_state->transition_type) ||
  459. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  460. /* Bail out */
  461. return 0;
  462. /* enable sui misr if requested, before the transition */
  463. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  464. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  465. if (ret) {
  466. smmu_state->sui_misr_state = NONE;
  467. goto end;
  468. }
  469. }
  470. mutex_lock(&sde_kms->secure_transition_lock);
  471. switch (smmu_state->state) {
  472. case DETACH_ALL_REQ:
  473. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  474. if (!ret)
  475. smmu_state->state = DETACHED;
  476. break;
  477. case ATTACH_ALL_REQ:
  478. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  479. VMID_CP_SEC_DISPLAY);
  480. if (!ret) {
  481. smmu_state->state = ATTACHED;
  482. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  483. }
  484. break;
  485. case DETACH_SEC_REQ:
  486. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  487. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  488. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  489. if (!ret)
  490. smmu_state->state = DETACHED_SEC;
  491. break;
  492. case ATTACH_SEC_REQ:
  493. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  494. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  495. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  496. if (!ret) {
  497. smmu_state->state = ATTACHED;
  498. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  499. }
  500. break;
  501. default:
  502. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  503. DRMID(crtc), smmu_state->state,
  504. smmu_state->transition_type);
  505. ret = -EINVAL;
  506. break;
  507. }
  508. mutex_unlock(&sde_kms->secure_transition_lock);
  509. /* disable sui misr if requested, after the transition */
  510. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  511. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  512. if (ret)
  513. goto end;
  514. }
  515. end:
  516. smmu_state->transition_error = false;
  517. if (ret) {
  518. smmu_state->transition_error = true;
  519. SDE_ERROR(
  520. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  521. DRMID(crtc), old_smmu_state, smmu_state->state,
  522. smmu_state->secure_level, ret);
  523. smmu_state->state = smmu_state->prev_state;
  524. smmu_state->secure_level = smmu_state->prev_secure_level;
  525. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  526. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  527. }
  528. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  529. DRMID(crtc), old_smmu_state, smmu_state->state,
  530. smmu_state->secure_level, ret);
  531. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  532. smmu_state->transition_type,
  533. smmu_state->transition_error,
  534. smmu_state->secure_level, smmu_state->prev_secure_level,
  535. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  536. smmu_state->sui_misr_state = NONE;
  537. smmu_state->transition_type = NONE;
  538. return ret;
  539. }
  540. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  541. struct drm_atomic_state *state)
  542. {
  543. struct drm_crtc *crtc;
  544. struct drm_crtc_state *old_crtc_state;
  545. struct drm_plane_state *old_plane_state, *new_plane_state;
  546. struct drm_plane *plane;
  547. struct drm_plane_state *plane_state;
  548. struct sde_kms *sde_kms = to_sde_kms(kms);
  549. struct drm_device *dev = sde_kms->dev;
  550. int i, ops = 0, ret = 0;
  551. bool old_valid_fb = false;
  552. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  553. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  554. if (!crtc->state || !crtc->state->active)
  555. continue;
  556. /*
  557. * It is safe to assume only one active crtc,
  558. * and compatible translation modes on the
  559. * planes staged on this crtc.
  560. * otherwise validation would have failed.
  561. * For this CRTC,
  562. */
  563. /*
  564. * 1. Check if old state on the CRTC has planes
  565. * staged with valid fbs
  566. */
  567. for_each_old_plane_in_state(state, plane, plane_state, i) {
  568. if (!plane_state->crtc)
  569. continue;
  570. if (plane_state->fb) {
  571. old_valid_fb = true;
  572. break;
  573. }
  574. }
  575. /*
  576. * 2.Get the operations needed to be performed before
  577. * secure transition can be initiated.
  578. */
  579. ops = sde_crtc_get_secure_transition_ops(crtc,
  580. old_crtc_state, old_valid_fb);
  581. if (ops < 0) {
  582. SDE_ERROR("invalid secure operations %x\n", ops);
  583. return ops;
  584. }
  585. if (!ops) {
  586. smmu_state->transition_error = false;
  587. goto no_ops;
  588. }
  589. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  590. crtc->base.id, ops, crtc->state);
  591. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  592. /* 3. Perform operations needed for secure transition */
  593. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  594. SDE_DEBUG("wait_for_transfer_done\n");
  595. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  596. }
  597. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  598. SDE_DEBUG("cleanup planes\n");
  599. drm_atomic_helper_cleanup_planes(dev, state);
  600. for_each_oldnew_plane_in_state(state, plane,
  601. old_plane_state, new_plane_state, i)
  602. sde_plane_destroy_fb(old_plane_state);
  603. }
  604. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  605. SDE_DEBUG("secure ctrl\n");
  606. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  607. }
  608. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  609. SDE_DEBUG("prepare planes %d",
  610. crtc->state->plane_mask);
  611. drm_atomic_crtc_for_each_plane(plane,
  612. crtc) {
  613. const struct drm_plane_helper_funcs *funcs;
  614. plane_state = plane->state;
  615. funcs = plane->helper_private;
  616. SDE_DEBUG("psde:%d FB[%u]\n",
  617. plane->base.id,
  618. plane->fb->base.id);
  619. if (!funcs)
  620. continue;
  621. if (funcs->prepare_fb(plane, plane_state)) {
  622. ret = funcs->prepare_fb(plane,
  623. plane_state);
  624. if (ret)
  625. return ret;
  626. }
  627. }
  628. }
  629. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  630. SDE_DEBUG("secure operations completed\n");
  631. }
  632. no_ops:
  633. return 0;
  634. }
  635. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  636. unsigned int splash_buffer_size,
  637. unsigned int ramdump_base,
  638. unsigned int ramdump_buffer_size)
  639. {
  640. unsigned long pfn_start, pfn_end, pfn_idx;
  641. int ret = 0;
  642. if (!mem_addr || !splash_buffer_size) {
  643. SDE_ERROR("invalid params\n");
  644. return -EINVAL;
  645. }
  646. /* leave ramdump memory only if base address matches */
  647. if (ramdump_base == mem_addr &&
  648. ramdump_buffer_size <= splash_buffer_size) {
  649. mem_addr += ramdump_buffer_size;
  650. splash_buffer_size -= ramdump_buffer_size;
  651. }
  652. pfn_start = mem_addr >> PAGE_SHIFT;
  653. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  654. ret = memblock_free(mem_addr, splash_buffer_size);
  655. if (ret) {
  656. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  657. return ret;
  658. }
  659. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  660. free_reserved_page(pfn_to_page(pfn_idx));
  661. return ret;
  662. }
  663. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  664. struct sde_splash_mem *splash)
  665. {
  666. struct msm_mmu *mmu = NULL;
  667. int ret = 0;
  668. if (!sde_kms->aspace[0]) {
  669. SDE_ERROR("aspace not found for sde kms node\n");
  670. return -EINVAL;
  671. }
  672. mmu = sde_kms->aspace[0]->mmu;
  673. if (!mmu) {
  674. SDE_ERROR("mmu not found for aspace\n");
  675. return -EINVAL;
  676. }
  677. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  678. SDE_ERROR("invalid input params for map\n");
  679. return -EINVAL;
  680. }
  681. if (!splash->ref_cnt) {
  682. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  683. splash->splash_buf_base,
  684. splash->splash_buf_size,
  685. IOMMU_READ | IOMMU_NOEXEC);
  686. if (ret)
  687. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  688. }
  689. splash->ref_cnt++;
  690. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  691. splash->splash_buf_base,
  692. splash->splash_buf_size,
  693. splash->ref_cnt);
  694. return ret;
  695. }
  696. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  697. {
  698. int i = 0;
  699. int ret = 0;
  700. if (!sde_kms)
  701. return -EINVAL;
  702. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  703. ret = _sde_kms_splash_mem_get(sde_kms,
  704. sde_kms->splash_data.splash_display[i].splash);
  705. if (ret)
  706. return ret;
  707. }
  708. return ret;
  709. }
  710. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  711. struct sde_splash_mem *splash)
  712. {
  713. struct msm_mmu *mmu = NULL;
  714. int rc = 0;
  715. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  716. SDE_ERROR("invalid params\n");
  717. return -EINVAL;
  718. }
  719. mmu = sde_kms->aspace[0]->mmu;
  720. if (!splash || !splash->ref_cnt ||
  721. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  722. return -EINVAL;
  723. splash->ref_cnt--;
  724. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  725. splash->splash_buf_base, splash->ref_cnt);
  726. if (!splash->ref_cnt) {
  727. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  728. splash->splash_buf_size);
  729. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  730. splash->splash_buf_size, splash->ramdump_base,
  731. splash->ramdump_size);
  732. splash->splash_buf_base = 0;
  733. splash->splash_buf_size = 0;
  734. }
  735. return rc;
  736. }
  737. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  738. {
  739. int i = 0;
  740. int ret = 0;
  741. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  742. return -EINVAL;
  743. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  744. ret = _sde_kms_splash_mem_put(sde_kms,
  745. sde_kms->splash_data.splash_display[i].splash);
  746. if (ret)
  747. return ret;
  748. }
  749. return ret;
  750. }
  751. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  752. struct drm_connector_state *conn_state)
  753. {
  754. int lp_mode, blank;
  755. if (crtc_state->active)
  756. lp_mode = sde_connector_get_property(conn_state,
  757. CONNECTOR_PROP_LP);
  758. else
  759. lp_mode = SDE_MODE_DPMS_OFF;
  760. switch (lp_mode) {
  761. case SDE_MODE_DPMS_ON:
  762. blank = DRM_PANEL_BLANK_UNBLANK;
  763. break;
  764. case SDE_MODE_DPMS_LP1:
  765. case SDE_MODE_DPMS_LP2:
  766. blank = DRM_PANEL_BLANK_LP;
  767. break;
  768. case SDE_MODE_DPMS_OFF:
  769. default:
  770. blank = DRM_PANEL_BLANK_POWERDOWN;
  771. break;
  772. }
  773. return blank;
  774. }
  775. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  776. unsigned long event)
  777. {
  778. struct drm_connector *connector;
  779. struct drm_connector_state *old_conn_state;
  780. struct drm_crtc_state *old_crtc_state;
  781. struct drm_crtc *crtc;
  782. int i, old_mode, new_mode, old_fps, new_fps;
  783. for_each_old_connector_in_state(old_state, connector,
  784. old_conn_state, i) {
  785. crtc = connector->state->crtc ? connector->state->crtc :
  786. old_conn_state->crtc;
  787. if (!crtc)
  788. continue;
  789. new_fps = crtc->state->mode.vrefresh;
  790. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  791. if (old_conn_state->crtc) {
  792. old_crtc_state = drm_atomic_get_existing_crtc_state(
  793. old_state, old_conn_state->crtc);
  794. old_fps = old_crtc_state->mode.vrefresh;
  795. old_mode = _sde_kms_get_blank(old_crtc_state,
  796. old_conn_state);
  797. } else {
  798. old_fps = 0;
  799. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  800. }
  801. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  802. struct drm_panel_notifier notifier_data;
  803. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  804. connector->panel, crtc->state->active,
  805. old_conn_state->crtc, event);
  806. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  807. old_mode, new_mode, old_fps, new_fps);
  808. /* If suspend resume and fps change are happening
  809. * at the same time, give preference to power mode
  810. * changes rather than fps change.
  811. */
  812. if ((old_mode == new_mode) && (old_fps != new_fps))
  813. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  814. notifier_data.data = &new_mode;
  815. notifier_data.refresh_rate = new_fps;
  816. notifier_data.id = connector->base.id;
  817. if (connector->panel)
  818. drm_panel_notifier_call_chain(connector->panel,
  819. event, &notifier_data);
  820. }
  821. }
  822. }
  823. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  824. struct drm_atomic_state *state)
  825. {
  826. int i;
  827. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  828. struct drm_crtc *crtc, *vm_crtc = NULL;
  829. struct drm_crtc_state *new_cstate, *old_cstate;
  830. struct sde_crtc_state *vm_cstate;
  831. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  832. if (!new_cstate->active && !old_cstate->active)
  833. continue;
  834. vm_cstate = to_sde_crtc_state(new_cstate);
  835. vm_req = sde_crtc_get_property(vm_cstate,
  836. CRTC_PROP_VM_REQ_STATE);
  837. if (vm_req != VM_REQ_NONE) {
  838. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  839. vm_req, crtc->base.id);
  840. vm_crtc = crtc;
  841. break;
  842. }
  843. }
  844. return vm_crtc;
  845. }
  846. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  847. struct drm_atomic_state *state)
  848. {
  849. struct drm_device *ddev;
  850. struct drm_crtc *crtc;
  851. struct drm_crtc_state *new_cstate;
  852. struct drm_encoder *encoder;
  853. struct drm_connector *connector;
  854. struct sde_vm_ops *vm_ops;
  855. struct sde_crtc_state *cstate;
  856. enum sde_crtc_vm_req vm_req;
  857. int rc = 0;
  858. ddev = sde_kms->dev;
  859. vm_ops = sde_vm_get_ops(sde_kms);
  860. if (!vm_ops)
  861. return -EINVAL;
  862. crtc = sde_kms_vm_get_vm_crtc(state);
  863. if (!crtc)
  864. return 0;
  865. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  866. cstate = to_sde_crtc_state(new_cstate);
  867. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  868. if (vm_req != VM_REQ_ACQUIRE)
  869. return 0;
  870. /* enable MDSS irq line */
  871. sde_irq_update(&sde_kms->base, true);
  872. /* clear the stale IRQ status bits */
  873. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  874. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  875. /* enable the display path IRQ's */
  876. drm_for_each_encoder_mask(encoder, crtc->dev,
  877. crtc->state->encoder_mask) {
  878. if (sde_encoder_in_clone_mode(encoder))
  879. continue;
  880. sde_encoder_irq_control(encoder, true);
  881. }
  882. /* Schedule ESD work */
  883. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  884. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  885. sde_connector_schedule_status_work(connector, true);
  886. /* enable vblank events */
  887. drm_crtc_vblank_on(crtc);
  888. /* handle non-SDE pre_acquire */
  889. if (vm_ops->vm_client_post_acquire)
  890. rc = vm_ops->vm_client_post_acquire(sde_kms);
  891. return rc;
  892. }
  893. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  894. struct drm_atomic_state *state)
  895. {
  896. struct drm_device *ddev;
  897. struct drm_plane *plane;
  898. struct drm_crtc *crtc;
  899. struct drm_crtc_state *new_cstate;
  900. struct sde_crtc_state *cstate;
  901. enum sde_crtc_vm_req vm_req;
  902. ddev = sde_kms->dev;
  903. crtc = sde_kms_vm_get_vm_crtc(state);
  904. if (!crtc)
  905. return 0;
  906. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  907. cstate = to_sde_crtc_state(new_cstate);
  908. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  909. if (vm_req != VM_REQ_ACQUIRE)
  910. return 0;
  911. /* Clear the stale IRQ status bits */
  912. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  913. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  914. /* Program the SID's for the trusted VM */
  915. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  916. sde_plane_set_sid(plane, 1);
  917. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  918. return 0;
  919. }
  920. static void sde_kms_prepare_commit(struct msm_kms *kms,
  921. struct drm_atomic_state *state)
  922. {
  923. struct sde_kms *sde_kms;
  924. struct msm_drm_private *priv;
  925. struct drm_device *dev;
  926. struct drm_encoder *encoder;
  927. struct drm_crtc *crtc;
  928. struct drm_crtc_state *crtc_state;
  929. struct sde_vm_ops *vm_ops;
  930. int i, rc;
  931. if (!kms)
  932. return;
  933. sde_kms = to_sde_kms(kms);
  934. dev = sde_kms->dev;
  935. if (!dev || !dev->dev_private)
  936. return;
  937. priv = dev->dev_private;
  938. SDE_ATRACE_BEGIN("prepare_commit");
  939. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  940. if (rc < 0) {
  941. SDE_ERROR("failed to enable power resources %d\n", rc);
  942. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  943. goto end;
  944. }
  945. if (sde_kms->first_kickoff) {
  946. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  947. sde_kms->first_kickoff = false;
  948. }
  949. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  950. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  951. head) {
  952. if (encoder->crtc != crtc)
  953. continue;
  954. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  955. SDE_ERROR("crtc:%d, initiating hw reset\n",
  956. DRMID(crtc));
  957. sde_encoder_needs_hw_reset(encoder);
  958. sde_crtc_set_needs_hw_reset(crtc);
  959. }
  960. }
  961. }
  962. /*
  963. * NOTE: for secure use cases we want to apply the new HW
  964. * configuration only after completing preparation for secure
  965. * transitions prepare below if any transtions is required.
  966. */
  967. sde_kms_prepare_secure_transition(kms, state);
  968. vm_ops = sde_vm_get_ops(sde_kms);
  969. if (!vm_ops)
  970. goto end_vm;
  971. if (vm_ops->vm_prepare_commit)
  972. vm_ops->vm_prepare_commit(sde_kms, state);
  973. end_vm:
  974. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  975. end:
  976. SDE_ATRACE_END("prepare_commit");
  977. }
  978. static void sde_kms_commit(struct msm_kms *kms,
  979. struct drm_atomic_state *old_state)
  980. {
  981. struct sde_kms *sde_kms;
  982. struct drm_crtc *crtc;
  983. struct drm_crtc_state *old_crtc_state;
  984. int i;
  985. if (!kms || !old_state)
  986. return;
  987. sde_kms = to_sde_kms(kms);
  988. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  989. SDE_ERROR("power resource is not enabled\n");
  990. return;
  991. }
  992. SDE_ATRACE_BEGIN("sde_kms_commit");
  993. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  994. if (crtc->state->active) {
  995. SDE_EVT32(DRMID(crtc), old_state);
  996. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  997. }
  998. }
  999. SDE_ATRACE_END("sde_kms_commit");
  1000. }
  1001. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  1002. struct sde_splash_display *splash_display)
  1003. {
  1004. if (!sde_kms || !splash_display ||
  1005. !sde_kms->splash_data.num_splash_displays)
  1006. return;
  1007. if (sde_kms->splash_data.num_splash_regions)
  1008. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  1009. sde_kms->splash_data.num_splash_displays--;
  1010. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  1011. sde_kms->splash_data.num_splash_displays);
  1012. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1013. }
  1014. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1015. struct drm_crtc *crtc)
  1016. {
  1017. struct msm_drm_private *priv;
  1018. struct sde_splash_display *splash_display;
  1019. int i;
  1020. if (!sde_kms || !crtc)
  1021. return;
  1022. priv = sde_kms->dev->dev_private;
  1023. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1024. return;
  1025. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1026. sde_kms->splash_data.num_splash_displays);
  1027. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1028. splash_display = &sde_kms->splash_data.splash_display[i];
  1029. if (splash_display->encoder &&
  1030. crtc == splash_display->encoder->crtc)
  1031. break;
  1032. }
  1033. if (i >= MAX_DSI_DISPLAYS)
  1034. return;
  1035. if (splash_display->cont_splash_enabled) {
  1036. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1037. splash_display, false);
  1038. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1039. }
  1040. /* remove the votes if all displays are done with splash */
  1041. if (!sde_kms->splash_data.num_splash_displays) {
  1042. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1043. sde_power_data_bus_set_quota(&priv->phandle, i,
  1044. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1045. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1046. pm_runtime_put_sync(sde_kms->dev->dev);
  1047. }
  1048. }
  1049. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1050. struct drm_atomic_state *state)
  1051. {
  1052. struct sde_vm_ops *vm_ops;
  1053. struct drm_device *ddev;
  1054. struct drm_crtc *crtc;
  1055. struct drm_plane *plane;
  1056. struct drm_encoder *encoder;
  1057. struct sde_crtc_state *cstate;
  1058. struct drm_crtc_state *new_cstate;
  1059. enum sde_crtc_vm_req vm_req;
  1060. int rc = 0;
  1061. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1062. return -EINVAL;
  1063. vm_ops = sde_vm_get_ops(sde_kms);
  1064. ddev = sde_kms->dev;
  1065. crtc = sde_kms_vm_get_vm_crtc(state);
  1066. if (!crtc)
  1067. return 0;
  1068. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1069. cstate = to_sde_crtc_state(new_cstate);
  1070. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1071. if (vm_req != VM_REQ_RELEASE)
  1072. return 0;
  1073. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1074. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1075. drm_for_each_encoder_mask(encoder, crtc->dev,
  1076. crtc->state->encoder_mask) {
  1077. if (sde_encoder_in_clone_mode(encoder))
  1078. continue;
  1079. sde_encoder_irq_control(encoder, false);
  1080. }
  1081. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1082. sde_plane_set_sid(plane, 0);
  1083. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1084. sde_vm_lock(sde_kms);
  1085. if (vm_ops->vm_release)
  1086. rc = vm_ops->vm_release(sde_kms);
  1087. sde_vm_unlock(sde_kms);
  1088. return rc;
  1089. }
  1090. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1091. struct drm_atomic_state *state)
  1092. {
  1093. struct drm_device *ddev;
  1094. struct drm_crtc *crtc;
  1095. struct drm_encoder *encoder;
  1096. struct drm_connector *connector;
  1097. int rc = 0;
  1098. ddev = sde_kms->dev;
  1099. crtc = sde_kms_vm_get_vm_crtc(state);
  1100. if (!crtc)
  1101. return 0;
  1102. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1103. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1104. /* disable ESD work */
  1105. list_for_each_entry(connector,
  1106. &ddev->mode_config.connector_list, head) {
  1107. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1108. sde_connector_schedule_status_work(connector, false);
  1109. }
  1110. /* disable SDE irq's */
  1111. drm_for_each_encoder_mask(encoder, crtc->dev,
  1112. crtc->state->encoder_mask) {
  1113. if (sde_encoder_in_clone_mode(encoder))
  1114. continue;
  1115. sde_encoder_irq_control(encoder, false);
  1116. }
  1117. /* disable IRQ line */
  1118. sde_irq_update(&sde_kms->base, false);
  1119. /* disable vblank events */
  1120. drm_crtc_vblank_off(crtc);
  1121. /* reset sw state */
  1122. sde_crtc_reset_sw_state(crtc);
  1123. return rc;
  1124. }
  1125. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1126. struct drm_atomic_state *state)
  1127. {
  1128. struct sde_vm_ops *vm_ops;
  1129. struct sde_crtc_state *cstate;
  1130. struct drm_crtc *crtc;
  1131. struct drm_crtc_state *new_cstate;
  1132. enum sde_crtc_vm_req vm_req;
  1133. int rc = 0;
  1134. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1135. return -EINVAL;
  1136. vm_ops = sde_vm_get_ops(sde_kms);
  1137. crtc = sde_kms_vm_get_vm_crtc(state);
  1138. if (!crtc)
  1139. return 0;
  1140. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1141. cstate = to_sde_crtc_state(new_cstate);
  1142. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1143. if (vm_req != VM_REQ_RELEASE)
  1144. return 0;
  1145. /* handle SDE pre-release */
  1146. rc = sde_kms_vm_pre_release(sde_kms, state);
  1147. if (rc) {
  1148. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1149. goto exit;
  1150. }
  1151. /* properly handoff color processing features */
  1152. sde_cp_crtc_vm_primary_handoff(crtc);
  1153. /* handle non-SDE clients pre-release */
  1154. if (vm_ops->vm_client_pre_release) {
  1155. rc = vm_ops->vm_client_pre_release(sde_kms);
  1156. if (rc) {
  1157. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1158. rc);
  1159. goto exit;
  1160. }
  1161. }
  1162. sde_vm_lock(sde_kms);
  1163. /* release HW */
  1164. if (vm_ops->vm_release) {
  1165. rc = vm_ops->vm_release(sde_kms);
  1166. if (rc)
  1167. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1168. }
  1169. sde_vm_unlock(sde_kms);
  1170. exit:
  1171. return rc;
  1172. }
  1173. static void sde_kms_complete_commit(struct msm_kms *kms,
  1174. struct drm_atomic_state *old_state)
  1175. {
  1176. struct sde_kms *sde_kms;
  1177. struct msm_drm_private *priv;
  1178. struct drm_crtc *crtc;
  1179. struct drm_crtc_state *old_crtc_state;
  1180. struct drm_connector *connector;
  1181. struct drm_connector_state *old_conn_state;
  1182. struct msm_display_conn_params params;
  1183. struct sde_vm_ops *vm_ops;
  1184. int i, rc = 0;
  1185. if (!kms || !old_state)
  1186. return;
  1187. sde_kms = to_sde_kms(kms);
  1188. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1189. return;
  1190. priv = sde_kms->dev->dev_private;
  1191. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1192. SDE_ERROR("power resource is not enabled\n");
  1193. return;
  1194. }
  1195. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1196. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1197. sde_crtc_complete_commit(crtc, old_crtc_state);
  1198. /* complete secure transitions if any */
  1199. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1200. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1201. }
  1202. for_each_old_connector_in_state(old_state, connector,
  1203. old_conn_state, i) {
  1204. struct sde_connector *c_conn;
  1205. c_conn = to_sde_connector(connector);
  1206. if (!c_conn->ops.post_kickoff)
  1207. continue;
  1208. memset(&params, 0, sizeof(params));
  1209. sde_connector_complete_qsync_commit(connector, &params);
  1210. rc = c_conn->ops.post_kickoff(connector, &params);
  1211. if (rc) {
  1212. pr_err("Connector Post kickoff failed rc=%d\n",
  1213. rc);
  1214. }
  1215. }
  1216. vm_ops = sde_vm_get_ops(sde_kms);
  1217. if (vm_ops && vm_ops->vm_post_commit) {
  1218. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1219. if (rc)
  1220. SDE_ERROR("vm post commit failed, rc = %d\n",
  1221. rc);
  1222. }
  1223. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1224. pm_runtime_put_sync(sde_kms->dev->dev);
  1225. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1226. _sde_kms_release_splash_resource(sde_kms, crtc);
  1227. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1228. SDE_ATRACE_END("sde_kms_complete_commit");
  1229. }
  1230. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1231. struct drm_crtc *crtc)
  1232. {
  1233. struct drm_encoder *encoder;
  1234. struct drm_device *dev;
  1235. int ret;
  1236. bool cwb_disabling;
  1237. if (!kms || !crtc || !crtc->state) {
  1238. SDE_ERROR("invalid params\n");
  1239. return;
  1240. }
  1241. dev = crtc->dev;
  1242. if (!crtc->state->enable) {
  1243. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1244. return;
  1245. }
  1246. if (!crtc->state->active) {
  1247. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1248. return;
  1249. }
  1250. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1251. SDE_ERROR("power resource is not enabled\n");
  1252. return;
  1253. }
  1254. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1255. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1256. cwb_disabling = false;
  1257. if (encoder->crtc != crtc) {
  1258. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1259. crtc);
  1260. if (!cwb_disabling)
  1261. continue;
  1262. }
  1263. /*
  1264. * Wait for post-flush if necessary to delay before
  1265. * plane_cleanup. For example, wait for vsync in case of video
  1266. * mode panels. This may be a no-op for command mode panels.
  1267. */
  1268. SDE_EVT32_VERBOSE(DRMID(crtc));
  1269. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1270. if (ret && ret != -EWOULDBLOCK) {
  1271. SDE_ERROR("wait for commit done returned %d\n", ret);
  1272. sde_crtc_request_frame_reset(crtc);
  1273. break;
  1274. }
  1275. sde_crtc_complete_flip(crtc, NULL);
  1276. if (cwb_disabling)
  1277. sde_encoder_virt_reset(encoder);
  1278. }
  1279. sde_crtc_static_cache_read_kickoff(crtc);
  1280. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1281. }
  1282. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1283. struct drm_atomic_state *old_state)
  1284. {
  1285. struct drm_crtc *crtc;
  1286. struct drm_crtc_state *old_crtc_state;
  1287. int i, rc;
  1288. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1289. SDE_ERROR("invalid argument(s)\n");
  1290. return;
  1291. }
  1292. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1293. retry:
  1294. /* attempt to acquire ww mutex for connection */
  1295. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1296. old_state->acquire_ctx);
  1297. if (rc == -EDEADLK) {
  1298. drm_modeset_backoff(old_state->acquire_ctx);
  1299. goto retry;
  1300. }
  1301. /* old_state actually contains updated crtc pointers */
  1302. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1303. if (crtc->state->active || crtc->state->active_changed)
  1304. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1305. }
  1306. SDE_ATRACE_END("sde_kms_prepare_fence");
  1307. }
  1308. /**
  1309. * _sde_kms_get_displays - query for underlying display handles and cache them
  1310. * @sde_kms: Pointer to sde kms structure
  1311. * Returns: Zero on success
  1312. */
  1313. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1314. {
  1315. int rc = -ENOMEM;
  1316. if (!sde_kms) {
  1317. SDE_ERROR("invalid sde kms\n");
  1318. return -EINVAL;
  1319. }
  1320. /* dsi */
  1321. sde_kms->dsi_displays = NULL;
  1322. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1323. if (sde_kms->dsi_display_count) {
  1324. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1325. sizeof(void *),
  1326. GFP_KERNEL);
  1327. if (!sde_kms->dsi_displays) {
  1328. SDE_ERROR("failed to allocate dsi displays\n");
  1329. goto exit_deinit_dsi;
  1330. }
  1331. sde_kms->dsi_display_count =
  1332. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1333. sde_kms->dsi_display_count);
  1334. }
  1335. /* wb */
  1336. sde_kms->wb_displays = NULL;
  1337. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1338. if (sde_kms->wb_display_count) {
  1339. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1340. sizeof(void *),
  1341. GFP_KERNEL);
  1342. if (!sde_kms->wb_displays) {
  1343. SDE_ERROR("failed to allocate wb displays\n");
  1344. goto exit_deinit_wb;
  1345. }
  1346. sde_kms->wb_display_count =
  1347. wb_display_get_displays(sde_kms->wb_displays,
  1348. sde_kms->wb_display_count);
  1349. }
  1350. /* dp */
  1351. sde_kms->dp_displays = NULL;
  1352. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1353. if (sde_kms->dp_display_count) {
  1354. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1355. sizeof(void *), GFP_KERNEL);
  1356. if (!sde_kms->dp_displays) {
  1357. SDE_ERROR("failed to allocate dp displays\n");
  1358. goto exit_deinit_dp;
  1359. }
  1360. sde_kms->dp_display_count =
  1361. dp_display_get_displays(sde_kms->dp_displays,
  1362. sde_kms->dp_display_count);
  1363. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1364. }
  1365. return 0;
  1366. exit_deinit_dp:
  1367. kfree(sde_kms->dp_displays);
  1368. sde_kms->dp_stream_count = 0;
  1369. sde_kms->dp_display_count = 0;
  1370. sde_kms->dp_displays = NULL;
  1371. exit_deinit_wb:
  1372. kfree(sde_kms->wb_displays);
  1373. sde_kms->wb_display_count = 0;
  1374. sde_kms->wb_displays = NULL;
  1375. exit_deinit_dsi:
  1376. kfree(sde_kms->dsi_displays);
  1377. sde_kms->dsi_display_count = 0;
  1378. sde_kms->dsi_displays = NULL;
  1379. return rc;
  1380. }
  1381. /**
  1382. * _sde_kms_release_displays - release cache of underlying display handles
  1383. * @sde_kms: Pointer to sde kms structure
  1384. */
  1385. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1386. {
  1387. if (!sde_kms) {
  1388. SDE_ERROR("invalid sde kms\n");
  1389. return;
  1390. }
  1391. kfree(sde_kms->wb_displays);
  1392. sde_kms->wb_displays = NULL;
  1393. sde_kms->wb_display_count = 0;
  1394. kfree(sde_kms->dsi_displays);
  1395. sde_kms->dsi_displays = NULL;
  1396. sde_kms->dsi_display_count = 0;
  1397. }
  1398. /**
  1399. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1400. * for underlying displays
  1401. * @dev: Pointer to drm device structure
  1402. * @priv: Pointer to private drm device data
  1403. * @sde_kms: Pointer to sde kms structure
  1404. * Returns: Zero on success
  1405. */
  1406. static int _sde_kms_setup_displays(struct drm_device *dev,
  1407. struct msm_drm_private *priv,
  1408. struct sde_kms *sde_kms)
  1409. {
  1410. static const struct sde_connector_ops dsi_ops = {
  1411. .set_info_blob = dsi_conn_set_info_blob,
  1412. .detect = dsi_conn_detect,
  1413. .get_modes = dsi_connector_get_modes,
  1414. .pre_destroy = dsi_connector_put_modes,
  1415. .mode_valid = dsi_conn_mode_valid,
  1416. .get_info = dsi_display_get_info,
  1417. .set_backlight = dsi_display_set_backlight,
  1418. .soft_reset = dsi_display_soft_reset,
  1419. .pre_kickoff = dsi_conn_pre_kickoff,
  1420. .clk_ctrl = dsi_display_clk_ctrl,
  1421. .set_power = dsi_display_set_power,
  1422. .get_mode_info = dsi_conn_get_mode_info,
  1423. .get_dst_format = dsi_display_get_dst_format,
  1424. .post_kickoff = dsi_conn_post_kickoff,
  1425. .check_status = dsi_display_check_status,
  1426. .enable_event = dsi_conn_enable_event,
  1427. .cmd_transfer = dsi_display_cmd_transfer,
  1428. .cont_splash_config = dsi_display_cont_splash_config,
  1429. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1430. .get_panel_vfp = dsi_display_get_panel_vfp,
  1431. .get_default_lms = dsi_display_get_default_lms,
  1432. .cmd_receive = dsi_display_cmd_receive,
  1433. .install_properties = NULL,
  1434. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1435. .get_qsync_min_fps = dsi_display_get_qsync_min_fps,
  1436. .prepare_commit = dsi_conn_prepare_commit,
  1437. };
  1438. static const struct sde_connector_ops wb_ops = {
  1439. .post_init = sde_wb_connector_post_init,
  1440. .set_info_blob = sde_wb_connector_set_info_blob,
  1441. .detect = sde_wb_connector_detect,
  1442. .get_modes = sde_wb_connector_get_modes,
  1443. .set_property = sde_wb_connector_set_property,
  1444. .get_info = sde_wb_get_info,
  1445. .soft_reset = NULL,
  1446. .get_mode_info = sde_wb_get_mode_info,
  1447. .get_dst_format = NULL,
  1448. .check_status = NULL,
  1449. .cmd_transfer = NULL,
  1450. .cont_splash_config = NULL,
  1451. .cont_splash_res_disable = NULL,
  1452. .get_panel_vfp = NULL,
  1453. .cmd_receive = NULL,
  1454. .install_properties = NULL,
  1455. .set_allowed_mode_switch = NULL,
  1456. };
  1457. static const struct sde_connector_ops dp_ops = {
  1458. .post_init = dp_connector_post_init,
  1459. .detect = dp_connector_detect,
  1460. .get_modes = dp_connector_get_modes,
  1461. .atomic_check = dp_connector_atomic_check,
  1462. .mode_valid = dp_connector_mode_valid,
  1463. .get_info = dp_connector_get_info,
  1464. .get_mode_info = dp_connector_get_mode_info,
  1465. .post_open = dp_connector_post_open,
  1466. .check_status = NULL,
  1467. .set_colorspace = dp_connector_set_colorspace,
  1468. .config_hdr = dp_connector_config_hdr,
  1469. .cmd_transfer = NULL,
  1470. .cont_splash_config = NULL,
  1471. .cont_splash_res_disable = NULL,
  1472. .get_panel_vfp = NULL,
  1473. .update_pps = dp_connector_update_pps,
  1474. .cmd_receive = NULL,
  1475. .install_properties = dp_connector_install_properties,
  1476. .set_allowed_mode_switch = NULL,
  1477. };
  1478. struct msm_display_info info;
  1479. struct drm_encoder *encoder;
  1480. void *display, *connector;
  1481. int i, max_encoders;
  1482. int rc = 0;
  1483. u32 dsc_count = 0, mixer_count = 0;
  1484. u32 max_dp_dsc_count, max_dp_mixer_count;
  1485. if (!dev || !priv || !sde_kms) {
  1486. SDE_ERROR("invalid argument(s)\n");
  1487. return -EINVAL;
  1488. }
  1489. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1490. sde_kms->dp_display_count +
  1491. sde_kms->dp_stream_count;
  1492. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1493. max_encoders = ARRAY_SIZE(priv->encoders);
  1494. SDE_ERROR("capping number of displays to %d", max_encoders);
  1495. }
  1496. /* wb */
  1497. for (i = 0; i < sde_kms->wb_display_count &&
  1498. priv->num_encoders < max_encoders; ++i) {
  1499. display = sde_kms->wb_displays[i];
  1500. encoder = NULL;
  1501. memset(&info, 0x0, sizeof(info));
  1502. rc = sde_wb_get_info(NULL, &info, display);
  1503. if (rc) {
  1504. SDE_ERROR("wb get_info %d failed\n", i);
  1505. continue;
  1506. }
  1507. encoder = sde_encoder_init(dev, &info);
  1508. if (IS_ERR_OR_NULL(encoder)) {
  1509. SDE_ERROR("encoder init failed for wb %d\n", i);
  1510. continue;
  1511. }
  1512. rc = sde_wb_drm_init(display, encoder);
  1513. if (rc) {
  1514. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1515. sde_encoder_destroy(encoder);
  1516. continue;
  1517. }
  1518. connector = sde_connector_init(dev,
  1519. encoder,
  1520. 0,
  1521. display,
  1522. &wb_ops,
  1523. DRM_CONNECTOR_POLL_HPD,
  1524. DRM_MODE_CONNECTOR_VIRTUAL);
  1525. if (connector) {
  1526. priv->encoders[priv->num_encoders++] = encoder;
  1527. priv->connectors[priv->num_connectors++] = connector;
  1528. } else {
  1529. SDE_ERROR("wb %d connector init failed\n", i);
  1530. sde_wb_drm_deinit(display);
  1531. sde_encoder_destroy(encoder);
  1532. }
  1533. }
  1534. /* dsi */
  1535. for (i = 0; i < sde_kms->dsi_display_count &&
  1536. priv->num_encoders < max_encoders; ++i) {
  1537. display = sde_kms->dsi_displays[i];
  1538. encoder = NULL;
  1539. memset(&info, 0x0, sizeof(info));
  1540. rc = dsi_display_get_info(NULL, &info, display);
  1541. if (rc) {
  1542. SDE_ERROR("dsi get_info %d failed\n", i);
  1543. continue;
  1544. }
  1545. encoder = sde_encoder_init(dev, &info);
  1546. if (IS_ERR_OR_NULL(encoder)) {
  1547. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1548. continue;
  1549. }
  1550. rc = dsi_display_drm_bridge_init(display, encoder);
  1551. if (rc) {
  1552. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1553. sde_encoder_destroy(encoder);
  1554. continue;
  1555. }
  1556. connector = sde_connector_init(dev,
  1557. encoder,
  1558. dsi_display_get_drm_panel(display),
  1559. display,
  1560. &dsi_ops,
  1561. DRM_CONNECTOR_POLL_HPD,
  1562. DRM_MODE_CONNECTOR_DSI);
  1563. if (connector) {
  1564. priv->encoders[priv->num_encoders++] = encoder;
  1565. priv->connectors[priv->num_connectors++] = connector;
  1566. } else {
  1567. SDE_ERROR("dsi %d connector init failed\n", i);
  1568. dsi_display_drm_bridge_deinit(display);
  1569. sde_encoder_destroy(encoder);
  1570. continue;
  1571. }
  1572. rc = dsi_display_drm_ext_bridge_init(display,
  1573. encoder, connector);
  1574. if (rc) {
  1575. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1576. dsi_display_drm_bridge_deinit(display);
  1577. sde_connector_destroy(connector);
  1578. sde_encoder_destroy(encoder);
  1579. }
  1580. dsc_count += info.dsc_count;
  1581. mixer_count += info.lm_count;
  1582. }
  1583. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1584. sde_kms->catalog->mixer_count - mixer_count : 0;
  1585. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1586. sde_kms->catalog->dsc_count - dsc_count : 0;
  1587. /* dp */
  1588. for (i = 0; i < sde_kms->dp_display_count &&
  1589. priv->num_encoders < max_encoders; ++i) {
  1590. int idx;
  1591. display = sde_kms->dp_displays[i];
  1592. encoder = NULL;
  1593. memset(&info, 0x0, sizeof(info));
  1594. rc = dp_connector_get_info(NULL, &info, display);
  1595. if (rc) {
  1596. SDE_ERROR("dp get_info %d failed\n", i);
  1597. continue;
  1598. }
  1599. encoder = sde_encoder_init(dev, &info);
  1600. if (IS_ERR_OR_NULL(encoder)) {
  1601. SDE_ERROR("dp encoder init failed %d\n", i);
  1602. continue;
  1603. }
  1604. rc = dp_drm_bridge_init(display, encoder,
  1605. max_dp_mixer_count, max_dp_dsc_count);
  1606. if (rc) {
  1607. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1608. sde_encoder_destroy(encoder);
  1609. continue;
  1610. }
  1611. connector = sde_connector_init(dev,
  1612. encoder,
  1613. NULL,
  1614. display,
  1615. &dp_ops,
  1616. DRM_CONNECTOR_POLL_HPD,
  1617. DRM_MODE_CONNECTOR_DisplayPort);
  1618. if (connector) {
  1619. priv->encoders[priv->num_encoders++] = encoder;
  1620. priv->connectors[priv->num_connectors++] = connector;
  1621. } else {
  1622. SDE_ERROR("dp %d connector init failed\n", i);
  1623. dp_drm_bridge_deinit(display);
  1624. sde_encoder_destroy(encoder);
  1625. }
  1626. /* update display cap to MST_MODE for DP MST encoders */
  1627. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1628. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1629. priv->num_encoders < max_encoders; idx++) {
  1630. info.h_tile_instance[0] = idx;
  1631. encoder = sde_encoder_init(dev, &info);
  1632. if (IS_ERR_OR_NULL(encoder)) {
  1633. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1634. continue;
  1635. }
  1636. rc = dp_mst_drm_bridge_init(display, encoder);
  1637. if (rc) {
  1638. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1639. i, rc);
  1640. sde_encoder_destroy(encoder);
  1641. continue;
  1642. }
  1643. priv->encoders[priv->num_encoders++] = encoder;
  1644. }
  1645. }
  1646. return 0;
  1647. }
  1648. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1649. {
  1650. struct msm_drm_private *priv;
  1651. int i;
  1652. if (!sde_kms) {
  1653. SDE_ERROR("invalid sde_kms\n");
  1654. return;
  1655. } else if (!sde_kms->dev) {
  1656. SDE_ERROR("invalid dev\n");
  1657. return;
  1658. } else if (!sde_kms->dev->dev_private) {
  1659. SDE_ERROR("invalid dev_private\n");
  1660. return;
  1661. }
  1662. priv = sde_kms->dev->dev_private;
  1663. for (i = 0; i < priv->num_crtcs; i++)
  1664. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1665. priv->num_crtcs = 0;
  1666. for (i = 0; i < priv->num_planes; i++)
  1667. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1668. priv->num_planes = 0;
  1669. for (i = 0; i < priv->num_connectors; i++)
  1670. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1671. priv->num_connectors = 0;
  1672. for (i = 0; i < priv->num_encoders; i++)
  1673. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1674. priv->num_encoders = 0;
  1675. _sde_kms_release_displays(sde_kms);
  1676. }
  1677. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1678. {
  1679. struct drm_device *dev;
  1680. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1681. struct drm_crtc *crtc;
  1682. struct msm_drm_private *priv;
  1683. struct sde_mdss_cfg *catalog;
  1684. int primary_planes_idx = 0, i, ret;
  1685. int max_crtc_count;
  1686. u32 sspp_id[MAX_PLANES];
  1687. u32 master_plane_id[MAX_PLANES];
  1688. u32 num_virt_planes = 0;
  1689. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1690. SDE_ERROR("invalid sde_kms\n");
  1691. return -EINVAL;
  1692. }
  1693. dev = sde_kms->dev;
  1694. priv = dev->dev_private;
  1695. catalog = sde_kms->catalog;
  1696. ret = sde_core_irq_domain_add(sde_kms);
  1697. if (ret)
  1698. goto fail_irq;
  1699. /*
  1700. * Query for underlying display drivers, and create connectors,
  1701. * bridges and encoders for them.
  1702. */
  1703. if (!_sde_kms_get_displays(sde_kms))
  1704. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1705. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1706. /* Create the planes */
  1707. for (i = 0; i < catalog->sspp_count; i++) {
  1708. bool primary = true;
  1709. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1710. || primary_planes_idx >= max_crtc_count)
  1711. primary = false;
  1712. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1713. (1UL << max_crtc_count) - 1, 0);
  1714. if (IS_ERR(plane)) {
  1715. SDE_ERROR("sde_plane_init failed\n");
  1716. ret = PTR_ERR(plane);
  1717. goto fail;
  1718. }
  1719. priv->planes[priv->num_planes++] = plane;
  1720. if (primary)
  1721. primary_planes[primary_planes_idx++] = plane;
  1722. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1723. sde_is_custom_client()) {
  1724. int priority =
  1725. catalog->sspp[i].sblk->smart_dma_priority;
  1726. sspp_id[priority - 1] = catalog->sspp[i].id;
  1727. master_plane_id[priority - 1] = plane->base.id;
  1728. num_virt_planes++;
  1729. }
  1730. }
  1731. /* Initialize smart DMA virtual planes */
  1732. for (i = 0; i < num_virt_planes; i++) {
  1733. plane = sde_plane_init(dev, sspp_id[i], false,
  1734. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1735. if (IS_ERR(plane)) {
  1736. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1737. ret = PTR_ERR(plane);
  1738. goto fail;
  1739. }
  1740. priv->planes[priv->num_planes++] = plane;
  1741. }
  1742. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1743. /* Create one CRTC per encoder */
  1744. for (i = 0; i < max_crtc_count; i++) {
  1745. crtc = sde_crtc_init(dev, primary_planes[i]);
  1746. if (IS_ERR(crtc)) {
  1747. ret = PTR_ERR(crtc);
  1748. goto fail;
  1749. }
  1750. priv->crtcs[priv->num_crtcs++] = crtc;
  1751. }
  1752. if (sde_is_custom_client()) {
  1753. /* All CRTCs are compatible with all planes */
  1754. for (i = 0; i < priv->num_planes; i++)
  1755. priv->planes[i]->possible_crtcs =
  1756. (1 << priv->num_crtcs) - 1;
  1757. }
  1758. /* All CRTCs are compatible with all encoders */
  1759. for (i = 0; i < priv->num_encoders; i++)
  1760. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1761. return 0;
  1762. fail:
  1763. _sde_kms_drm_obj_destroy(sde_kms);
  1764. fail_irq:
  1765. sde_core_irq_domain_fini(sde_kms);
  1766. return ret;
  1767. }
  1768. /**
  1769. * sde_kms_timeline_status - provides current timeline status
  1770. * This API should be called without mode config lock.
  1771. * @dev: Pointer to drm device
  1772. */
  1773. void sde_kms_timeline_status(struct drm_device *dev)
  1774. {
  1775. struct drm_crtc *crtc;
  1776. struct drm_connector *conn;
  1777. struct drm_connector_list_iter conn_iter;
  1778. if (!dev) {
  1779. SDE_ERROR("invalid drm device node\n");
  1780. return;
  1781. }
  1782. drm_for_each_crtc(crtc, dev)
  1783. sde_crtc_timeline_status(crtc);
  1784. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1785. /*
  1786. *Probably locked from last close dumping status anyway
  1787. */
  1788. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1789. drm_connector_list_iter_begin(dev, &conn_iter);
  1790. drm_for_each_connector_iter(conn, &conn_iter)
  1791. sde_conn_timeline_status(conn);
  1792. drm_connector_list_iter_end(&conn_iter);
  1793. return;
  1794. }
  1795. mutex_lock(&dev->mode_config.mutex);
  1796. drm_connector_list_iter_begin(dev, &conn_iter);
  1797. drm_for_each_connector_iter(conn, &conn_iter)
  1798. sde_conn_timeline_status(conn);
  1799. drm_connector_list_iter_end(&conn_iter);
  1800. mutex_unlock(&dev->mode_config.mutex);
  1801. }
  1802. static int sde_kms_postinit(struct msm_kms *kms)
  1803. {
  1804. struct sde_kms *sde_kms = to_sde_kms(kms);
  1805. struct drm_device *dev;
  1806. struct drm_crtc *crtc;
  1807. int rc;
  1808. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1809. SDE_ERROR("invalid sde_kms\n");
  1810. return -EINVAL;
  1811. }
  1812. dev = sde_kms->dev;
  1813. rc = _sde_debugfs_init(sde_kms);
  1814. if (rc)
  1815. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1816. drm_for_each_crtc(crtc, dev)
  1817. sde_crtc_post_init(dev, crtc);
  1818. return rc;
  1819. }
  1820. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1821. struct drm_encoder *encoder)
  1822. {
  1823. return rate;
  1824. }
  1825. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1826. struct platform_device *pdev)
  1827. {
  1828. struct drm_device *dev;
  1829. struct msm_drm_private *priv;
  1830. struct sde_vm_ops *vm_ops;
  1831. int i;
  1832. if (!sde_kms || !pdev)
  1833. return;
  1834. dev = sde_kms->dev;
  1835. if (!dev)
  1836. return;
  1837. priv = dev->dev_private;
  1838. if (!priv)
  1839. return;
  1840. if (sde_kms->genpd_init) {
  1841. sde_kms->genpd_init = false;
  1842. pm_genpd_remove(&sde_kms->genpd);
  1843. of_genpd_del_provider(pdev->dev.of_node);
  1844. }
  1845. vm_ops = sde_vm_get_ops(sde_kms);
  1846. if (vm_ops && vm_ops->vm_deinit)
  1847. vm_ops->vm_deinit(sde_kms, vm_ops);
  1848. if (sde_kms->hw_intr)
  1849. sde_hw_intr_destroy(sde_kms->hw_intr);
  1850. sde_kms->hw_intr = NULL;
  1851. if (sde_kms->power_event)
  1852. sde_power_handle_unregister_event(
  1853. &priv->phandle, sde_kms->power_event);
  1854. _sde_kms_release_displays(sde_kms);
  1855. _sde_kms_unmap_all_splash_regions(sde_kms);
  1856. if (sde_kms->catalog) {
  1857. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1858. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1859. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1860. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1861. }
  1862. }
  1863. if (sde_kms->rm_init)
  1864. sde_rm_destroy(&sde_kms->rm);
  1865. sde_kms->rm_init = false;
  1866. if (sde_kms->catalog)
  1867. sde_hw_catalog_deinit(sde_kms->catalog);
  1868. sde_kms->catalog = NULL;
  1869. if (sde_kms->sid)
  1870. msm_iounmap(pdev, sde_kms->sid);
  1871. sde_kms->sid = NULL;
  1872. if (sde_kms->reg_dma)
  1873. msm_iounmap(pdev, sde_kms->reg_dma);
  1874. sde_kms->reg_dma = NULL;
  1875. if (sde_kms->vbif[VBIF_NRT])
  1876. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1877. sde_kms->vbif[VBIF_NRT] = NULL;
  1878. if (sde_kms->vbif[VBIF_RT])
  1879. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1880. sde_kms->vbif[VBIF_RT] = NULL;
  1881. if (sde_kms->mmio)
  1882. msm_iounmap(pdev, sde_kms->mmio);
  1883. sde_kms->mmio = NULL;
  1884. sde_reg_dma_deinit();
  1885. _sde_kms_mmu_destroy(sde_kms);
  1886. }
  1887. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1888. {
  1889. int i;
  1890. if (!sde_kms)
  1891. return -EINVAL;
  1892. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1893. struct msm_mmu *mmu;
  1894. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1895. if (!aspace)
  1896. continue;
  1897. mmu = sde_kms->aspace[i]->mmu;
  1898. if (secure_only &&
  1899. !aspace->mmu->funcs->is_domain_secure(mmu))
  1900. continue;
  1901. /* cleanup aspace before detaching */
  1902. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1903. SDE_DEBUG("Detaching domain:%d\n", i);
  1904. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1905. ARRAY_SIZE(iommu_ports));
  1906. aspace->domain_attached = false;
  1907. }
  1908. return 0;
  1909. }
  1910. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1911. {
  1912. int i;
  1913. if (!sde_kms)
  1914. return -EINVAL;
  1915. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1916. struct msm_mmu *mmu;
  1917. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1918. if (!aspace)
  1919. continue;
  1920. mmu = sde_kms->aspace[i]->mmu;
  1921. if (secure_only &&
  1922. !aspace->mmu->funcs->is_domain_secure(mmu))
  1923. continue;
  1924. SDE_DEBUG("Attaching domain:%d\n", i);
  1925. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1926. ARRAY_SIZE(iommu_ports));
  1927. aspace->domain_attached = true;
  1928. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1929. }
  1930. return 0;
  1931. }
  1932. static void sde_kms_destroy(struct msm_kms *kms)
  1933. {
  1934. struct sde_kms *sde_kms;
  1935. struct drm_device *dev;
  1936. if (!kms) {
  1937. SDE_ERROR("invalid kms\n");
  1938. return;
  1939. }
  1940. sde_kms = to_sde_kms(kms);
  1941. dev = sde_kms->dev;
  1942. if (!dev || !dev->dev) {
  1943. SDE_ERROR("invalid device\n");
  1944. return;
  1945. }
  1946. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1947. kfree(sde_kms);
  1948. }
  1949. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1950. struct drm_atomic_state *state)
  1951. {
  1952. struct drm_device *dev = sde_kms->dev;
  1953. struct drm_plane *plane;
  1954. struct drm_plane_state *plane_state;
  1955. struct drm_crtc *crtc;
  1956. struct drm_crtc_state *crtc_state;
  1957. struct drm_connector *conn;
  1958. struct drm_connector_state *conn_state;
  1959. struct drm_connector_list_iter conn_iter;
  1960. int ret = 0;
  1961. drm_for_each_plane(plane, dev) {
  1962. plane_state = drm_atomic_get_plane_state(state, plane);
  1963. if (IS_ERR(plane_state)) {
  1964. ret = PTR_ERR(plane_state);
  1965. SDE_ERROR("error %d getting plane %d state\n",
  1966. ret, DRMID(plane));
  1967. return ret;
  1968. }
  1969. ret = sde_plane_helper_reset_custom_properties(plane,
  1970. plane_state);
  1971. if (ret) {
  1972. SDE_ERROR("error %d resetting plane props %d\n",
  1973. ret, DRMID(plane));
  1974. return ret;
  1975. }
  1976. }
  1977. drm_for_each_crtc(crtc, dev) {
  1978. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1979. if (IS_ERR(crtc_state)) {
  1980. ret = PTR_ERR(crtc_state);
  1981. SDE_ERROR("error %d getting crtc %d state\n",
  1982. ret, DRMID(crtc));
  1983. return ret;
  1984. }
  1985. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1986. if (ret) {
  1987. SDE_ERROR("error %d resetting crtc props %d\n",
  1988. ret, DRMID(crtc));
  1989. return ret;
  1990. }
  1991. }
  1992. drm_connector_list_iter_begin(dev, &conn_iter);
  1993. drm_for_each_connector_iter(conn, &conn_iter) {
  1994. conn_state = drm_atomic_get_connector_state(state, conn);
  1995. if (IS_ERR(conn_state)) {
  1996. ret = PTR_ERR(conn_state);
  1997. SDE_ERROR("error %d getting connector %d state\n",
  1998. ret, DRMID(conn));
  1999. return ret;
  2000. }
  2001. ret = sde_connector_helper_reset_custom_properties(conn,
  2002. conn_state);
  2003. if (ret) {
  2004. SDE_ERROR("error %d resetting connector props %d\n",
  2005. ret, DRMID(conn));
  2006. return ret;
  2007. }
  2008. }
  2009. drm_connector_list_iter_end(&conn_iter);
  2010. return ret;
  2011. }
  2012. static void sde_kms_lastclose(struct msm_kms *kms)
  2013. {
  2014. struct sde_kms *sde_kms;
  2015. struct drm_device *dev;
  2016. struct drm_atomic_state *state;
  2017. struct drm_modeset_acquire_ctx ctx;
  2018. int ret;
  2019. if (!kms) {
  2020. SDE_ERROR("invalid argument\n");
  2021. return;
  2022. }
  2023. sde_kms = to_sde_kms(kms);
  2024. dev = sde_kms->dev;
  2025. drm_modeset_acquire_init(&ctx, 0);
  2026. state = drm_atomic_state_alloc(dev);
  2027. if (!state) {
  2028. ret = -ENOMEM;
  2029. goto out_ctx;
  2030. }
  2031. state->acquire_ctx = &ctx;
  2032. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2033. retry:
  2034. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2035. if (ret)
  2036. goto out_state;
  2037. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2038. if (ret)
  2039. goto out_state;
  2040. ret = drm_atomic_commit(state);
  2041. out_state:
  2042. if (ret == -EDEADLK)
  2043. goto backoff;
  2044. drm_atomic_state_put(state);
  2045. out_ctx:
  2046. drm_modeset_drop_locks(&ctx);
  2047. drm_modeset_acquire_fini(&ctx);
  2048. if (ret)
  2049. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2050. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2051. return;
  2052. backoff:
  2053. drm_atomic_state_clear(state);
  2054. drm_modeset_backoff(&ctx);
  2055. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2056. goto retry;
  2057. }
  2058. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2059. struct drm_atomic_state *state)
  2060. {
  2061. struct sde_kms *sde_kms;
  2062. struct drm_device *dev;
  2063. struct drm_crtc *crtc;
  2064. struct drm_encoder *encoder;
  2065. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2066. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2067. uint32_t crtc_encoder_cnt = 0;
  2068. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2069. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2070. struct sde_vm_ops *vm_ops;
  2071. bool vm_req_active = false;
  2072. enum sde_crtc_idle_pc_state idle_pc_state;
  2073. struct sde_mdss_cfg *catalog;
  2074. int rc = 0;
  2075. struct sde_connector *sde_conn;
  2076. struct dsi_display *dsi_display;
  2077. struct drm_connector *connector;
  2078. struct drm_connector_state *new_connstate;
  2079. if (!kms || !state)
  2080. return -EINVAL;
  2081. sde_kms = to_sde_kms(kms);
  2082. dev = sde_kms->dev;
  2083. catalog = sde_kms->catalog;
  2084. vm_ops = sde_vm_get_ops(sde_kms);
  2085. if (!vm_ops)
  2086. return 0;
  2087. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw ||
  2088. !vm_ops->vm_acquire)
  2089. return -EINVAL;
  2090. sde_vm_lock(sde_kms);
  2091. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2092. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2093. if (!new_cstate->active && !old_cstate->active)
  2094. continue;
  2095. new_state = to_sde_crtc_state(new_cstate);
  2096. new_vm_req = sde_crtc_get_property(new_state,
  2097. CRTC_PROP_VM_REQ_STATE);
  2098. old_state = to_sde_crtc_state(old_cstate);
  2099. old_vm_req = sde_crtc_get_property(old_state,
  2100. CRTC_PROP_VM_REQ_STATE);
  2101. /*
  2102. * No active request if the transition is from
  2103. * VM_REQ_NONE to VM_REQ_NONE
  2104. */
  2105. if (old_vm_req || new_vm_req) {
  2106. rc = vm_ops->vm_request_valid(sde_kms,
  2107. old_vm_req, new_vm_req);
  2108. if (rc) {
  2109. SDE_ERROR(
  2110. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2111. old_vm_req, new_vm_req,
  2112. vm_ops->vm_owns_hw(sde_kms), rc);
  2113. goto end;
  2114. } else if (old_vm_req == VM_REQ_ACQUIRE &&
  2115. new_vm_req == VM_REQ_NONE) {
  2116. SDE_DEBUG(
  2117. "VM transition valid; ignore further checks\n");
  2118. } else {
  2119. vm_req_active = true;
  2120. }
  2121. }
  2122. idle_pc_state = sde_crtc_get_property(new_state,
  2123. CRTC_PROP_IDLE_PC_STATE);
  2124. active_crtc = crtc;
  2125. active_cstate = new_cstate;
  2126. commit_crtc_cnt++;
  2127. }
  2128. /* return early if no active vm request */
  2129. if (!vm_req_active)
  2130. goto end;
  2131. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2132. if (!crtc->state->active)
  2133. continue;
  2134. global_crtc_cnt++;
  2135. global_active_crtc = crtc;
  2136. }
  2137. if (active_crtc) {
  2138. drm_for_each_encoder_mask(encoder, active_crtc->dev,
  2139. active_cstate->encoder_mask)
  2140. crtc_encoder_cnt++;
  2141. }
  2142. SDE_EVT32(old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2143. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d\n", old_vm_req,
  2144. new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2145. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2146. int conn_mask = active_cstate->connector_mask;
  2147. if (drm_connector_mask(connector) & conn_mask) {
  2148. sde_conn = to_sde_connector(connector);
  2149. dsi_display = (struct dsi_display *) sde_conn->display;
  2150. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i,
  2151. dsi_display->type,
  2152. dsi_display->trusted_vm_env);
  2153. SDE_DEBUG(
  2154. "VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d,",
  2155. dsi_display->name, DRMID(connector),
  2156. DRMID(active_crtc), dsi_display->type,
  2157. dsi_display->trusted_vm_env);
  2158. break;
  2159. }
  2160. }
  2161. /* Check for single crtc commits only on valid VM requests */
  2162. if (active_crtc && global_active_crtc &&
  2163. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2164. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2165. active_crtc != global_active_crtc)) {
  2166. SDE_ERROR(
  2167. "VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2168. catalog->max_trusted_vm_displays,
  2169. commit_crtc_cnt, global_crtc_cnt, DRMID(active_crtc),
  2170. DRMID(global_active_crtc));
  2171. rc = -E2BIG;
  2172. goto end;
  2173. } else if ((new_vm_req == VM_REQ_RELEASE) &&
  2174. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2175. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2176. /*
  2177. * disable idle-pc before releasing the HW
  2178. * allow only specified number of encoders on a given crtc
  2179. */
  2180. SDE_ERROR(
  2181. "VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2182. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC,
  2183. crtc_encoder_cnt);
  2184. rc = -EINVAL;
  2185. goto end;
  2186. }
  2187. if ((new_vm_req == VM_REQ_ACQUIRE) && !vm_ops->vm_owns_hw(sde_kms)) {
  2188. rc = vm_ops->vm_acquire(sde_kms);
  2189. if (rc) {
  2190. SDE_ERROR(
  2191. "VM acquire failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2192. old_vm_req, new_vm_req,
  2193. vm_ops->vm_owns_hw(sde_kms), rc);
  2194. goto end;
  2195. }
  2196. if (vm_ops->vm_resource_init)
  2197. rc = vm_ops->vm_resource_init(sde_kms, state);
  2198. }
  2199. end:
  2200. sde_vm_unlock(sde_kms);
  2201. return rc;
  2202. }
  2203. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2204. struct drm_atomic_state *state)
  2205. {
  2206. struct sde_kms *sde_kms;
  2207. struct drm_device *dev;
  2208. struct drm_crtc *crtc;
  2209. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2210. struct drm_crtc_state *crtc_state;
  2211. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2212. bool sec_session = false, global_sec_session = false;
  2213. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2214. int i;
  2215. if (!kms || !state) {
  2216. return -EINVAL;
  2217. SDE_ERROR("invalid arguments\n");
  2218. }
  2219. sde_kms = to_sde_kms(kms);
  2220. dev = sde_kms->dev;
  2221. /* iterate state object for active secure/non-secure crtc */
  2222. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2223. if (!crtc_state->active)
  2224. continue;
  2225. active_crtc_cnt++;
  2226. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2227. &fb_sec, &fb_sec_dir);
  2228. if (fb_sec_dir)
  2229. sec_session = true;
  2230. cur_crtc = crtc;
  2231. }
  2232. /* iterate global list for active and secure/non-secure crtc */
  2233. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2234. if (!crtc->state->active)
  2235. continue;
  2236. global_active_crtc_cnt++;
  2237. /* update only when crtc is not the same as current crtc */
  2238. if (crtc != cur_crtc) {
  2239. fb_ns = fb_sec = fb_sec_dir = 0;
  2240. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2241. &fb_sec, &fb_sec_dir);
  2242. if (fb_sec_dir)
  2243. global_sec_session = true;
  2244. global_crtc = crtc;
  2245. }
  2246. }
  2247. if (!global_sec_session && !sec_session)
  2248. return 0;
  2249. /*
  2250. * - fail crtc commit, if secure-camera/secure-ui session is
  2251. * in-progress in any other display
  2252. * - fail secure-camera/secure-ui crtc commit, if any other display
  2253. * session is in-progress
  2254. */
  2255. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2256. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2257. SDE_ERROR(
  2258. "crtc%d secure check failed global_active:%d active:%d\n",
  2259. cur_crtc ? cur_crtc->base.id : -1,
  2260. global_active_crtc_cnt, active_crtc_cnt);
  2261. return -EPERM;
  2262. /*
  2263. * As only one crtc is allowed during secure session, the crtc
  2264. * in this commit should match with the global crtc
  2265. */
  2266. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2267. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2268. cur_crtc->base.id, sec_session,
  2269. global_crtc->base.id, global_sec_session);
  2270. return -EPERM;
  2271. }
  2272. return 0;
  2273. }
  2274. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2275. struct drm_atomic_state *state)
  2276. {
  2277. struct drm_crtc *crtc;
  2278. struct drm_crtc_state *new_cstate;
  2279. struct sde_crtc_state *cstate;
  2280. struct sde_vm_ops *vm_ops;
  2281. enum sde_crtc_vm_req vm_req;
  2282. struct sde_kms *sde_kms = to_sde_kms(kms);
  2283. vm_ops = sde_vm_get_ops(sde_kms);
  2284. if (!vm_ops)
  2285. return;
  2286. crtc = sde_kms_vm_get_vm_crtc(state);
  2287. if (!crtc)
  2288. return;
  2289. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2290. cstate = to_sde_crtc_state(new_cstate);
  2291. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2292. if (vm_req != VM_REQ_ACQUIRE)
  2293. return;
  2294. sde_vm_lock(sde_kms);
  2295. if (vm_ops->vm_acquire_fail_handler)
  2296. vm_ops->vm_acquire_fail_handler(sde_kms);
  2297. sde_vm_unlock(sde_kms);
  2298. }
  2299. static int sde_kms_atomic_check(struct msm_kms *kms,
  2300. struct drm_atomic_state *state)
  2301. {
  2302. struct sde_kms *sde_kms;
  2303. struct drm_device *dev;
  2304. int ret;
  2305. if (!kms || !state)
  2306. return -EINVAL;
  2307. sde_kms = to_sde_kms(kms);
  2308. dev = sde_kms->dev;
  2309. SDE_ATRACE_BEGIN("atomic_check");
  2310. if (sde_kms_is_suspend_blocked(dev)) {
  2311. SDE_DEBUG("suspended, skip atomic_check\n");
  2312. ret = -EBUSY;
  2313. goto end;
  2314. }
  2315. ret = sde_kms_check_vm_request(kms, state);
  2316. if (ret) {
  2317. SDE_ERROR("vm switch request checks failed\n");
  2318. goto end;
  2319. }
  2320. ret = drm_atomic_helper_check(dev, state);
  2321. if (ret)
  2322. goto vm_clean_up;
  2323. /*
  2324. * Check if any secure transition(moving CRTC between secure and
  2325. * non-secure state and vice-versa) is allowed or not. when moving
  2326. * to secure state, planes with fb_mode set to dir_translated only can
  2327. * be staged on the CRTC, and only one CRTC can be active during
  2328. * Secure state
  2329. */
  2330. ret = sde_kms_check_secure_transition(kms, state);
  2331. if (ret)
  2332. goto vm_clean_up;
  2333. goto end;
  2334. vm_clean_up:
  2335. sde_kms_vm_res_release(kms, state);
  2336. end:
  2337. SDE_ATRACE_END("atomic_check");
  2338. return ret;
  2339. }
  2340. static struct msm_gem_address_space*
  2341. _sde_kms_get_address_space(struct msm_kms *kms,
  2342. unsigned int domain)
  2343. {
  2344. struct sde_kms *sde_kms;
  2345. if (!kms) {
  2346. SDE_ERROR("invalid kms\n");
  2347. return NULL;
  2348. }
  2349. sde_kms = to_sde_kms(kms);
  2350. if (!sde_kms) {
  2351. SDE_ERROR("invalid sde_kms\n");
  2352. return NULL;
  2353. }
  2354. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2355. return NULL;
  2356. return (sde_kms->aspace[domain] &&
  2357. sde_kms->aspace[domain]->domain_attached) ?
  2358. sde_kms->aspace[domain] : NULL;
  2359. }
  2360. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2361. unsigned int domain)
  2362. {
  2363. struct sde_kms *sde_kms;
  2364. struct msm_gem_address_space *aspace;
  2365. if (!kms) {
  2366. SDE_ERROR("invalid kms\n");
  2367. return NULL;
  2368. }
  2369. sde_kms = to_sde_kms(kms);
  2370. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2371. SDE_ERROR("invalid params\n");
  2372. return NULL;
  2373. }
  2374. aspace = _sde_kms_get_address_space(kms, domain);
  2375. return (aspace && aspace->domain_attached) ?
  2376. msm_gem_get_aspace_device(aspace) : NULL;
  2377. }
  2378. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2379. {
  2380. struct drm_device *dev = NULL;
  2381. struct sde_kms *sde_kms = NULL;
  2382. struct drm_connector *connector = NULL;
  2383. struct drm_connector_list_iter conn_iter;
  2384. struct sde_connector *sde_conn = NULL;
  2385. if (!kms) {
  2386. SDE_ERROR("invalid kms\n");
  2387. return;
  2388. }
  2389. sde_kms = to_sde_kms(kms);
  2390. dev = sde_kms->dev;
  2391. if (!dev) {
  2392. SDE_ERROR("invalid device\n");
  2393. return;
  2394. }
  2395. if (!dev->mode_config.poll_enabled)
  2396. return;
  2397. mutex_lock(&dev->mode_config.mutex);
  2398. drm_connector_list_iter_begin(dev, &conn_iter);
  2399. drm_for_each_connector_iter(connector, &conn_iter) {
  2400. /* Only handle HPD capable connectors. */
  2401. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2402. continue;
  2403. sde_conn = to_sde_connector(connector);
  2404. if (sde_conn->ops.post_open)
  2405. sde_conn->ops.post_open(&sde_conn->base,
  2406. sde_conn->display);
  2407. }
  2408. drm_connector_list_iter_end(&conn_iter);
  2409. mutex_unlock(&dev->mode_config.mutex);
  2410. }
  2411. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2412. struct sde_splash_display *splash_display,
  2413. struct drm_crtc *crtc)
  2414. {
  2415. struct msm_drm_private *priv;
  2416. struct drm_plane *plane;
  2417. struct sde_splash_mem *splash;
  2418. enum sde_sspp plane_id;
  2419. bool is_virtual;
  2420. int i, j;
  2421. if (!sde_kms || !splash_display || !crtc) {
  2422. SDE_ERROR("invalid input args\n");
  2423. return -EINVAL;
  2424. }
  2425. priv = sde_kms->dev->dev_private;
  2426. for (i = 0; i < priv->num_planes; i++) {
  2427. plane = priv->planes[i];
  2428. plane_id = sde_plane_pipe(plane);
  2429. is_virtual = is_sde_plane_virtual(plane);
  2430. splash = splash_display->splash;
  2431. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2432. if ((plane_id != splash_display->pipes[j].sspp) ||
  2433. (splash_display->pipes[j].is_virtual
  2434. != is_virtual))
  2435. continue;
  2436. if (splash && sde_plane_validate_src_addr(plane,
  2437. splash->splash_buf_base,
  2438. splash->splash_buf_size)) {
  2439. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2440. plane_id, crtc->base.id);
  2441. }
  2442. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2443. crtc->base.id, plane_id, is_virtual);
  2444. }
  2445. }
  2446. return 0;
  2447. }
  2448. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2449. struct dsi_display *dsi_display)
  2450. {
  2451. void *display;
  2452. struct drm_encoder *encoder = NULL;
  2453. struct msm_display_info info;
  2454. struct drm_device *dev;
  2455. struct sde_kms *sde_kms;
  2456. struct drm_connector_list_iter conn_iter;
  2457. struct drm_connector *connector = NULL;
  2458. struct sde_connector *sde_conn = NULL;
  2459. int rc = 0;
  2460. sde_kms = to_sde_kms(kms);
  2461. dev = sde_kms->dev;
  2462. display = dsi_display;
  2463. if (dsi_display) {
  2464. if (dsi_display->bridge->base.encoder) {
  2465. encoder = dsi_display->bridge->base.encoder;
  2466. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2467. }
  2468. memset(&info, 0x0, sizeof(info));
  2469. rc = dsi_display_get_info(NULL, &info, display);
  2470. if (rc) {
  2471. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2472. rc, __func__);
  2473. encoder = NULL;
  2474. }
  2475. }
  2476. drm_connector_list_iter_begin(dev, &conn_iter);
  2477. drm_for_each_connector_iter(connector, &conn_iter) {
  2478. /**
  2479. * Inform cont_splash is disabled to each interface/connector.
  2480. * This is currently supported for DSI interface.
  2481. */
  2482. sde_conn = to_sde_connector(connector);
  2483. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2484. if (!dsi_display || !encoder) {
  2485. sde_conn->ops.cont_splash_res_disable
  2486. (sde_conn->display);
  2487. } else if (connector->encoder_ids[0]
  2488. == encoder->base.id) {
  2489. /**
  2490. * This handles dual DSI
  2491. * configuration where one DSI
  2492. * interface has cont_splash
  2493. * enabled and the other doesn't.
  2494. */
  2495. sde_conn->ops.cont_splash_res_disable
  2496. (sde_conn->display);
  2497. break;
  2498. }
  2499. }
  2500. }
  2501. drm_connector_list_iter_end(&conn_iter);
  2502. return 0;
  2503. }
  2504. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2505. {
  2506. int i;
  2507. void *display;
  2508. struct dsi_display *dsi_display;
  2509. struct drm_encoder *encoder;
  2510. if (!sde_kms)
  2511. return -EINVAL;
  2512. if (!sde_in_trusted_vm(sde_kms))
  2513. return 0;
  2514. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2515. display = sde_kms->dsi_displays[i];
  2516. dsi_display = (struct dsi_display *)display;
  2517. if (!dsi_display->bridge->base.encoder) {
  2518. SDE_ERROR("no encoder on dsi display:%d", i);
  2519. return -EINVAL;
  2520. }
  2521. encoder = dsi_display->bridge->base.encoder;
  2522. encoder->possible_crtcs = 1 << i;
  2523. SDE_DEBUG(
  2524. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2525. encoder->index, encoder->base.id,
  2526. encoder->name, encoder->possible_crtcs);
  2527. }
  2528. return 0;
  2529. }
  2530. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2531. struct sde_kms *sde_kms, struct drm_connector *connector,
  2532. struct drm_atomic_state *state)
  2533. {
  2534. struct drm_display_mode *mode, *cur_mode = NULL;
  2535. struct drm_crtc *crtc;
  2536. struct drm_crtc_state *new_cstate, *old_cstate;
  2537. u32 i = 0;
  2538. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2539. list_for_each_entry(mode, &connector->modes, head) {
  2540. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2541. cur_mode = mode;
  2542. break;
  2543. }
  2544. }
  2545. } else if (state) {
  2546. /* get the mode from first atomic_check phase for trusted_vm*/
  2547. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2548. new_cstate, i) {
  2549. if (!new_cstate->active && !old_cstate->active)
  2550. continue;
  2551. list_for_each_entry(mode, &connector->modes, head) {
  2552. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2553. cur_mode = mode;
  2554. break;
  2555. }
  2556. }
  2557. }
  2558. }
  2559. return cur_mode;
  2560. }
  2561. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2562. struct drm_atomic_state *state)
  2563. {
  2564. void *display;
  2565. struct dsi_display *dsi_display;
  2566. struct msm_display_info info;
  2567. struct drm_encoder *encoder = NULL;
  2568. struct drm_crtc *crtc = NULL;
  2569. int i, rc = 0;
  2570. struct drm_display_mode *drm_mode = NULL;
  2571. struct drm_device *dev;
  2572. struct msm_drm_private *priv;
  2573. struct sde_kms *sde_kms;
  2574. struct drm_connector_list_iter conn_iter;
  2575. struct drm_connector *connector = NULL;
  2576. struct sde_connector *sde_conn = NULL;
  2577. struct sde_splash_display *splash_display;
  2578. if (!kms) {
  2579. SDE_ERROR("invalid kms\n");
  2580. return -EINVAL;
  2581. }
  2582. sde_kms = to_sde_kms(kms);
  2583. dev = sde_kms->dev;
  2584. if (!dev) {
  2585. SDE_ERROR("invalid device\n");
  2586. return -EINVAL;
  2587. }
  2588. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2589. if (rc) {
  2590. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2591. return -EINVAL;
  2592. }
  2593. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2594. && (!sde_kms->splash_data.num_splash_regions)) ||
  2595. !sde_kms->splash_data.num_splash_displays) {
  2596. DRM_INFO("cont_splash feature not enabled\n");
  2597. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2598. return rc;
  2599. }
  2600. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2601. sde_kms->splash_data.num_splash_displays,
  2602. sde_kms->dsi_display_count);
  2603. /* dsi */
  2604. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2605. display = sde_kms->dsi_displays[i];
  2606. dsi_display = (struct dsi_display *)display;
  2607. splash_display = &sde_kms->splash_data.splash_display[i];
  2608. if (!splash_display->cont_splash_enabled) {
  2609. SDE_DEBUG("display->name = %s splash not enabled\n",
  2610. dsi_display->name);
  2611. sde_kms_inform_cont_splash_res_disable(kms,
  2612. dsi_display);
  2613. continue;
  2614. }
  2615. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2616. if (dsi_display->bridge->base.encoder) {
  2617. encoder = dsi_display->bridge->base.encoder;
  2618. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2619. }
  2620. memset(&info, 0x0, sizeof(info));
  2621. rc = dsi_display_get_info(NULL, &info, display);
  2622. if (rc) {
  2623. SDE_ERROR("dsi get_info %d failed\n", i);
  2624. encoder = NULL;
  2625. continue;
  2626. }
  2627. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2628. ((info.is_connected) ? "true" : "false"),
  2629. info.display_type);
  2630. if (!encoder) {
  2631. SDE_ERROR("encoder not initialized\n");
  2632. return -EINVAL;
  2633. }
  2634. priv = sde_kms->dev->dev_private;
  2635. encoder->crtc = priv->crtcs[i];
  2636. crtc = encoder->crtc;
  2637. splash_display->encoder = encoder;
  2638. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2639. i, crtc->index, crtc->base.id, encoder->index,
  2640. encoder->base.id);
  2641. mutex_lock(&dev->mode_config.mutex);
  2642. drm_connector_list_iter_begin(dev, &conn_iter);
  2643. drm_for_each_connector_iter(connector, &conn_iter) {
  2644. /**
  2645. * SDE_KMS doesn't attach more than one encoder to
  2646. * a DSI connector. So it is safe to check only with
  2647. * the first encoder entry. Revisit this logic if we
  2648. * ever have to support continuous splash for
  2649. * external displays in MST configuration.
  2650. */
  2651. if (connector->encoder_ids[0] == encoder->base.id)
  2652. break;
  2653. }
  2654. drm_connector_list_iter_end(&conn_iter);
  2655. if (!connector) {
  2656. SDE_ERROR("connector not initialized\n");
  2657. mutex_unlock(&dev->mode_config.mutex);
  2658. return -EINVAL;
  2659. }
  2660. mutex_unlock(&dev->mode_config.mutex);
  2661. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2662. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  2663. if (!drm_mode) {
  2664. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  2665. sde_kms->splash_data.type);
  2666. return -EINVAL;
  2667. }
  2668. SDE_DEBUG(
  2669. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  2670. drm_mode->name, drm_mode->type,
  2671. drm_mode->flags, sde_kms->splash_data.type);
  2672. /* Update CRTC drm structure */
  2673. crtc->state->active = true;
  2674. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2675. if (rc) {
  2676. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2677. return rc;
  2678. }
  2679. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2680. drm_mode_copy(&crtc->mode, drm_mode);
  2681. /* Update encoder structure */
  2682. sde_encoder_update_caps_for_cont_splash(encoder,
  2683. splash_display, true);
  2684. sde_crtc_update_cont_splash_settings(crtc);
  2685. sde_conn = to_sde_connector(connector);
  2686. if (sde_conn && sde_conn->ops.cont_splash_config)
  2687. sde_conn->ops.cont_splash_config(sde_conn->display);
  2688. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2689. splash_display, crtc);
  2690. if (rc) {
  2691. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2692. return rc;
  2693. }
  2694. }
  2695. return rc;
  2696. }
  2697. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2698. {
  2699. struct sde_kms *sde_kms;
  2700. if (!kms) {
  2701. SDE_ERROR("invalid kms\n");
  2702. return false;
  2703. }
  2704. sde_kms = to_sde_kms(kms);
  2705. return sde_kms->splash_data.num_splash_displays;
  2706. }
  2707. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2708. const struct drm_display_mode *mode,
  2709. const struct msm_resource_caps_info *res, u32 *num_lm)
  2710. {
  2711. struct sde_kms *sde_kms;
  2712. s64 mode_clock_hz = 0;
  2713. s64 max_mdp_clock_hz = 0;
  2714. s64 max_lm_width = 0;
  2715. s64 hdisplay_fp = 0;
  2716. s64 htotal_fp = 0;
  2717. s64 vtotal_fp = 0;
  2718. s64 vrefresh_fp = 0;
  2719. s64 mdp_fudge_factor = 0;
  2720. s64 num_lm_fp = 0;
  2721. s64 lm_clk_fp = 0;
  2722. s64 lm_width_fp = 0;
  2723. int rc = 0;
  2724. if (!num_lm) {
  2725. SDE_ERROR("invalid num_lm pointer\n");
  2726. return -EINVAL;
  2727. }
  2728. /* default to 1 layer mixer */
  2729. *num_lm = 1;
  2730. if (!kms || !mode || !res) {
  2731. SDE_ERROR("invalid input args\n");
  2732. return -EINVAL;
  2733. }
  2734. sde_kms = to_sde_kms(kms);
  2735. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2736. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2737. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2738. htotal_fp = drm_int2fixp(mode->htotal);
  2739. vtotal_fp = drm_int2fixp(mode->vtotal);
  2740. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2741. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2742. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2743. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2744. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2745. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2746. if (mode_clock_hz > max_mdp_clock_hz ||
  2747. hdisplay_fp > max_lm_width) {
  2748. *num_lm = 0;
  2749. do {
  2750. *num_lm += 2;
  2751. num_lm_fp = drm_int2fixp(*num_lm);
  2752. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2753. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2754. if (*num_lm > 4) {
  2755. rc = -EINVAL;
  2756. goto error;
  2757. }
  2758. } while (lm_clk_fp > max_mdp_clock_hz ||
  2759. lm_width_fp > max_lm_width);
  2760. mode_clock_hz = lm_clk_fp;
  2761. }
  2762. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2763. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2764. *num_lm, drm_fixp2int(mode_clock_hz),
  2765. sde_kms->perf.max_core_clk_rate);
  2766. return 0;
  2767. error:
  2768. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2769. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2770. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2771. *num_lm, drm_fixp2int(mode_clock_hz),
  2772. sde_kms->perf.max_core_clk_rate);
  2773. return rc;
  2774. }
  2775. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2776. u32 hdisplay, u32 *num_dsc)
  2777. {
  2778. struct sde_kms *sde_kms;
  2779. uint32_t max_dsc_width;
  2780. if (!num_dsc) {
  2781. SDE_ERROR("invalid num_dsc pointer\n");
  2782. return -EINVAL;
  2783. }
  2784. *num_dsc = 0;
  2785. if (!kms || !hdisplay) {
  2786. SDE_ERROR("invalid input args\n");
  2787. return -EINVAL;
  2788. }
  2789. sde_kms = to_sde_kms(kms);
  2790. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2791. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2792. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2793. hdisplay, max_dsc_width,
  2794. *num_dsc);
  2795. return 0;
  2796. }
  2797. static void _sde_kms_null_commit(struct drm_device *dev,
  2798. struct drm_encoder *enc)
  2799. {
  2800. struct drm_modeset_acquire_ctx ctx;
  2801. struct drm_connector *conn = NULL;
  2802. struct drm_connector *tmp_conn = NULL;
  2803. struct drm_connector_list_iter conn_iter;
  2804. struct drm_atomic_state *state = NULL;
  2805. struct drm_crtc_state *crtc_state = NULL;
  2806. struct drm_connector_state *conn_state = NULL;
  2807. int retry_cnt = 0;
  2808. int ret = 0;
  2809. drm_modeset_acquire_init(&ctx, 0);
  2810. retry:
  2811. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2812. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2813. drm_modeset_backoff(&ctx);
  2814. retry_cnt++;
  2815. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2816. goto retry;
  2817. } else if (WARN_ON(ret)) {
  2818. goto end;
  2819. }
  2820. state = drm_atomic_state_alloc(dev);
  2821. if (!state) {
  2822. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2823. goto end;
  2824. }
  2825. state->acquire_ctx = &ctx;
  2826. drm_connector_list_iter_begin(dev, &conn_iter);
  2827. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2828. if (enc == tmp_conn->state->best_encoder) {
  2829. conn = tmp_conn;
  2830. break;
  2831. }
  2832. }
  2833. drm_connector_list_iter_end(&conn_iter);
  2834. if (!conn) {
  2835. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2836. goto end;
  2837. }
  2838. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2839. conn_state = drm_atomic_get_connector_state(state, conn);
  2840. if (IS_ERR(conn_state)) {
  2841. SDE_ERROR("error %d getting connector %d state\n",
  2842. ret, DRMID(conn));
  2843. goto end;
  2844. }
  2845. crtc_state->active = true;
  2846. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2847. if (ret)
  2848. SDE_ERROR("error %d setting the crtc\n", ret);
  2849. ret = drm_atomic_commit(state);
  2850. if (ret)
  2851. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2852. end:
  2853. if (state)
  2854. drm_atomic_state_put(state);
  2855. drm_modeset_drop_locks(&ctx);
  2856. drm_modeset_acquire_fini(&ctx);
  2857. }
  2858. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2859. const int32_t connector_id)
  2860. {
  2861. struct drm_connector_list_iter conn_iter;
  2862. struct drm_connector *conn;
  2863. struct drm_encoder *drm_enc;
  2864. drm_connector_list_iter_begin(dev, &conn_iter);
  2865. drm_for_each_connector_iter(conn, &conn_iter) {
  2866. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2867. connector_id != conn->base.id)
  2868. continue;
  2869. if (conn->state && conn->state->best_encoder)
  2870. drm_enc = conn->state->best_encoder;
  2871. else
  2872. drm_enc = conn->encoder;
  2873. if (drm_enc)
  2874. sde_encoder_early_wakeup(drm_enc);
  2875. }
  2876. drm_connector_list_iter_end(&conn_iter);
  2877. }
  2878. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2879. struct device *dev)
  2880. {
  2881. int i, ret, crtc_id = 0;
  2882. struct drm_device *ddev = dev_get_drvdata(dev);
  2883. struct drm_connector *conn;
  2884. struct drm_connector_list_iter conn_iter;
  2885. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2886. drm_connector_list_iter_begin(ddev, &conn_iter);
  2887. drm_for_each_connector_iter(conn, &conn_iter) {
  2888. uint64_t lp;
  2889. lp = sde_connector_get_lp(conn);
  2890. if (lp != SDE_MODE_DPMS_LP2)
  2891. continue;
  2892. if (sde_encoder_in_clone_mode(conn->encoder))
  2893. continue;
  2894. ret = sde_encoder_wait_for_event(conn->encoder,
  2895. MSM_ENC_TX_COMPLETE);
  2896. if (ret && ret != -EWOULDBLOCK) {
  2897. SDE_ERROR(
  2898. "[conn: %d] wait for commit done returned %d\n",
  2899. conn->base.id, ret);
  2900. } else if (!ret) {
  2901. crtc_id = drm_crtc_index(conn->state->crtc);
  2902. if (priv->event_thread[crtc_id].thread)
  2903. kthread_flush_worker(
  2904. &priv->event_thread[crtc_id].worker);
  2905. sde_encoder_idle_request(conn->encoder);
  2906. }
  2907. }
  2908. drm_connector_list_iter_end(&conn_iter);
  2909. for (i = 0; i < priv->num_crtcs; i++) {
  2910. if (priv->disp_thread[i].thread)
  2911. kthread_flush_worker(
  2912. &priv->disp_thread[i].worker);
  2913. if (priv->event_thread[i].thread)
  2914. kthread_flush_worker(
  2915. &priv->event_thread[i].worker);
  2916. }
  2917. kthread_flush_worker(&priv->pp_event_worker);
  2918. }
  2919. static int sde_kms_pm_suspend(struct device *dev)
  2920. {
  2921. struct drm_device *ddev;
  2922. struct drm_modeset_acquire_ctx ctx;
  2923. struct drm_connector *conn;
  2924. struct drm_encoder *enc;
  2925. struct drm_connector_list_iter conn_iter;
  2926. struct drm_atomic_state *state = NULL;
  2927. struct sde_kms *sde_kms;
  2928. int ret = 0, num_crtcs = 0;
  2929. if (!dev)
  2930. return -EINVAL;
  2931. ddev = dev_get_drvdata(dev);
  2932. if (!ddev || !ddev_to_msm_kms(ddev))
  2933. return -EINVAL;
  2934. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2935. SDE_EVT32(0);
  2936. /* disable hot-plug polling */
  2937. drm_kms_helper_poll_disable(ddev);
  2938. /* if a display stuck in CS trigger a null commit to complete handoff */
  2939. drm_for_each_encoder(enc, ddev) {
  2940. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2941. _sde_kms_null_commit(ddev, enc);
  2942. }
  2943. /* acquire modeset lock(s) */
  2944. drm_modeset_acquire_init(&ctx, 0);
  2945. retry:
  2946. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2947. if (ret)
  2948. goto unlock;
  2949. /* save current state for resume */
  2950. if (sde_kms->suspend_state)
  2951. drm_atomic_state_put(sde_kms->suspend_state);
  2952. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2953. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2954. ret = PTR_ERR(sde_kms->suspend_state);
  2955. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2956. sde_kms->suspend_state = NULL;
  2957. goto unlock;
  2958. }
  2959. /* create atomic state to disable all CRTCs */
  2960. state = drm_atomic_state_alloc(ddev);
  2961. if (!state) {
  2962. ret = -ENOMEM;
  2963. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2964. goto unlock;
  2965. }
  2966. state->acquire_ctx = &ctx;
  2967. drm_connector_list_iter_begin(ddev, &conn_iter);
  2968. drm_for_each_connector_iter(conn, &conn_iter) {
  2969. struct drm_crtc_state *crtc_state;
  2970. uint64_t lp;
  2971. if (!conn->state || !conn->state->crtc ||
  2972. conn->dpms != DRM_MODE_DPMS_ON ||
  2973. sde_encoder_in_clone_mode(conn->encoder))
  2974. continue;
  2975. lp = sde_connector_get_lp(conn);
  2976. if (lp == SDE_MODE_DPMS_LP1) {
  2977. /* transition LP1->LP2 on pm suspend */
  2978. ret = sde_connector_set_property_for_commit(conn, state,
  2979. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2980. if (ret) {
  2981. DRM_ERROR("failed to set lp2 for conn %d\n",
  2982. conn->base.id);
  2983. drm_connector_list_iter_end(&conn_iter);
  2984. goto unlock;
  2985. }
  2986. }
  2987. if (lp != SDE_MODE_DPMS_LP2) {
  2988. /* force CRTC to be inactive */
  2989. crtc_state = drm_atomic_get_crtc_state(state,
  2990. conn->state->crtc);
  2991. if (IS_ERR_OR_NULL(crtc_state)) {
  2992. DRM_ERROR("failed to get crtc %d state\n",
  2993. conn->state->crtc->base.id);
  2994. drm_connector_list_iter_end(&conn_iter);
  2995. goto unlock;
  2996. }
  2997. if (lp != SDE_MODE_DPMS_LP1)
  2998. crtc_state->active = false;
  2999. ++num_crtcs;
  3000. }
  3001. }
  3002. drm_connector_list_iter_end(&conn_iter);
  3003. /* check for nothing to do */
  3004. if (num_crtcs == 0) {
  3005. DRM_DEBUG("all crtcs are already in the off state\n");
  3006. sde_kms->suspend_block = true;
  3007. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3008. goto unlock;
  3009. }
  3010. /* commit the "disable all" state */
  3011. ret = drm_atomic_commit(state);
  3012. if (ret < 0) {
  3013. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3014. goto unlock;
  3015. }
  3016. sde_kms->suspend_block = true;
  3017. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3018. unlock:
  3019. if (state) {
  3020. drm_atomic_state_put(state);
  3021. state = NULL;
  3022. }
  3023. if (ret == -EDEADLK) {
  3024. drm_modeset_backoff(&ctx);
  3025. goto retry;
  3026. }
  3027. drm_modeset_drop_locks(&ctx);
  3028. drm_modeset_acquire_fini(&ctx);
  3029. /*
  3030. * pm runtime driver avoids multiple runtime_suspend API call by
  3031. * checking runtime_status. However, this call helps when there is a
  3032. * race condition between pm_suspend call and doze_suspend/power_off
  3033. * commit. It removes the extra vote from suspend and adds it back
  3034. * later to allow power collapse during pm_suspend call
  3035. */
  3036. pm_runtime_put_sync(dev);
  3037. pm_runtime_get_noresume(dev);
  3038. /* dump clock state before entering suspend */
  3039. if (sde_kms->pm_suspend_clk_dump)
  3040. _sde_kms_dump_clks_state(sde_kms);
  3041. return ret;
  3042. }
  3043. static int sde_kms_pm_resume(struct device *dev)
  3044. {
  3045. struct drm_device *ddev;
  3046. struct sde_kms *sde_kms;
  3047. struct drm_modeset_acquire_ctx ctx;
  3048. int ret, i;
  3049. if (!dev)
  3050. return -EINVAL;
  3051. ddev = dev_get_drvdata(dev);
  3052. if (!ddev || !ddev_to_msm_kms(ddev))
  3053. return -EINVAL;
  3054. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3055. SDE_EVT32(sde_kms->suspend_state != NULL);
  3056. drm_mode_config_reset(ddev);
  3057. drm_modeset_acquire_init(&ctx, 0);
  3058. retry:
  3059. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3060. if (ret == -EDEADLK) {
  3061. drm_modeset_backoff(&ctx);
  3062. goto retry;
  3063. } else if (WARN_ON(ret)) {
  3064. goto end;
  3065. }
  3066. sde_kms->suspend_block = false;
  3067. if (sde_kms->suspend_state) {
  3068. sde_kms->suspend_state->acquire_ctx = &ctx;
  3069. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3070. ret = drm_atomic_helper_commit_duplicated_state(
  3071. sde_kms->suspend_state, &ctx);
  3072. if (ret != -EDEADLK)
  3073. break;
  3074. drm_modeset_backoff(&ctx);
  3075. }
  3076. if (ret < 0)
  3077. DRM_ERROR("failed to restore state, %d\n", ret);
  3078. drm_atomic_state_put(sde_kms->suspend_state);
  3079. sde_kms->suspend_state = NULL;
  3080. }
  3081. end:
  3082. drm_modeset_drop_locks(&ctx);
  3083. drm_modeset_acquire_fini(&ctx);
  3084. /* enable hot-plug polling */
  3085. drm_kms_helper_poll_enable(ddev);
  3086. return 0;
  3087. }
  3088. static const struct msm_kms_funcs kms_funcs = {
  3089. .hw_init = sde_kms_hw_init,
  3090. .postinit = sde_kms_postinit,
  3091. .irq_preinstall = sde_irq_preinstall,
  3092. .irq_postinstall = sde_irq_postinstall,
  3093. .irq_uninstall = sde_irq_uninstall,
  3094. .irq = sde_irq,
  3095. .lastclose = sde_kms_lastclose,
  3096. .prepare_fence = sde_kms_prepare_fence,
  3097. .prepare_commit = sde_kms_prepare_commit,
  3098. .commit = sde_kms_commit,
  3099. .complete_commit = sde_kms_complete_commit,
  3100. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3101. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3102. .enable_vblank = sde_kms_enable_vblank,
  3103. .disable_vblank = sde_kms_disable_vblank,
  3104. .check_modified_format = sde_format_check_modified_format,
  3105. .atomic_check = sde_kms_atomic_check,
  3106. .get_format = sde_get_msm_format,
  3107. .round_pixclk = sde_kms_round_pixclk,
  3108. .display_early_wakeup = sde_kms_display_early_wakeup,
  3109. .pm_suspend = sde_kms_pm_suspend,
  3110. .pm_resume = sde_kms_pm_resume,
  3111. .destroy = sde_kms_destroy,
  3112. .debugfs_destroy = sde_kms_debugfs_destroy,
  3113. .cont_splash_config = sde_kms_cont_splash_config,
  3114. .register_events = _sde_kms_register_events,
  3115. .get_address_space = _sde_kms_get_address_space,
  3116. .get_address_space_device = _sde_kms_get_address_space_device,
  3117. .postopen = _sde_kms_post_open,
  3118. .check_for_splash = sde_kms_check_for_splash,
  3119. .get_mixer_count = sde_kms_get_mixer_count,
  3120. .get_dsc_count = sde_kms_get_dsc_count,
  3121. };
  3122. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3123. {
  3124. int i;
  3125. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3126. if (!sde_kms->aspace[i])
  3127. continue;
  3128. msm_gem_address_space_put(sde_kms->aspace[i]);
  3129. sde_kms->aspace[i] = NULL;
  3130. }
  3131. return 0;
  3132. }
  3133. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3134. {
  3135. struct msm_mmu *mmu;
  3136. int i, ret;
  3137. int early_map = 0;
  3138. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3139. return -EINVAL;
  3140. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3141. struct msm_gem_address_space *aspace;
  3142. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3143. if (IS_ERR(mmu)) {
  3144. ret = PTR_ERR(mmu);
  3145. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3146. i, ret);
  3147. continue;
  3148. }
  3149. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3150. mmu, "sde");
  3151. if (IS_ERR(aspace)) {
  3152. ret = PTR_ERR(aspace);
  3153. mmu->funcs->destroy(mmu);
  3154. goto fail;
  3155. }
  3156. sde_kms->aspace[i] = aspace;
  3157. aspace->domain_attached = true;
  3158. /* Mapping splash memory block */
  3159. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3160. sde_kms->splash_data.num_splash_regions) {
  3161. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3162. if (ret) {
  3163. SDE_ERROR("failed to map ret:%d\n", ret);
  3164. goto fail;
  3165. }
  3166. }
  3167. /*
  3168. * disable early-map which would have been enabled during
  3169. * bootup by smmu through the device-tree hint for cont-spash
  3170. */
  3171. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3172. &early_map);
  3173. if (ret) {
  3174. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3175. ret, early_map);
  3176. goto early_map_fail;
  3177. }
  3178. }
  3179. sde_kms->base.aspace = sde_kms->aspace[0];
  3180. return 0;
  3181. early_map_fail:
  3182. _sde_kms_unmap_all_splash_regions(sde_kms);
  3183. fail:
  3184. _sde_kms_mmu_destroy(sde_kms);
  3185. return ret;
  3186. }
  3187. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3188. {
  3189. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3190. return;
  3191. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3192. }
  3193. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3194. {
  3195. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3196. return;
  3197. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3198. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3199. sde_kms->catalog);
  3200. }
  3201. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3202. {
  3203. struct sde_vbif_set_qos_params qos_params;
  3204. struct sde_mdss_cfg *catalog;
  3205. if (!sde_kms->catalog)
  3206. return;
  3207. catalog = sde_kms->catalog;
  3208. memset(&qos_params, 0, sizeof(qos_params));
  3209. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3210. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3211. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3212. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3213. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3214. }
  3215. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3216. {
  3217. struct sde_hw_uidle *uidle;
  3218. if (!sde_kms) {
  3219. SDE_ERROR("invalid kms\n");
  3220. return -EINVAL;
  3221. }
  3222. uidle = sde_kms->hw_uidle;
  3223. if (uidle && uidle->ops.active_override_enable)
  3224. uidle->ops.active_override_enable(uidle, enable);
  3225. return 0;
  3226. }
  3227. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3228. {
  3229. struct device *cpu_dev;
  3230. int cpu = 0;
  3231. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3232. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3233. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3234. return;
  3235. }
  3236. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3237. cpu_dev = get_cpu_device(cpu);
  3238. if (!cpu_dev) {
  3239. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3240. cpu);
  3241. continue;
  3242. }
  3243. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3244. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3245. cpu_irq_latency);
  3246. else
  3247. dev_pm_qos_add_request(cpu_dev,
  3248. &sde_kms->pm_qos_irq_req[cpu],
  3249. DEV_PM_QOS_RESUME_LATENCY,
  3250. cpu_irq_latency);
  3251. }
  3252. }
  3253. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3254. {
  3255. struct device *cpu_dev;
  3256. int cpu = 0;
  3257. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3258. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3259. return;
  3260. }
  3261. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3262. cpu_dev = get_cpu_device(cpu);
  3263. if (!cpu_dev) {
  3264. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3265. cpu);
  3266. continue;
  3267. }
  3268. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3269. dev_pm_qos_remove_request(
  3270. &sde_kms->pm_qos_irq_req[cpu]);
  3271. }
  3272. }
  3273. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3274. {
  3275. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3276. mutex_lock(&priv->phandle.phandle_lock);
  3277. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3278. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3279. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3280. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3281. mutex_unlock(&priv->phandle.phandle_lock);
  3282. }
  3283. static void sde_kms_irq_affinity_notify(
  3284. struct irq_affinity_notify *affinity_notify,
  3285. const cpumask_t *mask)
  3286. {
  3287. struct msm_drm_private *priv;
  3288. struct sde_kms *sde_kms = container_of(affinity_notify,
  3289. struct sde_kms, affinity_notify);
  3290. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3291. return;
  3292. priv = sde_kms->dev->dev_private;
  3293. mutex_lock(&priv->phandle.phandle_lock);
  3294. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3295. // save irq cpu mask
  3296. sde_kms->irq_cpu_mask = *mask;
  3297. // request vote with updated irq cpu mask
  3298. if (atomic_read(&sde_kms->irq_vote_count))
  3299. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3300. mutex_unlock(&priv->phandle.phandle_lock);
  3301. }
  3302. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3303. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3304. {
  3305. struct sde_kms *sde_kms = usr;
  3306. struct msm_kms *msm_kms;
  3307. msm_kms = &sde_kms->base;
  3308. if (!sde_kms)
  3309. return;
  3310. SDE_DEBUG("event_type:%d\n", event_type);
  3311. SDE_EVT32_VERBOSE(event_type);
  3312. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3313. sde_irq_update(msm_kms, true);
  3314. sde_kms->first_kickoff = true;
  3315. /**
  3316. * Rotator sid needs to be programmed since uefi doesn't
  3317. * configure it during continuous splash
  3318. */
  3319. sde_kms_init_rot_sid_hw(sde_kms);
  3320. if (sde_kms->splash_data.num_splash_displays ||
  3321. sde_in_trusted_vm(sde_kms))
  3322. return;
  3323. sde_vbif_init_memtypes(sde_kms);
  3324. sde_kms_init_shared_hw(sde_kms);
  3325. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3326. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3327. sde_irq_update(msm_kms, false);
  3328. sde_kms->first_kickoff = false;
  3329. if (sde_in_trusted_vm(sde_kms))
  3330. return;
  3331. _sde_kms_active_override(sde_kms, true);
  3332. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3333. sde_vbif_axi_halt_request(sde_kms);
  3334. }
  3335. }
  3336. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3337. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3338. {
  3339. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3340. int rc = -EINVAL;
  3341. SDE_DEBUG("\n");
  3342. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3343. if (rc > 0)
  3344. rc = 0;
  3345. SDE_EVT32(rc, genpd->device_count);
  3346. return rc;
  3347. }
  3348. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3349. {
  3350. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3351. SDE_DEBUG("\n");
  3352. pm_runtime_put_sync(sde_kms->dev->dev);
  3353. SDE_EVT32(genpd->device_count);
  3354. return 0;
  3355. }
  3356. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3357. struct sde_splash_data *data)
  3358. {
  3359. int i = 0;
  3360. int ret = 0;
  3361. struct device_node *parent, *node, *node1;
  3362. struct resource r, r1;
  3363. const char *node_name = "splash_region";
  3364. struct sde_splash_mem *mem;
  3365. bool share_splash_mem = false;
  3366. int num_displays, num_regions;
  3367. struct sde_splash_display *splash_display;
  3368. if (!data)
  3369. return -EINVAL;
  3370. memset(data, 0, sizeof(*data));
  3371. parent = of_find_node_by_path("/reserved-memory");
  3372. if (!parent) {
  3373. SDE_ERROR("failed to find reserved-memory node\n");
  3374. return -EINVAL;
  3375. }
  3376. node = of_find_node_by_name(parent, node_name);
  3377. if (!node) {
  3378. SDE_DEBUG("failed to find node %s\n", node_name);
  3379. return -EINVAL;
  3380. }
  3381. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3382. if (!node1)
  3383. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3384. /**
  3385. * Support sharing a single splash memory for all the built in displays
  3386. * and also independent splash region per displays. Incase of
  3387. * independent splash region for each connected display, dtsi node of
  3388. * cont_splash_region should be collection of all memory regions
  3389. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3390. */
  3391. num_displays = dsi_display_get_num_of_displays();
  3392. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3393. data->num_splash_displays = num_displays;
  3394. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3395. if (num_displays > num_regions) {
  3396. share_splash_mem = true;
  3397. pr_info(":%d displays share same splash buf\n", num_displays);
  3398. }
  3399. for (i = 0; i < num_displays; i++) {
  3400. splash_display = &data->splash_display[i];
  3401. if (!i || !share_splash_mem) {
  3402. if (of_address_to_resource(node, i, &r)) {
  3403. SDE_ERROR("invalid data for:%s\n", node_name);
  3404. return -EINVAL;
  3405. }
  3406. mem = &data->splash_mem[i];
  3407. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3408. SDE_DEBUG("failed to find ramdump memory\n");
  3409. mem->ramdump_base = 0;
  3410. mem->ramdump_size = 0;
  3411. } else {
  3412. mem->ramdump_base = (unsigned long)r1.start;
  3413. mem->ramdump_size = (r1.end - r1.start) + 1;
  3414. }
  3415. mem->splash_buf_base = (unsigned long)r.start;
  3416. mem->splash_buf_size = (r.end - r.start) + 1;
  3417. mem->ref_cnt = 0;
  3418. splash_display->splash = mem;
  3419. data->num_splash_regions++;
  3420. } else {
  3421. data->splash_display[i].splash = &data->splash_mem[0];
  3422. }
  3423. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3424. splash_display->splash->splash_buf_base,
  3425. splash_display->splash->splash_buf_size);
  3426. }
  3427. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3428. return ret;
  3429. }
  3430. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3431. struct platform_device *platformdev)
  3432. {
  3433. int rc = -EINVAL;
  3434. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3435. if (IS_ERR(sde_kms->mmio)) {
  3436. rc = PTR_ERR(sde_kms->mmio);
  3437. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3438. sde_kms->mmio = NULL;
  3439. goto error;
  3440. }
  3441. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3442. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3443. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3444. sde_kms->mmio_len);
  3445. if (rc)
  3446. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3447. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3448. "vbif_phys");
  3449. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3450. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3451. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3452. sde_kms->vbif[VBIF_RT] = NULL;
  3453. goto error;
  3454. }
  3455. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3456. "vbif_phys");
  3457. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3458. sde_kms->vbif_len[VBIF_RT]);
  3459. if (rc)
  3460. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3461. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3462. "vbif_nrt_phys");
  3463. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3464. sde_kms->vbif[VBIF_NRT] = NULL;
  3465. SDE_DEBUG("VBIF NRT is not defined");
  3466. } else {
  3467. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3468. "vbif_nrt_phys");
  3469. rc = sde_dbg_reg_register_base("vbif_nrt",
  3470. sde_kms->vbif[VBIF_NRT],
  3471. sde_kms->vbif_len[VBIF_NRT]);
  3472. if (rc)
  3473. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3474. rc);
  3475. }
  3476. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3477. "regdma_phys");
  3478. if (IS_ERR(sde_kms->reg_dma)) {
  3479. sde_kms->reg_dma = NULL;
  3480. SDE_DEBUG("REG_DMA is not defined");
  3481. } else {
  3482. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3483. "regdma_phys");
  3484. rc = sde_dbg_reg_register_base("reg_dma",
  3485. sde_kms->reg_dma,
  3486. sde_kms->reg_dma_len);
  3487. if (rc)
  3488. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3489. rc);
  3490. }
  3491. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3492. "sid_phys");
  3493. if (IS_ERR(sde_kms->sid)) {
  3494. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3495. sde_kms->sid = NULL;
  3496. } else {
  3497. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3498. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3499. sde_kms->sid_len);
  3500. if (rc)
  3501. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3502. }
  3503. error:
  3504. return rc;
  3505. }
  3506. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3507. struct sde_kms *sde_kms)
  3508. {
  3509. int rc = 0;
  3510. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3511. sde_kms->genpd.name = dev->unique;
  3512. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3513. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3514. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3515. if (rc < 0) {
  3516. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3517. sde_kms->genpd.name, rc);
  3518. return rc;
  3519. }
  3520. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3521. &sde_kms->genpd);
  3522. if (rc < 0) {
  3523. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3524. sde_kms->genpd.name, rc);
  3525. pm_genpd_remove(&sde_kms->genpd);
  3526. return rc;
  3527. }
  3528. sde_kms->genpd_init = true;
  3529. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3530. }
  3531. return rc;
  3532. }
  3533. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3534. struct drm_device *dev,
  3535. struct msm_drm_private *priv)
  3536. {
  3537. struct sde_rm *rm = NULL;
  3538. int i, rc = -EINVAL;
  3539. sde_kms->catalog = sde_hw_catalog_init(dev);
  3540. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3541. rc = PTR_ERR(sde_kms->catalog);
  3542. if (!sde_kms->catalog)
  3543. rc = -EINVAL;
  3544. SDE_ERROR("catalog init failed: %d\n", rc);
  3545. sde_kms->catalog = NULL;
  3546. goto power_error;
  3547. }
  3548. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3549. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3550. /* initialize power domain if defined */
  3551. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3552. if (rc) {
  3553. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3554. goto genpd_err;
  3555. }
  3556. rc = _sde_kms_mmu_init(sde_kms);
  3557. if (rc) {
  3558. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3559. goto power_error;
  3560. }
  3561. /* Initialize reg dma block which is a singleton */
  3562. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3563. sde_kms->dev);
  3564. if (rc) {
  3565. SDE_ERROR("failed: reg dma init failed\n");
  3566. goto power_error;
  3567. }
  3568. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3569. rm = &sde_kms->rm;
  3570. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3571. sde_kms->dev);
  3572. if (rc) {
  3573. SDE_ERROR("rm init failed: %d\n", rc);
  3574. goto power_error;
  3575. }
  3576. sde_kms->rm_init = true;
  3577. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3578. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3579. rc = PTR_ERR(sde_kms->hw_intr);
  3580. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3581. sde_kms->hw_intr = NULL;
  3582. goto hw_intr_init_err;
  3583. }
  3584. /*
  3585. * Attempt continuous splash handoff only if reserved
  3586. * splash memory is found & release resources on any error
  3587. * in finding display hw config in splash
  3588. */
  3589. if (sde_kms->splash_data.num_splash_regions) {
  3590. struct sde_splash_display *display;
  3591. int ret, display_count =
  3592. sde_kms->splash_data.num_splash_displays;
  3593. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3594. &sde_kms->splash_data, sde_kms->catalog);
  3595. for (i = 0; i < display_count; i++) {
  3596. display = &sde_kms->splash_data.splash_display[i];
  3597. /*
  3598. * free splash region on resource init failure and
  3599. * cont-splash disabled case
  3600. */
  3601. if (!display->cont_splash_enabled || ret)
  3602. _sde_kms_free_splash_display_data(
  3603. sde_kms, display);
  3604. }
  3605. }
  3606. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3607. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3608. rc = PTR_ERR(sde_kms->hw_mdp);
  3609. if (!sde_kms->hw_mdp)
  3610. rc = -EINVAL;
  3611. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3612. sde_kms->hw_mdp = NULL;
  3613. goto power_error;
  3614. }
  3615. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3616. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3617. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3618. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3619. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3620. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3621. if (!sde_kms->hw_vbif[vbif_idx])
  3622. rc = -EINVAL;
  3623. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3624. sde_kms->hw_vbif[vbif_idx] = NULL;
  3625. goto power_error;
  3626. }
  3627. }
  3628. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3629. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3630. sde_kms->mmio_len, sde_kms->catalog);
  3631. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3632. rc = PTR_ERR(sde_kms->hw_uidle);
  3633. if (!sde_kms->hw_uidle)
  3634. rc = -EINVAL;
  3635. /* uidle is optional, so do not make it a fatal error */
  3636. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3637. sde_kms->hw_uidle = NULL;
  3638. rc = 0;
  3639. }
  3640. } else {
  3641. sde_kms->hw_uidle = NULL;
  3642. }
  3643. if (sde_kms->sid) {
  3644. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3645. sde_kms->sid_len, sde_kms->catalog);
  3646. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3647. rc = PTR_ERR(sde_kms->hw_sid);
  3648. SDE_ERROR("failed to init sid %ld\n", rc);
  3649. sde_kms->hw_sid = NULL;
  3650. goto power_error;
  3651. }
  3652. }
  3653. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3654. &priv->phandle, "core_clk");
  3655. if (rc) {
  3656. SDE_ERROR("failed to init perf %d\n", rc);
  3657. goto perf_err;
  3658. }
  3659. /*
  3660. * _sde_kms_drm_obj_init should create the DRM related objects
  3661. * i.e. CRTCs, planes, encoders, connectors and so forth
  3662. */
  3663. rc = _sde_kms_drm_obj_init(sde_kms);
  3664. if (rc) {
  3665. SDE_ERROR("modeset init failed: %d\n", rc);
  3666. goto drm_obj_init_err;
  3667. }
  3668. return 0;
  3669. genpd_err:
  3670. drm_obj_init_err:
  3671. sde_core_perf_destroy(&sde_kms->perf);
  3672. hw_intr_init_err:
  3673. perf_err:
  3674. power_error:
  3675. return rc;
  3676. }
  3677. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3678. {
  3679. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3680. int rc = 0;
  3681. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3682. if (rc) {
  3683. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3684. return rc;
  3685. }
  3686. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3687. if (rc) {
  3688. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3689. return rc;
  3690. }
  3691. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3692. if (rc) {
  3693. SDE_ERROR("failed to get io irq for KMS");
  3694. return rc;
  3695. }
  3696. return rc;
  3697. }
  3698. static int sde_kms_hw_init(struct msm_kms *kms)
  3699. {
  3700. struct sde_kms *sde_kms;
  3701. struct drm_device *dev;
  3702. struct msm_drm_private *priv;
  3703. struct platform_device *platformdev;
  3704. int i, irq_num, rc = -EINVAL;
  3705. if (!kms) {
  3706. SDE_ERROR("invalid kms\n");
  3707. goto end;
  3708. }
  3709. sde_kms = to_sde_kms(kms);
  3710. dev = sde_kms->dev;
  3711. if (!dev || !dev->dev) {
  3712. SDE_ERROR("invalid device\n");
  3713. goto end;
  3714. }
  3715. platformdev = to_platform_device(dev->dev);
  3716. priv = dev->dev_private;
  3717. if (!priv) {
  3718. SDE_ERROR("invalid private data\n");
  3719. goto end;
  3720. }
  3721. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3722. if (rc)
  3723. goto error;
  3724. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3725. if (rc)
  3726. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3727. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3728. if (rc)
  3729. goto error;
  3730. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3731. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3732. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3733. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3734. mutex_init(&sde_kms->secure_transition_lock);
  3735. atomic_set(&sde_kms->detach_sec_cb, 0);
  3736. atomic_set(&sde_kms->detach_all_cb, 0);
  3737. atomic_set(&sde_kms->irq_vote_count, 0);
  3738. /*
  3739. * Support format modifiers for compression etc.
  3740. */
  3741. dev->mode_config.allow_fb_modifiers = true;
  3742. /*
  3743. * Handle (re)initializations during power enable
  3744. */
  3745. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3746. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3747. SDE_POWER_EVENT_POST_ENABLE |
  3748. SDE_POWER_EVENT_PRE_DISABLE,
  3749. sde_kms_handle_power_event, sde_kms, "kms");
  3750. if (sde_kms->splash_data.num_splash_displays) {
  3751. SDE_DEBUG("Skipping MDP Resources disable\n");
  3752. } else {
  3753. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3754. sde_power_data_bus_set_quota(&priv->phandle, i,
  3755. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3756. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3757. pm_runtime_put_sync(sde_kms->dev->dev);
  3758. }
  3759. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3760. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3761. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3762. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3763. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3764. if (sde_in_trusted_vm(sde_kms))
  3765. rc = sde_vm_trusted_init(sde_kms);
  3766. else
  3767. rc = sde_vm_primary_init(sde_kms);
  3768. if (rc) {
  3769. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3770. goto error;
  3771. }
  3772. return 0;
  3773. error:
  3774. _sde_kms_hw_destroy(sde_kms, platformdev);
  3775. end:
  3776. return rc;
  3777. }
  3778. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3779. {
  3780. struct msm_drm_private *priv;
  3781. struct sde_kms *sde_kms;
  3782. if (!dev || !dev->dev_private) {
  3783. SDE_ERROR("drm device node invalid\n");
  3784. return ERR_PTR(-EINVAL);
  3785. }
  3786. priv = dev->dev_private;
  3787. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3788. if (!sde_kms) {
  3789. SDE_ERROR("failed to allocate sde kms\n");
  3790. return ERR_PTR(-ENOMEM);
  3791. }
  3792. msm_kms_init(&sde_kms->base, &kms_funcs);
  3793. sde_kms->dev = dev;
  3794. return &sde_kms->base;
  3795. }
  3796. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3797. {
  3798. struct dsi_display *display;
  3799. struct sde_splash_display *handoff_display;
  3800. int i;
  3801. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3802. handoff_display = &sde_kms->splash_data.splash_display[i];
  3803. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3804. if (handoff_display->cont_splash_enabled)
  3805. _sde_kms_free_splash_display_data(sde_kms,
  3806. handoff_display);
  3807. dsi_display_set_active_state(display, false);
  3808. }
  3809. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3810. }
  3811. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  3812. struct drm_atomic_state *state)
  3813. {
  3814. struct drm_device *dev;
  3815. struct msm_drm_private *priv;
  3816. struct sde_splash_display *handoff_display;
  3817. struct dsi_display *display;
  3818. int ret, i;
  3819. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3820. SDE_ERROR("invalid params\n");
  3821. return -EINVAL;
  3822. }
  3823. dev = sde_kms->dev;
  3824. priv = dev->dev_private;
  3825. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3826. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3827. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3828. &sde_kms->splash_data, sde_kms->catalog);
  3829. if (ret) {
  3830. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  3831. return -EINVAL;
  3832. }
  3833. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3834. handoff_display = &sde_kms->splash_data.splash_display[i];
  3835. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3836. if (!handoff_display->cont_splash_enabled || ret)
  3837. _sde_kms_free_splash_display_data(sde_kms,
  3838. handoff_display);
  3839. else
  3840. dsi_display_set_active_state(display, true);
  3841. }
  3842. if (sde_kms->splash_data.num_splash_displays != 1) {
  3843. SDE_ERROR("no. of displays not supported:%d\n",
  3844. sde_kms->splash_data.num_splash_displays);
  3845. goto error;
  3846. }
  3847. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  3848. if (ret) {
  3849. SDE_ERROR("error in setting handoff configs\n");
  3850. goto error;
  3851. }
  3852. /**
  3853. * fill-in vote for the continuous splash hanodff path, which will be
  3854. * removed on the successful first commit.
  3855. */
  3856. pm_runtime_get_sync(sde_kms->dev->dev);
  3857. return 0;
  3858. error:
  3859. return ret;
  3860. }
  3861. static int _sde_kms_register_events(struct msm_kms *kms,
  3862. struct drm_mode_object *obj, u32 event, bool en)
  3863. {
  3864. int ret = 0;
  3865. struct drm_crtc *crtc = NULL;
  3866. struct drm_connector *conn = NULL;
  3867. struct sde_kms *sde_kms = NULL;
  3868. struct sde_vm_ops *vm_ops;
  3869. if (!kms || !obj) {
  3870. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3871. return -EINVAL;
  3872. }
  3873. sde_kms = to_sde_kms(kms);
  3874. /* check vm ownership, if event registration requires HW access */
  3875. switch (obj->type) {
  3876. case DRM_MODE_OBJECT_CRTC:
  3877. vm_ops = sde_vm_get_ops(sde_kms);
  3878. sde_vm_lock(sde_kms);
  3879. if (vm_ops && vm_ops->vm_owns_hw
  3880. && !vm_ops->vm_owns_hw(sde_kms)) {
  3881. sde_vm_unlock(sde_kms);
  3882. SDE_DEBUG("HW is owned by other VM\n");
  3883. return -EACCES;
  3884. }
  3885. crtc = obj_to_crtc(obj);
  3886. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3887. sde_vm_unlock(sde_kms);
  3888. break;
  3889. case DRM_MODE_OBJECT_CONNECTOR:
  3890. conn = obj_to_connector(obj);
  3891. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3892. en);
  3893. break;
  3894. }
  3895. return ret;
  3896. }
  3897. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3898. {
  3899. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3900. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3901. }