power.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/of.h>
  9. #include <linux/pinctrl/consumer.h>
  10. #include <linux/regulator/consumer.h>
  11. #include <soc/qcom/cmd-db.h>
  12. #include "main.h"
  13. #include "qmi.h"
  14. #include "debug.h"
  15. #include "power.h"
  16. #if IS_ENABLED(CONFIG_MSM_QMP)
  17. #include <linux/soc/qcom/qcom_aoss.h>
  18. #endif
  19. static struct icnss_vreg_cfg icnss_wcn6750_vreg_list[] = {
  20. {"vdd-cx-mx", 824000, 952000, 0, 0, 0, false, true},
  21. {"vdd-1.8-xo", 1872000, 1872000, 0, 0, 0, false, true},
  22. {"vdd-1.3-rfa", 1256000, 1352000, 0, 0, 0, false, true},
  23. };
  24. static struct icnss_vreg_cfg icnss_adrestea_vreg_list[] = {
  25. {"vdd-cx-mx", 752000, 752000, 0, 0, 0, false, true},
  26. {"vdd-1.8-xo", 1800000, 1800000, 0, 0, 0, false, true},
  27. {"vdd-1.3-rfa", 1304000, 1304000, 0, 0, 0, false, true},
  28. {"vdd-3.3-ch1", 3312000, 3312000, 0, 0, 0, false, true},
  29. {"vdd-3.3-ch0", 3312000, 3312000, 0, 0, 0, false, true},
  30. };
  31. static struct icnss_battery_level icnss_battery_level[] = {
  32. {70, 3300000},
  33. {60, 3200000},
  34. {50, 3100000},
  35. {25, 3000000},
  36. {0, 2850000},
  37. };
  38. static struct icnss_vreg_cfg icnss_wcn6450_vreg_list[] = {
  39. {"vdd-cx-mx", 824000, 952000, 0, 0, 0, false, true},
  40. {"vdd-1.8-xo", 1872000, 1872000, 0, 0, 0, false, true},
  41. {"vdd-1.3-rfa", 1256000, 1352000, 0, 0, 0, false, true},
  42. {"vdd-aon", 1256000, 1352000, 0, 0, 0, false, true},
  43. };
  44. static struct icnss_clk_cfg icnss_clk_list[] = {
  45. {"rf_clk", 0, 0},
  46. };
  47. static struct icnss_clk_cfg icnss_adrestea_clk_list[] = {
  48. {"cxo_ref_clk_pin", 0, 0},
  49. };
  50. #define ICNSS_VREG_LIST_SIZE ARRAY_SIZE(icnss_wcn6750_vreg_list)
  51. #define ICNSS_VREG_ADRESTEA_LIST_SIZE ARRAY_SIZE(icnss_adrestea_vreg_list)
  52. #define ICNSS_VREG_EVROS_LIST_SIZE ARRAY_SIZE(icnss_wcn6450_vreg_list)
  53. #define ICNSS_CLK_LIST_SIZE ARRAY_SIZE(icnss_clk_list)
  54. #define ICNSS_CLK_ADRESTEA_LIST_SIZE ARRAY_SIZE(icnss_adrestea_clk_list)
  55. #define ICNSS_CHAIN1_REGULATOR "vdd-3.3-ch1"
  56. #define MAX_PROP_SIZE 32
  57. #define BT_CXMX_VOLTAGE_MV 950
  58. #define ICNSS_MBOX_MSG_MAX_LEN 64
  59. #define ICNSS_MBOX_TIMEOUT_MS 1000
  60. #define ICNSS_BATTERY_LEVEL_COUNT ARRAY_SIZE(icnss_battery_level)
  61. #define ICNSS_MAX_BATTERY_LEVEL 100
  62. /**
  63. * enum icnss_vreg_param: Voltage regulator TCS param
  64. * @ICNSS_VREG_VOLTAGE: Provides voltage level to be configured in TCS
  65. * @ICNSS_VREG_MODE: Regulator mode
  66. * @ICNSS_VREG_ENABLE: Set Voltage regulator enable config in TCS
  67. */
  68. enum icnss_vreg_param {
  69. ICNSS_VREG_VOLTAGE,
  70. ICNSS_VREG_MODE,
  71. ICNSS_VREG_ENABLE,
  72. };
  73. /**
  74. * enum icnss_tcs_seq: TCS sequence ID for trigger
  75. * ICNSS_TCS_UP_SEQ: TCS Sequence based on up trigger / Wake TCS
  76. * ICNSS_TCS_DOWN_SEQ: TCS Sequence based on down trigger / Sleep TCS
  77. * ICNSS_TCS_ALL_SEQ: Update for both up and down triggers
  78. */
  79. enum icnss_tcs_seq {
  80. ICNSS_TCS_UP_SEQ,
  81. ICNSS_TCS_DOWN_SEQ,
  82. ICNSS_TCS_ALL_SEQ,
  83. };
  84. static int icnss_get_vreg_single(struct icnss_priv *priv,
  85. struct icnss_vreg_info *vreg)
  86. {
  87. int ret = 0;
  88. struct device *dev = NULL;
  89. struct regulator *reg = NULL;
  90. const __be32 *prop = NULL;
  91. char prop_name[MAX_PROP_SIZE] = {0};
  92. int len = 0;
  93. int i;
  94. dev = &priv->pdev->dev;
  95. reg = devm_regulator_get_optional(dev, vreg->cfg.name);
  96. if (IS_ERR(reg)) {
  97. ret = PTR_ERR(reg);
  98. if (ret == -ENODEV) {
  99. return ret;
  100. } else if (ret == -EPROBE_DEFER) {
  101. icnss_pr_info("EPROBE_DEFER for regulator: %s\n",
  102. vreg->cfg.name);
  103. goto out;
  104. } else if (priv->device_id == ADRASTEA_DEVICE_ID) {
  105. if (vreg->cfg.required) {
  106. icnss_pr_err("Regulator %s doesn't exist: %d\n",
  107. vreg->cfg.name, ret);
  108. goto out;
  109. } else {
  110. icnss_pr_dbg("Optional regulator %s doesn't exist: %d\n",
  111. vreg->cfg.name, ret);
  112. goto done;
  113. }
  114. } else {
  115. icnss_pr_err("Failed to get regulator %s, err = %d\n",
  116. vreg->cfg.name, ret);
  117. goto out;
  118. }
  119. }
  120. vreg->reg = reg;
  121. snprintf(prop_name, MAX_PROP_SIZE, "qcom,%s-config",
  122. vreg->cfg.name);
  123. prop = of_get_property(dev->of_node, prop_name, &len);
  124. icnss_pr_dbg("Got regulator config, prop: %s, len: %d\n",
  125. prop_name, len);
  126. if (!prop || len < (2 * sizeof(__be32))) {
  127. icnss_pr_dbg("Property %s %s, use default\n", prop_name,
  128. prop ? "invalid format" : "doesn't exist");
  129. goto done;
  130. }
  131. for (i = 0; (i * sizeof(__be32)) < len; i++) {
  132. switch (i) {
  133. case 0:
  134. vreg->cfg.min_uv = be32_to_cpup(&prop[0]);
  135. break;
  136. case 1:
  137. vreg->cfg.max_uv = be32_to_cpup(&prop[1]);
  138. break;
  139. case 2:
  140. vreg->cfg.load_ua = be32_to_cpup(&prop[2]);
  141. break;
  142. case 3:
  143. vreg->cfg.delay_us = be32_to_cpup(&prop[3]);
  144. break;
  145. case 4:
  146. if (priv->device_id == WCN6750_DEVICE_ID)
  147. vreg->cfg.need_unvote = be32_to_cpup(&prop[4]);
  148. else
  149. vreg->cfg.need_unvote = 0;
  150. break;
  151. default:
  152. icnss_pr_dbg("Property %s, ignoring value at %d\n",
  153. prop_name, i);
  154. break;
  155. }
  156. }
  157. done:
  158. icnss_pr_dbg("Got regulator: %s, min_uv: %u, max_uv: %u, load_ua: %u, delay_us: %u, need_unvote: %u\n",
  159. vreg->cfg.name, vreg->cfg.min_uv,
  160. vreg->cfg.max_uv, vreg->cfg.load_ua,
  161. vreg->cfg.delay_us, vreg->cfg.need_unvote);
  162. return 0;
  163. out:
  164. return ret;
  165. }
  166. static int icnss_vreg_on_single(struct icnss_vreg_info *vreg)
  167. {
  168. int ret = 0;
  169. if (vreg->enabled) {
  170. icnss_pr_dbg("Regulator %s is already enabled\n",
  171. vreg->cfg.name);
  172. return 0;
  173. }
  174. icnss_pr_dbg("Regulator %s is being enabled\n", vreg->cfg.name);
  175. if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
  176. ret = regulator_set_voltage(vreg->reg,
  177. vreg->cfg.min_uv,
  178. vreg->cfg.max_uv);
  179. if (ret) {
  180. icnss_pr_err("Failed to set voltage for regulator %s, min_uv: %u, max_uv: %u, err = %d\n",
  181. vreg->cfg.name, vreg->cfg.min_uv,
  182. vreg->cfg.max_uv, ret);
  183. goto out;
  184. }
  185. }
  186. if (vreg->cfg.load_ua) {
  187. ret = regulator_set_load(vreg->reg,
  188. vreg->cfg.load_ua);
  189. if (ret < 0) {
  190. icnss_pr_err("Failed to set load for regulator %s, load: %u, err = %d\n",
  191. vreg->cfg.name, vreg->cfg.load_ua,
  192. ret);
  193. goto out;
  194. }
  195. }
  196. if (vreg->cfg.delay_us)
  197. udelay(vreg->cfg.delay_us);
  198. ret = regulator_enable(vreg->reg);
  199. if (ret) {
  200. icnss_pr_err("Failed to enable regulator %s, err = %d\n",
  201. vreg->cfg.name, ret);
  202. goto out;
  203. }
  204. vreg->enabled = true;
  205. out:
  206. return ret;
  207. }
  208. static int icnss_vreg_unvote_single(struct icnss_vreg_info *vreg)
  209. {
  210. int ret = 0;
  211. if (!vreg->enabled) {
  212. icnss_pr_dbg("Regulator %s is already disabled\n",
  213. vreg->cfg.name);
  214. return 0;
  215. }
  216. icnss_pr_dbg("Removing vote for Regulator %s\n", vreg->cfg.name);
  217. if (vreg->cfg.load_ua) {
  218. ret = regulator_set_load(vreg->reg, 0);
  219. if (ret < 0)
  220. icnss_pr_err("Failed to set load for regulator %s, err = %d\n",
  221. vreg->cfg.name, ret);
  222. }
  223. if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
  224. ret = regulator_set_voltage(vreg->reg, 0,
  225. vreg->cfg.max_uv);
  226. if (ret)
  227. icnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
  228. vreg->cfg.name, ret);
  229. }
  230. return ret;
  231. }
  232. static int icnss_vreg_off_single(struct icnss_vreg_info *vreg)
  233. {
  234. int ret = 0;
  235. if (!vreg->enabled) {
  236. icnss_pr_dbg("Regulator %s is already disabled\n",
  237. vreg->cfg.name);
  238. return 0;
  239. }
  240. icnss_pr_dbg("Regulator %s is being disabled\n",
  241. vreg->cfg.name);
  242. ret = regulator_disable(vreg->reg);
  243. if (ret)
  244. icnss_pr_err("Failed to disable regulator %s, err = %d\n",
  245. vreg->cfg.name, ret);
  246. if (vreg->cfg.load_ua) {
  247. ret = regulator_set_load(vreg->reg, 0);
  248. if (ret < 0)
  249. icnss_pr_err("Failed to set load for regulator %s, err = %d\n",
  250. vreg->cfg.name, ret);
  251. }
  252. if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
  253. ret = regulator_set_voltage(vreg->reg, 0,
  254. vreg->cfg.max_uv);
  255. if (ret)
  256. icnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
  257. vreg->cfg.name, ret);
  258. }
  259. vreg->enabled = false;
  260. return ret;
  261. }
  262. static struct icnss_vreg_cfg *get_vreg_list(u32 *vreg_list_size,
  263. unsigned long device_id)
  264. {
  265. switch (device_id) {
  266. case WCN6750_DEVICE_ID:
  267. *vreg_list_size = ICNSS_VREG_LIST_SIZE;
  268. return icnss_wcn6750_vreg_list;
  269. case ADRASTEA_DEVICE_ID:
  270. *vreg_list_size = ICNSS_VREG_ADRESTEA_LIST_SIZE;
  271. return icnss_adrestea_vreg_list;
  272. case WCN6450_DEVICE_ID:
  273. *vreg_list_size = ICNSS_VREG_EVROS_LIST_SIZE;
  274. return icnss_wcn6450_vreg_list;
  275. default:
  276. icnss_pr_err("Unsupported device_id 0x%x\n", device_id);
  277. *vreg_list_size = 0;
  278. return NULL;
  279. }
  280. }
  281. int icnss_get_vreg(struct icnss_priv *priv)
  282. {
  283. int ret = 0;
  284. int i;
  285. struct icnss_vreg_info *vreg;
  286. struct icnss_vreg_cfg *vreg_cfg = NULL;
  287. struct list_head *vreg_list = &priv->vreg_list;
  288. struct device *dev = &priv->pdev->dev;
  289. u32 vreg_list_size = 0;
  290. vreg_cfg = get_vreg_list(&vreg_list_size, priv->device_id);
  291. if (!vreg_cfg)
  292. return -EINVAL;
  293. for (i = 0; i < vreg_list_size; i++) {
  294. vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
  295. if (!vreg)
  296. return -ENOMEM;
  297. memcpy(&vreg->cfg, &vreg_cfg[i], sizeof(vreg->cfg));
  298. ret = icnss_get_vreg_single(priv, vreg);
  299. if (ret != 0) {
  300. if (ret == -ENODEV)
  301. continue;
  302. else
  303. return ret;
  304. }
  305. list_add_tail(&vreg->list, vreg_list);
  306. }
  307. return 0;
  308. }
  309. void icnss_put_vreg(struct icnss_priv *priv)
  310. {
  311. struct list_head *vreg_list = &priv->vreg_list;
  312. struct icnss_vreg_info *vreg = NULL;
  313. while (!list_empty(vreg_list)) {
  314. vreg = list_first_entry(vreg_list,
  315. struct icnss_vreg_info, list);
  316. list_del(&vreg->list);
  317. }
  318. }
  319. static int icnss_vreg_on(struct icnss_priv *priv)
  320. {
  321. struct list_head *vreg_list = &priv->vreg_list;
  322. struct icnss_vreg_info *vreg = NULL;
  323. int ret = 0;
  324. list_for_each_entry(vreg, vreg_list, list) {
  325. if (IS_ERR_OR_NULL(vreg->reg) || !vreg->cfg.is_supported)
  326. continue;
  327. if (!priv->chain_reg_info_updated &&
  328. !strcmp(ICNSS_CHAIN1_REGULATOR, vreg->cfg.name)) {
  329. priv->chain_reg_info_updated = true;
  330. if (!priv->is_chain1_supported) {
  331. vreg->cfg.is_supported = false;
  332. continue;
  333. }
  334. }
  335. ret = icnss_vreg_on_single(vreg);
  336. if (ret)
  337. break;
  338. }
  339. if (!ret)
  340. return 0;
  341. list_for_each_entry_continue_reverse(vreg, vreg_list, list) {
  342. if (IS_ERR_OR_NULL(vreg->reg) || !vreg->enabled)
  343. continue;
  344. icnss_vreg_off_single(vreg);
  345. }
  346. return ret;
  347. }
  348. static int icnss_vreg_off(struct icnss_priv *priv)
  349. {
  350. struct list_head *vreg_list = &priv->vreg_list;
  351. struct icnss_vreg_info *vreg = NULL;
  352. list_for_each_entry_reverse(vreg, vreg_list, list) {
  353. if (IS_ERR_OR_NULL(vreg->reg))
  354. continue;
  355. icnss_vreg_off_single(vreg);
  356. }
  357. return 0;
  358. }
  359. int icnss_vreg_unvote(struct icnss_priv *priv)
  360. {
  361. struct list_head *vreg_list = &priv->vreg_list;
  362. struct icnss_vreg_info *vreg = NULL;
  363. list_for_each_entry_reverse(vreg, vreg_list, list) {
  364. if (IS_ERR_OR_NULL(vreg->reg))
  365. continue;
  366. if (vreg->cfg.need_unvote)
  367. icnss_vreg_unvote_single(vreg);
  368. }
  369. return 0;
  370. }
  371. int icnss_get_clk_single(struct icnss_priv *priv,
  372. struct icnss_clk_info *clk_info)
  373. {
  374. struct device *dev = &priv->pdev->dev;
  375. struct clk *clk;
  376. int ret;
  377. clk = devm_clk_get(dev, clk_info->cfg.name);
  378. if (IS_ERR(clk)) {
  379. ret = PTR_ERR(clk);
  380. if (clk_info->cfg.required)
  381. icnss_pr_err("Failed to get clock %s, err = %d\n",
  382. clk_info->cfg.name, ret);
  383. else
  384. icnss_pr_dbg("Failed to get optional clock %s, err = %d\n",
  385. clk_info->cfg.name, ret);
  386. return ret;
  387. }
  388. clk_info->clk = clk;
  389. icnss_pr_dbg("Got clock: %s, freq: %u\n",
  390. clk_info->cfg.name, clk_info->cfg.freq);
  391. return 0;
  392. }
  393. static int icnss_clk_on_single(struct icnss_clk_info *clk_info)
  394. {
  395. int ret;
  396. if (clk_info->enabled) {
  397. icnss_pr_dbg("Clock %s is already enabled\n",
  398. clk_info->cfg.name);
  399. return 0;
  400. }
  401. icnss_pr_dbg("Clock %s is being enabled\n", clk_info->cfg.name);
  402. if (clk_info->cfg.freq) {
  403. ret = clk_set_rate(clk_info->clk, clk_info->cfg.freq);
  404. if (ret) {
  405. icnss_pr_err("Failed to set frequency %u for clock %s, err = %d\n",
  406. clk_info->cfg.freq, clk_info->cfg.name,
  407. ret);
  408. return ret;
  409. }
  410. }
  411. ret = clk_prepare_enable(clk_info->clk);
  412. if (ret) {
  413. icnss_pr_err("Failed to enable clock %s, err = %d\n",
  414. clk_info->cfg.name, ret);
  415. return ret;
  416. }
  417. clk_info->enabled = true;
  418. return 0;
  419. }
  420. static int icnss_clk_off_single(struct icnss_clk_info *clk_info)
  421. {
  422. if (!clk_info->enabled) {
  423. icnss_pr_dbg("Clock %s is already disabled\n",
  424. clk_info->cfg.name);
  425. return 0;
  426. }
  427. icnss_pr_dbg("Clock %s is being disabled\n", clk_info->cfg.name);
  428. clk_disable_unprepare(clk_info->clk);
  429. clk_info->enabled = false;
  430. return 0;
  431. }
  432. int icnss_get_clk(struct icnss_priv *priv)
  433. {
  434. struct device *dev;
  435. struct list_head *clk_list;
  436. struct icnss_clk_info *clk_info;
  437. struct icnss_clk_cfg *clk_cfg;
  438. int ret, i;
  439. u32 clk_list_size = 0;
  440. if (!priv)
  441. return -ENODEV;
  442. dev = &priv->pdev->dev;
  443. clk_list = &priv->clk_list;
  444. if (priv->device_id == ADRASTEA_DEVICE_ID) {
  445. clk_cfg = icnss_adrestea_clk_list;
  446. clk_list_size = ICNSS_CLK_ADRESTEA_LIST_SIZE;
  447. } else if (priv->device_id == WCN6750_DEVICE_ID ||
  448. priv->device_id == WCN6450_DEVICE_ID) {
  449. clk_cfg = icnss_clk_list;
  450. clk_list_size = ICNSS_CLK_LIST_SIZE;
  451. }
  452. if (!list_empty(clk_list)) {
  453. icnss_pr_dbg("Clocks have already been updated\n");
  454. return 0;
  455. }
  456. for (i = 0; i < clk_list_size; i++) {
  457. clk_info = devm_kzalloc(dev, sizeof(*clk_info), GFP_KERNEL);
  458. if (!clk_info) {
  459. ret = -ENOMEM;
  460. goto cleanup;
  461. }
  462. memcpy(&clk_info->cfg, &clk_cfg[i],
  463. sizeof(clk_info->cfg));
  464. ret = icnss_get_clk_single(priv, clk_info);
  465. if (ret != 0) {
  466. if (clk_info->cfg.required)
  467. goto cleanup;
  468. else
  469. continue;
  470. }
  471. list_add_tail(&clk_info->list, clk_list);
  472. }
  473. return 0;
  474. cleanup:
  475. while (!list_empty(clk_list)) {
  476. clk_info = list_first_entry(clk_list, struct icnss_clk_info,
  477. list);
  478. list_del(&clk_info->list);
  479. }
  480. return ret;
  481. }
  482. void icnss_put_clk(struct icnss_priv *priv)
  483. {
  484. struct device *dev;
  485. struct list_head *clk_list;
  486. struct icnss_clk_info *clk_info;
  487. if (!priv)
  488. return;
  489. dev = &priv->pdev->dev;
  490. clk_list = &priv->clk_list;
  491. while (!list_empty(clk_list)) {
  492. clk_info = list_first_entry(clk_list, struct icnss_clk_info,
  493. list);
  494. list_del(&clk_info->list);
  495. }
  496. }
  497. static int icnss_clk_on(struct list_head *clk_list)
  498. {
  499. struct icnss_clk_info *clk_info;
  500. int ret = 0;
  501. list_for_each_entry(clk_info, clk_list, list) {
  502. if (IS_ERR_OR_NULL(clk_info->clk))
  503. continue;
  504. ret = icnss_clk_on_single(clk_info);
  505. if (ret)
  506. break;
  507. }
  508. if (!ret)
  509. return 0;
  510. list_for_each_entry_continue_reverse(clk_info, clk_list, list) {
  511. if (IS_ERR_OR_NULL(clk_info->clk))
  512. continue;
  513. icnss_clk_off_single(clk_info);
  514. }
  515. return ret;
  516. }
  517. static int icnss_clk_off(struct list_head *clk_list)
  518. {
  519. struct icnss_clk_info *clk_info;
  520. list_for_each_entry_reverse(clk_info, clk_list, list) {
  521. if (IS_ERR_OR_NULL(clk_info->clk))
  522. continue;
  523. icnss_clk_off_single(clk_info);
  524. }
  525. return 0;
  526. }
  527. int icnss_hw_power_on(struct icnss_priv *priv)
  528. {
  529. int ret = 0;
  530. icnss_pr_dbg("HW Power on: state: 0x%lx\n", priv->state);
  531. spin_lock(&priv->on_off_lock);
  532. if (test_bit(ICNSS_POWER_ON, &priv->state)) {
  533. spin_unlock(&priv->on_off_lock);
  534. return ret;
  535. }
  536. set_bit(ICNSS_POWER_ON, &priv->state);
  537. spin_unlock(&priv->on_off_lock);
  538. ret = icnss_vreg_on(priv);
  539. if (ret) {
  540. icnss_pr_err("Failed to turn on vreg, err = %d\n", ret);
  541. goto out;
  542. }
  543. ret = icnss_clk_on(&priv->clk_list);
  544. if (ret)
  545. goto vreg_off;
  546. return ret;
  547. vreg_off:
  548. icnss_vreg_off(priv);
  549. out:
  550. clear_bit(ICNSS_POWER_ON, &priv->state);
  551. return ret;
  552. }
  553. int icnss_hw_power_off(struct icnss_priv *priv)
  554. {
  555. int ret = 0;
  556. if (test_bit(HW_ALWAYS_ON, &priv->ctrl_params.quirks))
  557. return 0;
  558. if (test_bit(ICNSS_FW_DOWN, &priv->state))
  559. return 0;
  560. icnss_pr_dbg("HW Power off: 0x%lx\n", priv->state);
  561. spin_lock(&priv->on_off_lock);
  562. if (!test_bit(ICNSS_POWER_ON, &priv->state)) {
  563. spin_unlock(&priv->on_off_lock);
  564. return ret;
  565. }
  566. clear_bit(ICNSS_POWER_ON, &priv->state);
  567. spin_unlock(&priv->on_off_lock);
  568. icnss_clk_off(&priv->clk_list);
  569. ret = icnss_vreg_off(priv);
  570. return ret;
  571. }
  572. int icnss_power_on(struct device *dev)
  573. {
  574. struct icnss_priv *priv = dev_get_drvdata(dev);
  575. if (!priv) {
  576. icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
  577. dev, priv);
  578. return -EINVAL;
  579. }
  580. icnss_pr_dbg("Power On: 0x%lx\n", priv->state);
  581. return icnss_hw_power_on(priv);
  582. }
  583. EXPORT_SYMBOL(icnss_power_on);
  584. int icnss_power_off(struct device *dev)
  585. {
  586. struct icnss_priv *priv = dev_get_drvdata(dev);
  587. if (!priv) {
  588. icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
  589. dev, priv);
  590. return -EINVAL;
  591. }
  592. icnss_pr_dbg("Power Off: 0x%lx\n", priv->state);
  593. return icnss_hw_power_off(priv);
  594. }
  595. EXPORT_SYMBOL(icnss_power_off);
  596. void icnss_put_resources(struct icnss_priv *priv)
  597. {
  598. icnss_put_clk(priv);
  599. icnss_put_vreg(priv);
  600. }
  601. #if IS_ENABLED(CONFIG_MSM_QMP)
  602. /**
  603. * icnss_aop_interface_init: Initialize AOP interface: either mbox channel or direct QMP
  604. * @priv: Pointer to icnss platform data
  605. *
  606. * Device tree file should have either mbox or qmp configured, but not both.
  607. * Based on device tree configuration setup mbox channel or QMP
  608. *
  609. * Return: 0 for success, otherwise error code
  610. */
  611. int icnss_aop_interface_init(struct icnss_priv *priv)
  612. {
  613. struct mbox_client *mbox = &priv->mbox_client_data;
  614. struct mbox_chan *chan;
  615. int ret = 0, ol_cpr = 0;
  616. ol_cpr = of_property_read_string(priv->pdev->dev.of_node,
  617. "qcom,vreg_ol_cpr",
  618. &priv->cpr_info.vreg_ol_cpr);
  619. if (ol_cpr && !priv->pdc_init_table) {
  620. icnss_pr_dbg("Vreg for OL CPR and pdc_init table not configured\n");
  621. return -EINVAL;
  622. }
  623. mbox->dev = &priv->pdev->dev;
  624. mbox->tx_block = true;
  625. mbox->tx_tout = ICNSS_MBOX_TIMEOUT_MS;
  626. mbox->knows_txdone = false;
  627. priv->mbox_chan = NULL;
  628. priv->qmp = NULL;
  629. priv->use_direct_qmp = false;
  630. /* First try to get mbox channel, if it fails then try qmp_get
  631. * In device tree file there should be either mboxes or qmp,
  632. * cannot have both properties at the same time.
  633. */
  634. chan = mbox_request_channel(mbox, 0);
  635. if (IS_ERR(chan)) {
  636. ret = PTR_ERR(chan);
  637. icnss_pr_dbg("Failed to get mbox channel with err %d\n", ret);
  638. priv->qmp = qmp_get(&priv->pdev->dev);
  639. if (IS_ERR(priv->qmp)) {
  640. icnss_pr_err("Failed to get qmp\n");
  641. return PTR_ERR(priv->qmp);
  642. } else {
  643. priv->use_direct_qmp = true;
  644. icnss_pr_dbg("QMP initialized\n");
  645. }
  646. } else {
  647. priv->mbox_chan = chan;
  648. icnss_pr_dbg("Mbox channel initialized\n");
  649. }
  650. ret = icnss_aop_pdc_reconfig(priv);
  651. if (ret)
  652. icnss_pr_err("Failed to reconfig WLAN PDC, err = %d\n", ret);
  653. return ret;
  654. }
  655. /**
  656. * icnss_aop_interface_deinit: Cleanup AOP interface
  657. * @priv: Pointer to icnss platform data
  658. *
  659. * Cleanup mbox channel or QMP whichever was configured during initialization.
  660. *
  661. * Return: None
  662. */
  663. void icnss_aop_interface_deinit(struct icnss_priv *priv)
  664. {
  665. if (!IS_ERR_OR_NULL(priv->mbox_chan))
  666. mbox_free_channel(priv->mbox_chan);
  667. if (!IS_ERR_OR_NULL(priv->qmp)) {
  668. qmp_put(priv->qmp);
  669. priv->use_direct_qmp = false;
  670. }
  671. }
  672. static int icnss_aop_set_vreg_param(struct icnss_priv *priv,
  673. const char *vreg_name,
  674. enum icnss_vreg_param param,
  675. enum icnss_tcs_seq seq, int val)
  676. {
  677. struct qmp_pkt pkt;
  678. char mbox_msg[ICNSS_MBOX_MSG_MAX_LEN];
  679. static const char * const vreg_param_str[] = {"v", "m", "e"};
  680. static const char *const tcs_seq_str[] = {"upval", "dwnval", "enable"};
  681. int ret = 0;
  682. if (param > ICNSS_VREG_ENABLE || seq > ICNSS_TCS_ALL_SEQ || !vreg_name)
  683. return -EINVAL;
  684. snprintf(mbox_msg, ICNSS_MBOX_MSG_MAX_LEN,
  685. "{class: wlan_pdc, res: %s.%s, %s: %d}", vreg_name,
  686. vreg_param_str[param], tcs_seq_str[seq], val);
  687. if (priv->use_direct_qmp) {
  688. icnss_pr_dbg("Sending AOP QMP msg: %s\n", mbox_msg);
  689. ret = qmp_send(priv->qmp, mbox_msg, ICNSS_MBOX_MSG_MAX_LEN);
  690. if (ret < 0)
  691. icnss_pr_err("Failed to send AOP QMP msg: %s\n", mbox_msg);
  692. else
  693. ret = 0;
  694. } else {
  695. icnss_pr_dbg("Sending AOP Mbox msg: %s\n", mbox_msg);
  696. pkt.size = ICNSS_MBOX_MSG_MAX_LEN;
  697. pkt.data = mbox_msg;
  698. ret = mbox_send_message(priv->mbox_chan, &pkt);
  699. if (ret < 0)
  700. icnss_pr_err("Failed to send AOP mbox msg: %s,ret: %d\n",
  701. mbox_msg, ret);
  702. else
  703. ret = 0;
  704. }
  705. return ret;
  706. }
  707. /* icnss_aop_pdc_reconfig: Send AOP msg to configure PDC table for WLAN device
  708. * @priv: Pointer to icnss platform data
  709. *
  710. * Send AOP QMP or Mbox msg to configure PDC table for WLAN device
  711. *
  712. * Return: 0 for success, otherwise error code
  713. */
  714. int icnss_aop_pdc_reconfig(struct icnss_priv *priv)
  715. {
  716. u32 i;
  717. int ret;
  718. char *mbox_msg;
  719. struct qmp_pkt pkt;
  720. if (priv->pdc_init_table_len <= 0 || !priv->pdc_init_table)
  721. return 0;
  722. icnss_pr_dbg("Setting PDC defaults for device ID: (0x%x)\n",
  723. priv->device_id);
  724. for (i = 0; i < priv->pdc_init_table_len; i++) {
  725. mbox_msg = (char *)priv->pdc_init_table[i];
  726. if (priv->use_direct_qmp) {
  727. icnss_pr_dbg("Sending AOP QMP msg: %s\n", mbox_msg);
  728. ret = qmp_send(priv->qmp, mbox_msg,
  729. ICNSS_MBOX_MSG_MAX_LEN);
  730. if (ret < 0)
  731. icnss_pr_err("Failed to send AOP QMP msg: %s\n",
  732. mbox_msg);
  733. else
  734. ret = 0;
  735. } else {
  736. icnss_pr_dbg("Sending AOP Mbox msg: %s\n", mbox_msg);
  737. pkt.size = ICNSS_MBOX_MSG_MAX_LEN;
  738. pkt.data = mbox_msg;
  739. ret = mbox_send_message(priv->mbox_chan, &pkt);
  740. if (ret < 0)
  741. icnss_pr_err("Failed to send AOP mbox msg: %s,ret: %d\n",
  742. mbox_msg, ret);
  743. else
  744. ret = 0;
  745. }
  746. }
  747. return ret;
  748. }
  749. #else
  750. int icnss_aop_interface_init(struct icnss_priv *priv)
  751. {
  752. return 0;
  753. }
  754. void icnss_aop_interface_deinit(struct icnss_priv *priv)
  755. {
  756. }
  757. static int icnss_aop_set_vreg_param(struct icnss_priv *priv,
  758. const char *vreg_name,
  759. enum icnss_vreg_param param,
  760. enum icnss_tcs_seq seq, int val)
  761. {
  762. return 0;
  763. }
  764. int icnss_aop_pdc_reconfig(struct icnss_priv *priv)
  765. {
  766. return 0;
  767. }
  768. #endif
  769. void icnss_power_misc_params_init(struct icnss_priv *priv)
  770. {
  771. struct device *dev = &priv->pdev->dev;
  772. int ret;
  773. /* common DT Entries */
  774. priv->pdc_init_table_len =
  775. of_property_count_strings(dev->of_node,
  776. "qcom,pdc_init_table");
  777. if (priv->pdc_init_table_len > 0) {
  778. priv->pdc_init_table =
  779. kcalloc(priv->pdc_init_table_len,
  780. sizeof(char *), GFP_KERNEL);
  781. if (priv->pdc_init_table) {
  782. ret = of_property_read_string_array(dev->of_node,
  783. "qcom,pdc_init_table",
  784. priv->pdc_init_table,
  785. priv->pdc_init_table_len);
  786. if (ret < 0)
  787. icnss_pr_err("Failed to get PDC Init Table\n");
  788. } else {
  789. icnss_pr_err("Failed to alloc PDC Init Table mem\n");
  790. }
  791. } else {
  792. icnss_pr_dbg("PDC Init Table not configured\n");
  793. }
  794. }
  795. int icnss_update_cpr_info(struct icnss_priv *priv)
  796. {
  797. struct icnss_cpr_info *cpr_info = &priv->cpr_info;
  798. if (!cpr_info->vreg_ol_cpr || (!priv->mbox_chan && !priv->use_direct_qmp)) {
  799. icnss_pr_dbg("Mbox channel / QMP / OL CPR Vreg not configured\n");
  800. return 0;
  801. }
  802. if (cpr_info->voltage == 0) {
  803. icnss_pr_err("Voltage %dmV is not valid\n", cpr_info->voltage);
  804. return -EINVAL;
  805. }
  806. cpr_info->voltage = cpr_info->voltage > BT_CXMX_VOLTAGE_MV ?
  807. cpr_info->voltage : BT_CXMX_VOLTAGE_MV;
  808. return icnss_aop_set_vreg_param(priv,
  809. cpr_info->vreg_ol_cpr,
  810. ICNSS_VREG_VOLTAGE,
  811. ICNSS_TCS_UP_SEQ,
  812. cpr_info->voltage);
  813. }
  814. static int icnss_get_battery_level(struct icnss_priv *priv)
  815. {
  816. int err = 0, battery_percentage = 0;
  817. union power_supply_propval psp = {0,};
  818. if (!priv->batt_psy)
  819. priv->batt_psy = power_supply_get_by_name("battery");
  820. if (priv->batt_psy) {
  821. err = power_supply_get_property(priv->batt_psy,
  822. POWER_SUPPLY_PROP_CAPACITY,
  823. &psp);
  824. if (err) {
  825. icnss_pr_err("battery percentage read error:%d\n", err);
  826. goto out;
  827. }
  828. battery_percentage = psp.intval;
  829. }
  830. icnss_pr_info("Battery Percentage: %d\n", battery_percentage);
  831. out:
  832. return battery_percentage;
  833. }
  834. static void icnss_update_soc_level(struct work_struct *work)
  835. {
  836. int battery_percentage = 0, current_updated_voltage = 0, err = 0;
  837. int level_count;
  838. struct icnss_priv *priv = container_of(work, struct icnss_priv, soc_update_work);
  839. battery_percentage = icnss_get_battery_level(priv);
  840. if (!battery_percentage ||
  841. battery_percentage > ICNSS_MAX_BATTERY_LEVEL) {
  842. icnss_pr_err("Battery percentage read failure\n");
  843. return;
  844. }
  845. for (level_count = 0; level_count < ICNSS_BATTERY_LEVEL_COUNT;
  846. level_count++) {
  847. if (battery_percentage >=
  848. icnss_battery_level[level_count].lower_battery_threshold) {
  849. current_updated_voltage =
  850. icnss_battery_level[level_count].ldo_voltage;
  851. break;
  852. }
  853. }
  854. if (level_count != ICNSS_BATTERY_LEVEL_COUNT &&
  855. priv->last_updated_voltage != current_updated_voltage) {
  856. err = icnss_send_vbatt_update(priv, current_updated_voltage);
  857. if (err < 0) {
  858. icnss_pr_err("Unable to update ldo voltage");
  859. return;
  860. }
  861. priv->last_updated_voltage = current_updated_voltage;
  862. }
  863. }
  864. static int icnss_battery_supply_callback(struct notifier_block *nb,
  865. unsigned long event, void *data)
  866. {
  867. struct power_supply *psy = data;
  868. struct icnss_priv *priv = container_of(nb, struct icnss_priv,
  869. psf_nb);
  870. if (strcmp(psy->desc->name, "battery"))
  871. return NOTIFY_OK;
  872. if (test_bit(ICNSS_WLFW_CONNECTED, &priv->state) &&
  873. !test_bit(ICNSS_FW_DOWN, &priv->state))
  874. queue_work(priv->soc_update_wq, &priv->soc_update_work);
  875. return NOTIFY_OK;
  876. }
  877. int icnss_get_psf_info(struct icnss_priv *priv)
  878. {
  879. int ret = 0;
  880. priv->soc_update_wq = alloc_workqueue("icnss_soc_update",
  881. WQ_UNBOUND, 1);
  882. if (!priv->soc_update_wq) {
  883. icnss_pr_err("Workqueue creation failed for soc update\n");
  884. ret = -EFAULT;
  885. goto out;
  886. }
  887. priv->psf_nb.notifier_call = icnss_battery_supply_callback;
  888. ret = power_supply_reg_notifier(&priv->psf_nb);
  889. if (ret < 0) {
  890. icnss_pr_err("Power supply framework registration err: %d\n",
  891. ret);
  892. goto err_psf_registration;
  893. }
  894. INIT_WORK(&priv->soc_update_work, icnss_update_soc_level);
  895. return 0;
  896. err_psf_registration:
  897. destroy_workqueue(priv->soc_update_wq);
  898. out:
  899. return ret;
  900. }