ubwcp_main.c 86 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/dma-buf.h>
  8. #include <linux/slab.h>
  9. #include <linux/cdev.h>
  10. #include <linux/hashtable.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/types.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/of.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_address.h>
  17. #include <linux/genalloc.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/numa.h>
  21. #include <linux/memory_hotplug.h>
  22. #include <asm/page.h>
  23. #include <linux/delay.h>
  24. #include <linux/ubwcp_dma_heap.h>
  25. #include <linux/debugfs.h>
  26. #include <linux/clk.h>
  27. #include <linux/iommu.h>
  28. #include <linux/set_memory.h>
  29. #include <linux/range.h>
  30. MODULE_IMPORT_NS(DMA_BUF);
  31. #include "include/kernel/ubwcp.h"
  32. #include "ubwcp_hw.h"
  33. #include "include/uapi/ubwcp_ioctl.h"
  34. #define CREATE_TRACE_POINTS
  35. #include "ubwcp_trace.h"
  36. #define UBWCP_NUM_DEVICES 1
  37. #define UBWCP_DEVICE_NAME "ubwcp"
  38. #define UBWCP_BUFFER_DESC_OFFSET 64
  39. #define UBWCP_BUFFER_DESC_COUNT 256
  40. #define CACHE_ADDR(x) ((x) >> 6)
  41. #define PAGE_ADDR(x) ((x) >> 12)
  42. #define UBWCP_ALIGN(_x, _y) ((((_x) + (_y) - 1)/(_y))*(_y))
  43. #define DBG_BUF_ATTR(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  44. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  45. } while (0)
  46. #define DBG(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  47. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  48. } while (0)
  49. #define ERR(fmt, args...) pr_err("ubwcp: %d: %s(): ~~~ERROR~~~: " fmt "\n", __LINE__, __func__, ##args)
  50. #define ERR_RATE_LIMIT(fmt, args...) pr_err_ratelimited("ubwcp: %s(): ~~~ERROR~~~: " fmt "\n",\
  51. __func__, ##args)
  52. #define FENTRY() DBG("")
  53. #define META_DATA_PITCH_ALIGN 64
  54. #define META_DATA_HEIGHT_ALIGN 16
  55. #define META_DATA_SIZE_ALIGN 4096
  56. #define PIXEL_DATA_SIZE_ALIGN 4096
  57. #define UBWCP_SYNC_GRANULE 0x4000000L /* 64 MB */
  58. enum ula_remove_mem_status {
  59. ULA_REMOVE_MEM_SUCCESS = 0,
  60. ULA_REMOVE_MEM_ABORTED = 1
  61. };
  62. struct ubwcp_desc {
  63. int idx;
  64. void *ptr;
  65. };
  66. /* TBD: confirm size of width/height */
  67. struct ubwcp_dimension {
  68. u16 width;
  69. u16 height;
  70. };
  71. struct ubwcp_plane_info {
  72. u16 pixel_bytes;
  73. u16 per_pixel;
  74. struct ubwcp_dimension tilesize_p; /* pixels */
  75. struct ubwcp_dimension macrotilesize_p; /* pixels */
  76. };
  77. struct ubwcp_image_format_info {
  78. u16 planes;
  79. struct ubwcp_plane_info p_info[2];
  80. };
  81. enum ubwcp_std_image_format {
  82. RGBA = 0,
  83. NV12 = 1,
  84. NV124R = 2,
  85. P010 = 3,
  86. TP10 = 4,
  87. P016 = 5,
  88. INFO_FORMAT_LIST_SIZE,
  89. STD_IMAGE_FORMAT_INVALID = 0xFF
  90. };
  91. enum ubwcp_state {
  92. UBWCP_STATE_READY = 0,
  93. UBWCP_STATE_INVALID = -1,
  94. UBWCP_STATE_FAULT = -2,
  95. };
  96. struct ubwcp_driver {
  97. /* cdev related */
  98. dev_t devt;
  99. struct class *dev_class; //sysfs dev class
  100. struct device *dev_sys; //sysfs dev
  101. struct cdev cdev; //char dev
  102. /* debugfs */
  103. struct dentry *debugfs_root;
  104. bool read_err_irq_en;
  105. bool write_err_irq_en;
  106. bool decode_err_irq_en;
  107. bool encode_err_irq_en;
  108. /* ubwcp devices */
  109. struct device *dev; //ubwcp device
  110. struct device *dev_desc_cb; //smmu dev for descriptors
  111. struct device *dev_buf_cb; //smmu dev for ubwcp buffers
  112. void __iomem *base; //ubwcp base address
  113. struct regulator *vdd;
  114. struct clk **clocks;
  115. int num_clocks;
  116. /* interrupts */
  117. int irq_range_ck_rd;
  118. int irq_range_ck_wr;
  119. int irq_encode;
  120. int irq_decode;
  121. /* ula address pool */
  122. u64 ula_pool_base;
  123. u64 ula_pool_size;
  124. struct gen_pool *ula_pool;
  125. configure_mmap mmap_config_fptr;
  126. /* HW version */
  127. u32 hw_ver_major;
  128. u32 hw_ver_minor;
  129. /* keep track of all potential buffers.
  130. * hash table index'ed using dma_buf ptr.
  131. * 2**13 = 8192 hash values
  132. */
  133. DECLARE_HASHTABLE(buf_table, 13);
  134. /* buffer descriptor */
  135. void *buffer_desc_base; /* CPU address */
  136. dma_addr_t buffer_desc_dma_handle; /* dma address */
  137. size_t buffer_desc_size;
  138. struct ubwcp_desc desc_list[UBWCP_BUFFER_DESC_COUNT];
  139. struct ubwcp_image_format_info format_info[INFO_FORMAT_LIST_SIZE];
  140. /* driver state */
  141. enum ubwcp_state state;
  142. atomic_t num_non_lin_buffers;
  143. bool mem_online;
  144. struct mutex desc_lock; /* allocate/free descriptors */
  145. spinlock_t buf_table_lock; /* add/remove dma_buf into list of managed bufffers */
  146. struct mutex mem_hotplug_lock; /* memory hotplug lock */
  147. struct mutex ula_lock; /* allocate/free ula */
  148. struct mutex ubwcp_flush_lock; /* ubwcp flush */
  149. struct mutex hw_range_ck_lock; /* range ck */
  150. struct list_head err_handler_list; /* error handler list */
  151. spinlock_t err_handler_list_lock; /* err_handler_list lock */
  152. struct dev_pagemap pgmap;
  153. };
  154. struct ubwcp_buf {
  155. struct hlist_node hnode;
  156. struct ubwcp_driver *ubwcp;
  157. struct ubwcp_buffer_attrs buf_attr;
  158. bool perm;
  159. struct ubwcp_desc *desc;
  160. bool buf_attr_set;
  161. enum dma_data_direction lock_dir;
  162. int lock_count;
  163. /* dma_buf info */
  164. struct dma_buf *dma_buf;
  165. struct dma_buf_attachment *attachment;
  166. struct sg_table *sgt;
  167. /* ula info */
  168. phys_addr_t ula_pa;
  169. size_t ula_size;
  170. /* meta metadata */
  171. struct ubwcp_hw_meta_metadata mmdata;
  172. struct mutex lock;
  173. };
  174. static struct ubwcp_driver *me;
  175. static u32 ubwcp_debug_trace_enable;
  176. static struct ubwcp_driver *ubwcp_get_driver(void)
  177. {
  178. if (!me)
  179. WARN(1, "ubwcp: driver ptr requested but driver not initialized");
  180. return me;
  181. }
  182. static void image_format_init(struct ubwcp_driver *ubwcp)
  183. { /* planes, bytes/p, Tp , MTp */
  184. ubwcp->format_info[RGBA] = (struct ubwcp_image_format_info)
  185. {1, {{4, 1, {16, 4}, {64, 16}}}};
  186. ubwcp->format_info[NV12] = (struct ubwcp_image_format_info)
  187. {2, {{1, 1, {32, 8}, {128, 32}},
  188. {2, 1, {16, 8}, { 64, 32}}}};
  189. ubwcp->format_info[NV124R] = (struct ubwcp_image_format_info)
  190. {2, {{1, 1, {64, 4}, {256, 16}},
  191. {2, 1, {32, 4}, {128, 16}}}};
  192. ubwcp->format_info[P010] = (struct ubwcp_image_format_info)
  193. {2, {{2, 1, {32, 4}, {128, 16}},
  194. {4, 1, {16, 4}, { 64, 16}}}};
  195. ubwcp->format_info[TP10] = (struct ubwcp_image_format_info)
  196. {2, {{4, 3, {48, 4}, {192, 16}},
  197. {8, 3, {24, 4}, { 96, 16}}}};
  198. ubwcp->format_info[P016] = (struct ubwcp_image_format_info)
  199. {2, {{2, 1, {32, 4}, {128, 16}},
  200. {4, 1, {16, 4}, { 64, 16}}}};
  201. }
  202. static void ubwcp_buf_desc_list_init(struct ubwcp_driver *ubwcp)
  203. {
  204. int idx;
  205. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  206. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  207. desc_list[idx].idx = -1;
  208. desc_list[idx].ptr = NULL;
  209. }
  210. }
  211. static int ubwcp_init_clocks(struct ubwcp_driver *ubwcp, struct device *dev)
  212. {
  213. const char *cname;
  214. struct property *prop;
  215. int i;
  216. ubwcp->num_clocks =
  217. of_property_count_strings(dev->of_node, "clock-names");
  218. if (ubwcp->num_clocks < 1) {
  219. ubwcp->num_clocks = 0;
  220. return 0;
  221. }
  222. ubwcp->clocks = devm_kzalloc(dev,
  223. sizeof(*ubwcp->clocks) * ubwcp->num_clocks, GFP_KERNEL);
  224. if (!ubwcp->clocks)
  225. return -ENOMEM;
  226. i = 0;
  227. of_property_for_each_string(dev->of_node, "clock-names",
  228. prop, cname) {
  229. struct clk *c = devm_clk_get(dev, cname);
  230. if (IS_ERR(c)) {
  231. ERR("Couldn't get clock: %s\n", cname);
  232. return PTR_ERR(c);
  233. }
  234. ubwcp->clocks[i] = c;
  235. ++i;
  236. }
  237. return 0;
  238. }
  239. static int ubwcp_enable_clocks(struct ubwcp_driver *ubwcp)
  240. {
  241. int i, ret = 0;
  242. for (i = 0; i < ubwcp->num_clocks; ++i) {
  243. ret = clk_prepare_enable(ubwcp->clocks[i]);
  244. if (ret) {
  245. ERR("Couldn't enable clock #%d\n", i);
  246. while (i--)
  247. clk_disable_unprepare(ubwcp->clocks[i]);
  248. break;
  249. }
  250. }
  251. return ret;
  252. }
  253. static void ubwcp_disable_clocks(struct ubwcp_driver *ubwcp)
  254. {
  255. int i;
  256. for (i = ubwcp->num_clocks; i; --i)
  257. clk_disable_unprepare(ubwcp->clocks[i - 1]);
  258. }
  259. /* UBWCP Power control */
  260. static int ubwcp_power(struct ubwcp_driver *ubwcp, bool enable)
  261. {
  262. int ret = 0;
  263. if (enable)
  264. ret = regulator_enable(ubwcp->vdd);
  265. else
  266. ret = regulator_disable(ubwcp->vdd);
  267. if (ret) {
  268. ERR("regulator call (enable: %d) failed: %d", enable, ret);
  269. return ret;
  270. }
  271. if (enable) {
  272. ret = ubwcp_enable_clocks(ubwcp);
  273. if (ret) {
  274. ERR("enable clocks failed: %d", ret);
  275. regulator_disable(ubwcp->vdd);
  276. return ret;
  277. }
  278. } else {
  279. ubwcp_disable_clocks(ubwcp);
  280. }
  281. return ret;
  282. }
  283. /* get ubwcp_buf corresponding to the given dma_buf */
  284. static struct ubwcp_buf *dma_buf_to_ubwcp_buf(struct dma_buf *dmabuf)
  285. {
  286. struct ubwcp_buf *buf = NULL;
  287. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  288. unsigned long flags;
  289. if (!dmabuf || !ubwcp)
  290. return NULL;
  291. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  292. /* look up ubwcp_buf corresponding to this dma_buf */
  293. hash_for_each_possible(ubwcp->buf_table, buf, hnode, (u64)dmabuf) {
  294. if (buf->dma_buf == dmabuf)
  295. break;
  296. }
  297. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  298. return buf;
  299. }
  300. /* return ubwcp hardware version */
  301. int ubwcp_get_hw_version(struct ubwcp_ioctl_hw_version *ver)
  302. {
  303. struct ubwcp_driver *ubwcp;
  304. FENTRY();
  305. if (!ver) {
  306. ERR("invalid version ptr");
  307. return -EINVAL;
  308. }
  309. ubwcp = ubwcp_get_driver();
  310. if (!ubwcp)
  311. return -1;
  312. if (ubwcp->state != UBWCP_STATE_FAULT)
  313. return -EPERM;
  314. ver->major = ubwcp->hw_ver_major;
  315. ver->minor = ubwcp->hw_ver_minor;
  316. return 0;
  317. }
  318. EXPORT_SYMBOL(ubwcp_get_hw_version);
  319. static int ula_add_mem(struct ubwcp_driver *ubwcp)
  320. {
  321. int ret = 0;
  322. int nid;
  323. void *ptr;
  324. nid = memory_add_physaddr_to_nid(ubwcp->ula_pool_base);
  325. DBG("calling memremap_pages()...");
  326. ubwcp->pgmap.type = MEMORY_DEVICE_GENERIC;
  327. ubwcp->pgmap.nr_range = 1;
  328. ubwcp->pgmap.range.start = ubwcp->ula_pool_base;
  329. ubwcp->pgmap.range.end = ubwcp->ula_pool_base + ubwcp->ula_pool_size - 1;
  330. trace_ubwcp_memremap_pages_start(ubwcp->ula_pool_size);
  331. ptr = memremap_pages(&ubwcp->pgmap, nid);
  332. trace_ubwcp_memremap_pages_end(ubwcp->ula_pool_size);
  333. if (IS_ERR(ptr)) {
  334. ret = IS_ERR(ptr);
  335. ERR("memremap_pages() failed st:0x%lx sz:0x%lx err: %d",
  336. ubwcp->ula_pool_base,
  337. ubwcp->ula_pool_size,
  338. ret);
  339. } else {
  340. DBG("memremap_pages() ula_pool_base:0x%llx, size:0x%zx, kernel addr:0x%p",
  341. ubwcp->ula_pool_base,
  342. ubwcp->ula_pool_size,
  343. page_to_virt(pfn_to_page(PFN_DOWN(ubwcp->ula_pool_base))));
  344. }
  345. return ret;
  346. }
  347. static int ula_map_uncached(u64 base, u64 size)
  348. {
  349. int ret;
  350. trace_ubwcp_set_direct_map_range_uncached_start(size);
  351. ret = set_direct_map_range_uncached((unsigned long)phys_to_virt(base), size >> PAGE_SHIFT);
  352. trace_ubwcp_set_direct_map_range_uncached_end(size);
  353. if (ret)
  354. ERR("set_direct_map_range_uncached failed st:0x%lx num pages:%lu err: %d",
  355. base, size >> PAGE_SHIFT, ret);
  356. return ret;
  357. }
  358. static void ula_unmap(struct ubwcp_driver *ubwcp)
  359. {
  360. DBG("Calling memunmap_pages() for ULA PA pool");
  361. trace_ubwcp_memunmap_pages_start(ubwcp->ula_pool_size);
  362. memunmap_pages(&ubwcp->pgmap);
  363. trace_ubwcp_memunmap_pages_end(ubwcp->ula_pool_size);
  364. }
  365. static void ula_sync_for_cpu(struct device *dev, u64 addr, unsigned long size)
  366. {
  367. DBG("Partial sync offset:0x%lx size:0x%lx", addr, size);
  368. trace_ubwcp_dma_sync_single_for_cpu_start(size);
  369. dma_sync_single_for_cpu(dev, addr, size, DMA_BIDIRECTIONAL);
  370. trace_ubwcp_dma_sync_single_for_cpu_end(size);
  371. }
  372. /** Remove ula memory in chunks
  373. * Abort if new buffer addition is detected
  374. * If remove succeeds or aborted, return success
  375. * status value indicates if mem was removed or aborted (not removed)
  376. * Otherwise return failure
  377. */
  378. static int ula_remove_mem(struct ubwcp_driver *ubwcp, enum ula_remove_mem_status *status)
  379. {
  380. int ret = 0;
  381. unsigned long sync_remain = ubwcp->ula_pool_size;
  382. unsigned long sync_offset = 0;
  383. unsigned long sync_size = 0;
  384. ret = ula_map_uncached(ubwcp->ula_pool_base, ubwcp->ula_pool_size);
  385. if (ret)
  386. return ret;
  387. trace_ubwcp_offline_sync_start(ubwcp->ula_pool_size);
  388. while (sync_remain > 0) {
  389. if (atomic_read(&ubwcp->num_non_lin_buffers) > 0) {
  390. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  391. ula_unmap(ubwcp);
  392. if (ula_add_mem(ubwcp)) {
  393. ERR("remove mem: failed to add back during abort");
  394. return -1;
  395. }
  396. *status = ULA_REMOVE_MEM_ABORTED;
  397. return 0;
  398. }
  399. if (UBWCP_SYNC_GRANULE > sync_remain) {
  400. sync_size = sync_remain;
  401. sync_remain = 0;
  402. } else {
  403. sync_size = UBWCP_SYNC_GRANULE;
  404. sync_remain -= UBWCP_SYNC_GRANULE;
  405. }
  406. ula_sync_for_cpu(ubwcp->dev, ubwcp->ula_pool_base + sync_offset, sync_size);
  407. sync_offset += sync_size;
  408. }
  409. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  410. ula_unmap(ubwcp);
  411. *status = ULA_REMOVE_MEM_SUCCESS;
  412. return 0;
  413. }
  414. static int inc_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  415. {
  416. atomic_inc(&ubwcp->num_non_lin_buffers);
  417. mutex_lock(&ubwcp->mem_hotplug_lock);
  418. if (!ubwcp->mem_online) {
  419. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  420. ERR("Bad state: num_non_lin_buffers should not be 0");
  421. goto err;
  422. }
  423. if (ubwcp_power(ubwcp, true))
  424. goto err;
  425. if (ula_add_mem(ubwcp))
  426. goto err_add_memory;
  427. ubwcp->mem_online = true;
  428. }
  429. mutex_unlock(&ubwcp->mem_hotplug_lock);
  430. return 0;
  431. err_add_memory:
  432. ubwcp_power(ubwcp, false);
  433. err:
  434. atomic_dec(&ubwcp->num_non_lin_buffers);
  435. mutex_unlock(&ubwcp->mem_hotplug_lock);
  436. ubwcp->state = UBWCP_STATE_FAULT;
  437. return -1;
  438. }
  439. static int dec_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  440. {
  441. int ret;
  442. enum ula_remove_mem_status remove_status;
  443. atomic_dec(&ubwcp->num_non_lin_buffers);
  444. mutex_lock(&ubwcp->mem_hotplug_lock);
  445. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  446. DBG("last buffer: ~~~~~~~~~~~");
  447. if (!ubwcp->mem_online) {
  448. ERR("Bad state: mem_online should not be false");
  449. goto err;
  450. }
  451. ret = ula_remove_mem(ubwcp, &remove_status);
  452. if (ret)
  453. goto err;
  454. if (remove_status == ULA_REMOVE_MEM_SUCCESS) {
  455. ubwcp->mem_online = false;
  456. if (ubwcp_power(ubwcp, false))
  457. goto err;
  458. } else if (remove_status == ULA_REMOVE_MEM_ABORTED) {
  459. DBG("ula memory offline aborted");
  460. } else {
  461. ERR("unexpected ula remove status: %d", remove_status);
  462. goto err;
  463. }
  464. }
  465. mutex_unlock(&ubwcp->mem_hotplug_lock);
  466. return 0;
  467. err:
  468. atomic_inc(&ubwcp->num_non_lin_buffers);
  469. mutex_unlock(&ubwcp->mem_hotplug_lock);
  470. ubwcp->state = UBWCP_STATE_FAULT;
  471. return -1;
  472. }
  473. /**
  474. *
  475. * Initialize ubwcp buffer for the given dma_buf. This
  476. * initializes ubwcp internal data structures and possibly hw to
  477. * use ubwcp for this buffer.
  478. *
  479. * @param dmabuf : ptr to the buffer to be configured for ubwcp
  480. *
  481. * @return int : 0 on success, otherwise error code
  482. */
  483. static int ubwcp_init_buffer(struct dma_buf *dmabuf)
  484. {
  485. struct ubwcp_buf *buf;
  486. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  487. unsigned long flags;
  488. FENTRY();
  489. trace_ubwcp_init_buffer_start(dmabuf);
  490. if (!ubwcp) {
  491. trace_ubwcp_init_buffer_end(dmabuf);
  492. return -1;
  493. }
  494. if (ubwcp->state != UBWCP_STATE_READY) {
  495. ERR("driver in invalid state: %d", ubwcp->state);
  496. trace_ubwcp_init_buffer_end(dmabuf);
  497. return -EPERM;
  498. }
  499. if (!dmabuf) {
  500. ERR("NULL dmabuf input ptr");
  501. trace_ubwcp_init_buffer_end(dmabuf);
  502. return -EINVAL;
  503. }
  504. if (dma_buf_to_ubwcp_buf(dmabuf)) {
  505. ERR("dma_buf already initialized for ubwcp");
  506. trace_ubwcp_init_buffer_end(dmabuf);
  507. return -EEXIST;
  508. }
  509. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  510. if (!buf) {
  511. ERR("failed to alloc for new ubwcp_buf");
  512. trace_ubwcp_init_buffer_end(dmabuf);
  513. return -ENOMEM;
  514. }
  515. mutex_init(&buf->lock);
  516. buf->dma_buf = dmabuf;
  517. buf->ubwcp = ubwcp;
  518. buf->buf_attr.image_format = UBWCP_LINEAR;
  519. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  520. hash_add(ubwcp->buf_table, &buf->hnode, (u64)buf->dma_buf);
  521. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  522. trace_ubwcp_init_buffer_end(dmabuf);
  523. return 0;
  524. }
  525. static void dump_attributes(struct ubwcp_buffer_attrs *attr)
  526. {
  527. DBG_BUF_ATTR("");
  528. DBG_BUF_ATTR("image_format: %d", attr->image_format);
  529. DBG_BUF_ATTR("major_ubwc_ver: %d", attr->major_ubwc_ver);
  530. DBG_BUF_ATTR("minor_ubwc_ver: %d", attr->minor_ubwc_ver);
  531. DBG_BUF_ATTR("compression_type: %d", attr->compression_type);
  532. DBG_BUF_ATTR("lossy_params: %llu", attr->lossy_params);
  533. DBG_BUF_ATTR("width: %d", attr->width);
  534. DBG_BUF_ATTR("height: %d", attr->height);
  535. DBG_BUF_ATTR("stride: %d", attr->stride);
  536. DBG_BUF_ATTR("scanlines: %d", attr->scanlines);
  537. DBG_BUF_ATTR("planar_padding: %d", attr->planar_padding);
  538. DBG_BUF_ATTR("subsample: %d", attr->subsample);
  539. DBG_BUF_ATTR("sub_system_target: %d", attr->sub_system_target);
  540. DBG_BUF_ATTR("y_offset: %d", attr->y_offset);
  541. DBG_BUF_ATTR("batch_size: %d", attr->batch_size);
  542. DBG_BUF_ATTR("");
  543. }
  544. static enum ubwcp_std_image_format to_std_format(u16 ioctl_image_format)
  545. {
  546. switch (ioctl_image_format) {
  547. case UBWCP_RGBA8888:
  548. return RGBA;
  549. case UBWCP_NV12:
  550. case UBWCP_NV12_Y:
  551. case UBWCP_NV12_UV:
  552. return NV12;
  553. case UBWCP_NV124R:
  554. case UBWCP_NV124R_Y:
  555. case UBWCP_NV124R_UV:
  556. return NV124R;
  557. case UBWCP_TP10:
  558. case UBWCP_TP10_Y:
  559. case UBWCP_TP10_UV:
  560. return TP10;
  561. case UBWCP_P010:
  562. case UBWCP_P010_Y:
  563. case UBWCP_P010_UV:
  564. return P010;
  565. case UBWCP_P016:
  566. case UBWCP_P016_Y:
  567. case UBWCP_P016_UV:
  568. return P016;
  569. default:
  570. WARN(1, "Fix this!!!");
  571. return STD_IMAGE_FORMAT_INVALID;
  572. }
  573. }
  574. static int get_stride_alignment(enum ubwcp_std_image_format format, u16 *align)
  575. {
  576. switch (format) {
  577. case TP10:
  578. *align = 64;
  579. return 0;
  580. case NV12:
  581. *align = 128;
  582. return 0;
  583. case RGBA:
  584. case NV124R:
  585. case P010:
  586. case P016:
  587. *align = 256;
  588. return 0;
  589. default:
  590. return -1;
  591. }
  592. }
  593. /* returns stride of compressed image */
  594. static u32 get_compressed_stride(struct ubwcp_driver *ubwcp,
  595. enum ubwcp_std_image_format format, u32 width)
  596. {
  597. struct ubwcp_plane_info p_info;
  598. u16 macro_tile_width_p;
  599. u16 pixel_bytes;
  600. u16 per_pixel;
  601. p_info = ubwcp->format_info[format].p_info[0];
  602. macro_tile_width_p = p_info.macrotilesize_p.width;
  603. pixel_bytes = p_info.pixel_bytes;
  604. per_pixel = p_info.per_pixel;
  605. return UBWCP_ALIGN(width, macro_tile_width_p)*pixel_bytes/per_pixel;
  606. }
  607. /* check if linear stride conforms to hw limitations
  608. * always returns false for linear image
  609. */
  610. static bool stride_is_valid(struct ubwcp_driver *ubwcp,
  611. u16 ioctl_img_fmt, u32 width, u32 lin_stride)
  612. {
  613. u32 compressed_stride;
  614. enum ubwcp_std_image_format format = to_std_format(ioctl_img_fmt);
  615. if (format == STD_IMAGE_FORMAT_INVALID)
  616. return false;
  617. if ((lin_stride < width) || (lin_stride > 64*1024)) {
  618. ERR("stride is not valid (width <= stride <= 64K): %d", lin_stride);
  619. return false;
  620. }
  621. if (format == TP10) {
  622. if(!IS_ALIGNED(lin_stride, 64)) {
  623. ERR("stride must be aligned to 64: %d", lin_stride);
  624. return false;
  625. }
  626. } else {
  627. compressed_stride = get_compressed_stride(ubwcp, format, width);
  628. if (lin_stride != compressed_stride) {
  629. ERR("linear stride: %d must be same as compressed stride: %d",
  630. lin_stride, compressed_stride);
  631. return false;
  632. }
  633. }
  634. return true;
  635. }
  636. static bool ioctl_format_is_valid(u16 ioctl_image_format)
  637. {
  638. switch (ioctl_image_format) {
  639. case UBWCP_LINEAR:
  640. case UBWCP_RGBA8888:
  641. case UBWCP_NV12:
  642. case UBWCP_NV12_Y:
  643. case UBWCP_NV12_UV:
  644. case UBWCP_NV124R:
  645. case UBWCP_NV124R_Y:
  646. case UBWCP_NV124R_UV:
  647. case UBWCP_TP10:
  648. case UBWCP_TP10_Y:
  649. case UBWCP_TP10_UV:
  650. case UBWCP_P010:
  651. case UBWCP_P010_Y:
  652. case UBWCP_P010_UV:
  653. case UBWCP_P016:
  654. case UBWCP_P016_Y:
  655. case UBWCP_P016_UV:
  656. return true;
  657. default:
  658. return false;
  659. }
  660. }
  661. /* validate buffer attributes */
  662. static bool ubwcp_buf_attrs_valid(struct ubwcp_driver *ubwcp, struct ubwcp_buffer_attrs *attr)
  663. {
  664. if (!ioctl_format_is_valid(attr->image_format)) {
  665. ERR("invalid image format: %d", attr->image_format);
  666. goto err;
  667. }
  668. if (attr->major_ubwc_ver || attr->minor_ubwc_ver) {
  669. ERR("major/minor ubwc ver must be 0. major: %d minor: %d",
  670. attr->major_ubwc_ver, attr->minor_ubwc_ver);
  671. goto err;
  672. }
  673. if (attr->compression_type != UBWCP_COMPRESSION_LOSSLESS) {
  674. ERR("compression_type is not valid: %d",
  675. attr->compression_type);
  676. goto err;
  677. }
  678. if (attr->lossy_params != 0) {
  679. ERR("lossy_params is not valid: %d", attr->lossy_params);
  680. goto err;
  681. }
  682. //TBD: some upper limit for width?
  683. if (attr->width > 10*1024) {
  684. ERR("width is invalid (above upper limit): %d", attr->width);
  685. goto err;
  686. }
  687. //TBD: some upper limit for height?
  688. if (attr->height > 10*1024) {
  689. ERR("height is invalid (above upper limit): %d", attr->height);
  690. goto err;
  691. }
  692. if (attr->image_format != UBWCP_LINEAR)
  693. if(!stride_is_valid(ubwcp, attr->image_format, attr->width, attr->stride)) {
  694. ERR("stride is invalid: %d", attr->stride);
  695. goto err;
  696. }
  697. if ((attr->scanlines < attr->height) ||
  698. (attr->scanlines > attr->height + 32*1024)) {
  699. ERR("scanlines is not valid - height: %d scanlines: %d",
  700. attr->height, attr->scanlines);
  701. goto err;
  702. }
  703. if (attr->planar_padding > 4096) {
  704. ERR("planar_padding is not valid. (<= 4096): %d",
  705. attr->planar_padding);
  706. goto err;
  707. }
  708. if (attr->subsample != UBWCP_SUBSAMPLE_4_2_0) {
  709. ERR("subsample is not valid: %d", attr->subsample);
  710. goto err;
  711. }
  712. if (attr->sub_system_target & ~UBWCP_SUBSYSTEM_TARGET_CPU) {
  713. ERR("sub_system_target other that CPU is not supported: %d",
  714. attr->sub_system_target);
  715. goto err;
  716. }
  717. if (!(attr->sub_system_target & UBWCP_SUBSYSTEM_TARGET_CPU)) {
  718. ERR("sub_system_target is not set to CPU: %d",
  719. attr->sub_system_target);
  720. goto err;
  721. }
  722. if (attr->y_offset != 0) {
  723. ERR("y_offset is not valid: %d", attr->y_offset);
  724. goto err;
  725. }
  726. if (attr->batch_size != 1) {
  727. ERR("batch_size is not valid: %d", attr->batch_size);
  728. goto err;
  729. }
  730. dump_attributes(attr);
  731. return true;
  732. err:
  733. dump_attributes(attr);
  734. return false;
  735. }
  736. /* calculate and return metadata buffer size for a given plane
  737. * and buffer attributes
  738. * NOTE: in this function, we will only pass in NV12 format.
  739. * NOT NV12_Y or NV12_UV etc.
  740. * the Y or UV information is in the "plane"
  741. * "format" here purely means "encoding format" and no information
  742. * if some plane data is missing.
  743. */
  744. static size_t metadata_buf_sz(struct ubwcp_driver *ubwcp,
  745. enum ubwcp_std_image_format format,
  746. u32 width, u32 height, u8 plane)
  747. {
  748. size_t size;
  749. u64 pitch;
  750. u64 lines;
  751. u64 tile_width;
  752. u32 tile_height;
  753. struct ubwcp_image_format_info f_info;
  754. struct ubwcp_plane_info p_info;
  755. f_info = ubwcp->format_info[format];
  756. DBG_BUF_ATTR("");
  757. DBG_BUF_ATTR("");
  758. DBG_BUF_ATTR("Calculating metadata buffer size: format = %d, plane = %d", format, plane);
  759. if (plane >= f_info.planes) {
  760. ERR("Format does not have requested plane info: format: %d, plane: %d",
  761. format, plane);
  762. WARN(1, "Fix this!!!!!");
  763. return 0;
  764. }
  765. p_info = f_info.p_info[plane];
  766. /* UV plane */
  767. if (plane == 1) {
  768. width = width/2;
  769. height = height/2;
  770. }
  771. tile_width = p_info.tilesize_p.width;
  772. tile_height = p_info.tilesize_p.height;
  773. /* pitch: # of tiles in a row
  774. * lines: # of tile rows
  775. */
  776. pitch = UBWCP_ALIGN((width + tile_width - 1)/tile_width, META_DATA_PITCH_ALIGN);
  777. lines = UBWCP_ALIGN((height + tile_height - 1)/tile_height, META_DATA_HEIGHT_ALIGN);
  778. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  779. DBG_BUF_ATTR("tile params : %d x %d (pixels)", tile_width, tile_height);
  780. DBG_BUF_ATTR("pitch : %d (%d)", pitch, width/tile_width);
  781. DBG_BUF_ATTR("lines : %d (%d)", lines, height);
  782. DBG_BUF_ATTR("size (p*l*bytes) : %d", pitch*lines*1);
  783. /* x1 below is only to clarify that we are multiplying by 1 bytes/tile */
  784. size = UBWCP_ALIGN(pitch*lines*1, META_DATA_SIZE_ALIGN);
  785. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  786. return size;
  787. }
  788. /* calculate and return size of pixel data buffer for a given plane
  789. * and buffer attributes
  790. */
  791. static size_t pixeldata_buf_sz(struct ubwcp_driver *ubwcp,
  792. u16 format, u32 width,
  793. u32 height, u8 plane)
  794. {
  795. size_t size;
  796. u64 pitch;
  797. u64 lines;
  798. u16 pixel_bytes;
  799. u16 per_pixel;
  800. u64 macro_tile_width_p;
  801. u64 macro_tile_height_p;
  802. struct ubwcp_image_format_info f_info;
  803. struct ubwcp_plane_info p_info;
  804. f_info = ubwcp->format_info[format];
  805. DBG_BUF_ATTR("");
  806. DBG_BUF_ATTR("");
  807. DBG_BUF_ATTR("Calculating Pixeldata buffer size: format = %d, plane = %d", format, plane);
  808. if (plane >= f_info.planes) {
  809. ERR("Format does not have requested plane info: format: %d, plane: %d",
  810. format, plane);
  811. WARN(1, "Fix this!!!!!");
  812. return 0;
  813. }
  814. p_info = f_info.p_info[plane];
  815. pixel_bytes = p_info.pixel_bytes;
  816. per_pixel = p_info.per_pixel;
  817. /* UV plane */
  818. if (plane == 1) {
  819. width = width/2;
  820. height = height/2;
  821. }
  822. macro_tile_width_p = p_info.macrotilesize_p.width;
  823. macro_tile_height_p = p_info.macrotilesize_p.height;
  824. /* align pixel width and height macro tile width and height */
  825. pitch = UBWCP_ALIGN(width, macro_tile_width_p);
  826. lines = UBWCP_ALIGN(height, macro_tile_height_p);
  827. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  828. DBG_BUF_ATTR("macro tile params: %d x %d (pixels)", macro_tile_width_p,
  829. macro_tile_height_p);
  830. DBG_BUF_ATTR("bytes_per_pixel : %d/%d", pixel_bytes, per_pixel);
  831. DBG_BUF_ATTR("pitch : %d", pitch);
  832. DBG_BUF_ATTR("lines : %d", lines);
  833. DBG_BUF_ATTR("size (p*l*bytes) : %d", (pitch*lines*pixel_bytes)/per_pixel);
  834. size = UBWCP_ALIGN((pitch*lines*pixel_bytes)/per_pixel, PIXEL_DATA_SIZE_ALIGN);
  835. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  836. return size;
  837. }
  838. static int get_tile_height(struct ubwcp_driver *ubwcp, enum ubwcp_std_image_format format,
  839. u8 plane)
  840. {
  841. struct ubwcp_image_format_info f_info;
  842. struct ubwcp_plane_info p_info;
  843. f_info = ubwcp->format_info[format];
  844. p_info = f_info.p_info[plane];
  845. return p_info.tilesize_p.height;
  846. }
  847. /*
  848. * plane: must be 0 or 1 (1st plane == 0, 2nd plane == 1)
  849. */
  850. static size_t ubwcp_ula_size(struct ubwcp_driver *ubwcp, u16 format,
  851. u32 stride_b, u32 scanlines, u8 plane,
  852. bool add_tile_pad)
  853. {
  854. size_t size;
  855. DBG_BUF_ATTR("%s(format = %d, plane = %d)", __func__, format, plane);
  856. /* UV plane */
  857. if (plane == 1)
  858. scanlines = scanlines/2;
  859. if (add_tile_pad) {
  860. int tile_height = get_tile_height(ubwcp, format, plane);
  861. /* Align plane size to plane tile height */
  862. scanlines = ((scanlines + tile_height - 1) / tile_height) * tile_height;
  863. }
  864. size = stride_b*scanlines;
  865. DBG_BUF_ATTR("Size of plane-%u: (%u * %u) = %zu (0x%zx)",
  866. plane, stride_b, scanlines, size, size);
  867. return size;
  868. }
  869. static int missing_plane_from_format(u16 ioctl_image_format)
  870. {
  871. int missing_plane;
  872. switch (ioctl_image_format) {
  873. case UBWCP_NV12_Y:
  874. missing_plane = 2;
  875. break;
  876. case UBWCP_NV12_UV:
  877. missing_plane = 1;
  878. break;
  879. case UBWCP_NV124R_Y:
  880. missing_plane = 2;
  881. break;
  882. case UBWCP_NV124R_UV:
  883. missing_plane = 1;
  884. break;
  885. case UBWCP_TP10_Y:
  886. missing_plane = 2;
  887. break;
  888. case UBWCP_TP10_UV:
  889. missing_plane = 1;
  890. break;
  891. case UBWCP_P010_Y:
  892. missing_plane = 2;
  893. break;
  894. case UBWCP_P010_UV:
  895. missing_plane = 1;
  896. break;
  897. case UBWCP_P016_Y:
  898. missing_plane = 2;
  899. break;
  900. case UBWCP_P016_UV:
  901. missing_plane = 1;
  902. break;
  903. default:
  904. missing_plane = 0;
  905. }
  906. return missing_plane;
  907. }
  908. static int planes_in_format(enum ubwcp_std_image_format format)
  909. {
  910. if (format == RGBA)
  911. return 1;
  912. else
  913. return 2;
  914. }
  915. static unsigned int ubwcp_get_hw_image_format_value(u16 ioctl_image_format)
  916. {
  917. enum ubwcp_std_image_format format;
  918. format = to_std_format(ioctl_image_format);
  919. switch (format) {
  920. case RGBA:
  921. return HW_BUFFER_FORMAT_RGBA;
  922. case NV12:
  923. return HW_BUFFER_FORMAT_NV12;
  924. case NV124R:
  925. return HW_BUFFER_FORMAT_NV124R;
  926. case P010:
  927. return HW_BUFFER_FORMAT_P010;
  928. case TP10:
  929. return HW_BUFFER_FORMAT_TP10;
  930. case P016:
  931. return HW_BUFFER_FORMAT_P016;
  932. default:
  933. WARN(1, "Fix this!!!!!");
  934. return 0;
  935. }
  936. }
  937. static int ubwcp_validate_uv_align(struct ubwcp_driver *ubwcp,
  938. struct ubwcp_buffer_attrs *attr,
  939. size_t ula_y_plane_size,
  940. size_t uv_start_offset)
  941. {
  942. int ret = 0;
  943. size_t ula_y_plane_size_align;
  944. size_t y_tile_align_bytes;
  945. int y_tile_height;
  946. int planes;
  947. /* Only validate UV align if there is both a Y and UV plane */
  948. planes = planes_in_format(to_std_format(attr->image_format));
  949. if (planes != 2)
  950. return 0;
  951. /* Check it is cache line size aligned */
  952. if ((uv_start_offset % 64) != 0) {
  953. ret = -EINVAL;
  954. ERR("uv_start_offset %zu not cache line aligned",
  955. uv_start_offset);
  956. goto err;
  957. }
  958. /*
  959. * Check that UV plane does not overlap with any of the Y plane’s tiles
  960. */
  961. y_tile_height = get_tile_height(ubwcp, to_std_format(attr->image_format), 0);
  962. y_tile_align_bytes = y_tile_height * attr->stride;
  963. ula_y_plane_size_align = ((ula_y_plane_size + y_tile_align_bytes - 1) /
  964. y_tile_align_bytes) * y_tile_align_bytes;
  965. if (uv_start_offset < ula_y_plane_size_align) {
  966. ret = -EINVAL;
  967. ERR("uv offset %zu less than y plane align %zu for y plane size %zu",
  968. uv_start_offset, ula_y_plane_size_align,
  969. ula_y_plane_size);
  970. goto err;
  971. }
  972. return 0;
  973. err:
  974. return ret;
  975. }
  976. /* calculate ULA buffer parms */
  977. static int ubwcp_calc_ula_params(struct ubwcp_driver *ubwcp,
  978. struct ubwcp_buffer_attrs *attr,
  979. size_t *ula_size,
  980. size_t *ula_y_plane_size,
  981. size_t *uv_start_offset)
  982. {
  983. size_t size;
  984. enum ubwcp_std_image_format format;
  985. int planes;
  986. int missing_plane;
  987. u32 stride;
  988. u32 scanlines;
  989. u32 planar_padding;
  990. stride = attr->stride;
  991. scanlines = attr->scanlines;
  992. planar_padding = attr->planar_padding;
  993. /* convert ioctl image format to standard image format */
  994. format = to_std_format(attr->image_format);
  995. /* Number of "expected" planes in "the standard defined" image format */
  996. planes = planes_in_format(format);
  997. /* any plane missing?
  998. * valid missing_plane values:
  999. * 0 == no plane missing
  1000. * 1 == 1st plane missing
  1001. * 2 == 2nd plane missing
  1002. */
  1003. missing_plane = missing_plane_from_format(attr->image_format);
  1004. DBG_BUF_ATTR("ula params -->");
  1005. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1006. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1007. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1008. DBG_BUF_ATTR("Planar Padding : %d", planar_padding);
  1009. if (planes == 1) {
  1010. /* uv_start beyond ULA range */
  1011. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1012. *uv_start_offset = size;
  1013. *ula_y_plane_size = size;
  1014. } else {
  1015. if (!missing_plane) {
  1016. /* size for both planes and padding */
  1017. /* Don't pad out Y plane as client would not expect this padding */
  1018. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, false);
  1019. *ula_y_plane_size = size;
  1020. size += planar_padding;
  1021. *uv_start_offset = size;
  1022. size += ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1023. } else {
  1024. if (missing_plane == 2) {
  1025. /* Y-only image, set uv_start beyond ULA range */
  1026. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1027. *uv_start_offset = size;
  1028. *ula_y_plane_size = size;
  1029. } else {
  1030. /* first plane data is not there */
  1031. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1032. *uv_start_offset = 0; /* uv data is at the beginning */
  1033. *ula_y_plane_size = 0;
  1034. }
  1035. }
  1036. }
  1037. *ula_size = UBWCP_ALIGN(size, 4096);
  1038. DBG_BUF_ATTR("ULA_Size: %zu (0x%x) (before 4K align: %zu)", *ula_size, *ula_size, size);
  1039. return 0;
  1040. }
  1041. /* calculate UBWCP buffer parms */
  1042. static int ubwcp_calc_ubwcp_buf_params(struct ubwcp_driver *ubwcp,
  1043. struct ubwcp_buffer_attrs *attr,
  1044. size_t *md_p0, size_t *pd_p0,
  1045. size_t *md_p1, size_t *pd_p1,
  1046. size_t *stride_tp10_b)
  1047. {
  1048. int planes;
  1049. int missing_plane;
  1050. enum ubwcp_std_image_format format;
  1051. size_t stride_tp10_p;
  1052. FENTRY();
  1053. /* convert ioctl image format to standard image format */
  1054. format = to_std_format(attr->image_format);
  1055. missing_plane = missing_plane_from_format(attr->image_format);
  1056. planes = planes_in_format(format);
  1057. DBG_BUF_ATTR("ubwcp params -->");
  1058. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1059. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1060. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1061. *md_p0 = 0;
  1062. *pd_p0 = 0;
  1063. *md_p1 = 0;
  1064. *pd_p1 = 0;
  1065. *stride_tp10_b = 0;
  1066. if (!missing_plane) {
  1067. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1068. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1069. if (planes == 2) {
  1070. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1071. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1072. }
  1073. } else {
  1074. if (missing_plane == 1) {
  1075. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1076. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1077. } else {
  1078. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1079. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1080. }
  1081. }
  1082. if (format == TP10) {
  1083. stride_tp10_p = UBWCP_ALIGN(attr->width, 192);
  1084. *stride_tp10_b = (stride_tp10_p/3) + stride_tp10_p;
  1085. }
  1086. return 0;
  1087. }
  1088. /* reserve ULA address space of the given size */
  1089. static phys_addr_t ubwcp_ula_alloc(struct ubwcp_driver *ubwcp, size_t size)
  1090. {
  1091. phys_addr_t pa;
  1092. mutex_lock(&ubwcp->ula_lock);
  1093. pa = gen_pool_alloc(ubwcp->ula_pool, size);
  1094. DBG("addr: %p, size: %zx", pa, size);
  1095. mutex_unlock(&ubwcp->ula_lock);
  1096. return pa;
  1097. }
  1098. /* free ULA address space of the given address and size */
  1099. static void ubwcp_ula_free(struct ubwcp_driver *ubwcp, phys_addr_t pa, size_t size)
  1100. {
  1101. mutex_lock(&ubwcp->ula_lock);
  1102. if (!gen_pool_has_addr(ubwcp->ula_pool, pa, size)) {
  1103. ERR("Attempt to free mem not from gen_pool: pa: %p, size: %zx", pa, size);
  1104. goto err;
  1105. }
  1106. DBG("addr: %p, size: %zx", pa, size);
  1107. gen_pool_free(ubwcp->ula_pool, pa, size);
  1108. mutex_unlock(&ubwcp->ula_lock);
  1109. return;
  1110. err:
  1111. mutex_unlock(&ubwcp->ula_lock);
  1112. }
  1113. /* free up or expand current_pa and return the new pa */
  1114. static phys_addr_t ubwcp_ula_realloc(struct ubwcp_driver *ubwcp,
  1115. phys_addr_t pa,
  1116. size_t size,
  1117. size_t new_size)
  1118. {
  1119. if (size == new_size)
  1120. return pa;
  1121. if (pa)
  1122. ubwcp_ula_free(ubwcp, pa, size);
  1123. return ubwcp_ula_alloc(ubwcp, new_size);
  1124. }
  1125. /* unmap dma buf */
  1126. static void ubwcp_dma_unmap(struct ubwcp_buf *buf)
  1127. {
  1128. FENTRY();
  1129. if (buf->dma_buf && buf->attachment) {
  1130. DBG("Calling dma_buf_unmap_attachment()");
  1131. dma_buf_unmap_attachment(buf->attachment, buf->sgt, DMA_BIDIRECTIONAL);
  1132. buf->sgt = NULL;
  1133. dma_buf_detach(buf->dma_buf, buf->attachment);
  1134. buf->attachment = NULL;
  1135. }
  1136. }
  1137. static bool verify_dma_buf_size(struct ubwcp_buf *buf, size_t min_size)
  1138. {
  1139. size_t dma_len;
  1140. dma_len = sg_dma_len(buf->sgt->sgl);
  1141. if (dma_len < min_size) {
  1142. ERR("dma len: %zu is less than min ubwcp buffer size: %zu", dma_len, min_size);
  1143. return false;
  1144. } else
  1145. return true;
  1146. }
  1147. /* dma map ubwcp buffer */
  1148. static int ubwcp_dma_map(struct ubwcp_buf *buf,
  1149. struct device *dev,
  1150. dma_addr_t *iova)
  1151. {
  1152. int ret = 0;
  1153. struct dma_buf *dma_buf = buf->dma_buf;
  1154. struct dma_buf_attachment *attachment;
  1155. struct sg_table *sgt;
  1156. /* Map buffer to SMMU and get IOVA */
  1157. attachment = dma_buf_attach(dma_buf, dev);
  1158. if (IS_ERR(attachment)) {
  1159. ret = PTR_ERR(attachment);
  1160. ERR("dma_buf_attach() failed: %d", ret);
  1161. goto err;
  1162. }
  1163. dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
  1164. dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64));
  1165. sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL);
  1166. if (IS_ERR_OR_NULL(sgt)) {
  1167. ret = PTR_ERR(sgt);
  1168. ERR("dma_buf_map_attachment() failed: %d", ret);
  1169. goto err_detach;
  1170. }
  1171. if (sgt->nents != 1) {
  1172. ERR("nents = %d", sgt->nents);
  1173. goto err_unmap;
  1174. }
  1175. *iova = sg_dma_address(sgt->sgl);
  1176. buf->attachment = attachment;
  1177. buf->sgt = sgt;
  1178. return ret;
  1179. err_unmap:
  1180. dma_buf_unmap_attachment(attachment, sgt, DMA_BIDIRECTIONAL);
  1181. err_detach:
  1182. dma_buf_detach(dma_buf, attachment);
  1183. err:
  1184. if (!ret)
  1185. ret = -1;
  1186. return ret;
  1187. }
  1188. static void
  1189. ubwcp_pixel_to_bytes(struct ubwcp_driver *ubwcp,
  1190. enum ubwcp_std_image_format format,
  1191. u32 width_p, u32 height_p,
  1192. u32 *width_b, u32 *height_b)
  1193. {
  1194. u16 pixel_bytes;
  1195. u16 per_pixel;
  1196. struct ubwcp_image_format_info f_info;
  1197. struct ubwcp_plane_info p_info;
  1198. f_info = ubwcp->format_info[format];
  1199. p_info = f_info.p_info[0];
  1200. pixel_bytes = p_info.pixel_bytes;
  1201. per_pixel = p_info.per_pixel;
  1202. *width_b = (width_p*pixel_bytes)/per_pixel;
  1203. *height_b = (height_p*pixel_bytes)/per_pixel;
  1204. }
  1205. static void reset_buf_attrs(struct ubwcp_buf *buf)
  1206. {
  1207. struct ubwcp_hw_meta_metadata *mmdata;
  1208. struct ubwcp_driver *ubwcp;
  1209. ubwcp = buf->ubwcp;
  1210. mmdata = &buf->mmdata;
  1211. ubwcp_dma_unmap(buf);
  1212. /* reset ula params */
  1213. if (buf->ula_size) {
  1214. ubwcp_ula_free(ubwcp, buf->ula_pa, buf->ula_size);
  1215. buf->ula_size = 0;
  1216. buf->ula_pa = 0;
  1217. }
  1218. /* reset ubwcp params */
  1219. memset(mmdata, 0, sizeof(*mmdata));
  1220. buf->buf_attr_set = false;
  1221. buf->buf_attr.image_format = UBWCP_LINEAR;
  1222. }
  1223. static void print_mmdata_desc(struct ubwcp_hw_meta_metadata *mmdata)
  1224. {
  1225. DBG_BUF_ATTR("");
  1226. DBG_BUF_ATTR("--------MM_DATA DESC ---------");
  1227. DBG_BUF_ATTR("uv_start_addr : 0x%08llx (cache addr) (actual: 0x%llx)",
  1228. mmdata->uv_start_addr, mmdata->uv_start_addr << 6);
  1229. DBG_BUF_ATTR("format : 0x%08x", mmdata->format);
  1230. DBG_BUF_ATTR("stride : 0x%08x (cache addr) (actual: 0x%x)",
  1231. mmdata->stride, mmdata->stride << 6);
  1232. DBG_BUF_ATTR("stride_ubwcp : 0x%08x (cache addr) (actual: 0x%zx)",
  1233. mmdata->stride_ubwcp, mmdata->stride_ubwcp << 6);
  1234. DBG_BUF_ATTR("metadata_base_y : 0x%08x (page addr) (actual: 0x%llx)",
  1235. mmdata->metadata_base_y, mmdata->metadata_base_y << 12);
  1236. DBG_BUF_ATTR("metadata_base_uv: 0x%08x (page addr) (actual: 0x%zx)",
  1237. mmdata->metadata_base_uv, mmdata->metadata_base_uv << 12);
  1238. DBG_BUF_ATTR("buffer_y_offset : 0x%08x (page addr) (actual: 0x%zx)",
  1239. mmdata->buffer_y_offset, mmdata->buffer_y_offset << 12);
  1240. DBG_BUF_ATTR("buffer_uv_offset: 0x%08x (page addr) (actual: 0x%zx)",
  1241. mmdata->buffer_uv_offset, mmdata->buffer_uv_offset << 12);
  1242. DBG_BUF_ATTR("width_height : 0x%08x (width: 0x%x height: 0x%x)",
  1243. mmdata->width_height, mmdata->width_height >> 16, mmdata->width_height & 0xFFFF);
  1244. DBG_BUF_ATTR("");
  1245. }
  1246. /* set buffer attributes:
  1247. * Failure:
  1248. * This call may fail for multiple reasons and it will leave the buffer in an undefined state.
  1249. * In some situations it may leave the buffer in linear mapped state, and in other situations it
  1250. * may leave the buffer in previously set attributes state.
  1251. */
  1252. int ubwcp_set_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1253. {
  1254. int ret = 0;
  1255. size_t ula_size = 0;
  1256. size_t uv_start_offset = 0;
  1257. size_t ula_y_plane_size = 0;
  1258. phys_addr_t ula_pa = 0x0;
  1259. struct ubwcp_buf *buf;
  1260. struct ubwcp_driver *ubwcp;
  1261. size_t metadata_p0;
  1262. size_t pixeldata_p0;
  1263. size_t metadata_p1;
  1264. size_t pixeldata_p1;
  1265. size_t iova_min_size;
  1266. size_t stride_tp10_b;
  1267. dma_addr_t iova_base;
  1268. struct ubwcp_hw_meta_metadata *mmdata;
  1269. u64 uv_start;
  1270. u32 stride_b;
  1271. u32 width_b;
  1272. u32 height_b;
  1273. enum ubwcp_std_image_format std_image_format;
  1274. bool is_non_lin_buf;
  1275. FENTRY();
  1276. trace_ubwcp_set_buf_attrs_start(dmabuf);
  1277. if (!dmabuf) {
  1278. ERR("NULL dmabuf input ptr");
  1279. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1280. return -EINVAL;
  1281. }
  1282. if (!attr) {
  1283. ERR("NULL attr ptr");
  1284. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1285. return -EINVAL;
  1286. }
  1287. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1288. if (!buf) {
  1289. ERR("No corresponding ubwcp_buf for the passed in dma_buf");
  1290. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1291. return -EINVAL;
  1292. }
  1293. ubwcp = buf->ubwcp;
  1294. if (ubwcp->state != UBWCP_STATE_READY)
  1295. return -EPERM;
  1296. mutex_lock(&buf->lock);
  1297. if (buf->lock_count) {
  1298. ERR("Cannot set attr when buffer is locked");
  1299. ret = -EBUSY;
  1300. goto unlock;
  1301. }
  1302. mmdata = &buf->mmdata;
  1303. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1304. if (!ubwcp_buf_attrs_valid(ubwcp, attr)) {
  1305. ERR("Invalid buf attrs");
  1306. goto unlock;
  1307. }
  1308. /* note: this also checks if buf is mmap'ed */
  1309. ret = ubwcp->mmap_config_fptr(buf->dma_buf, true, 0, 0);
  1310. if (ret) {
  1311. ERR("dma_buf_mmap_config(0,0) failed: %d", ret);
  1312. goto unlock;
  1313. }
  1314. if (attr->image_format == UBWCP_LINEAR) {
  1315. DBG_BUF_ATTR("Linear format requested");
  1316. if (buf->buf_attr_set)
  1317. reset_buf_attrs(buf);
  1318. if (is_non_lin_buf) {
  1319. /*
  1320. * Changing buffer from ubwc to linear so decrement
  1321. * number of ubwc buffers
  1322. */
  1323. ret = dec_num_non_lin_buffers(ubwcp);
  1324. }
  1325. mutex_unlock(&buf->lock);
  1326. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1327. return ret;
  1328. }
  1329. std_image_format = to_std_format(attr->image_format);
  1330. if (std_image_format == STD_IMAGE_FORMAT_INVALID) {
  1331. ERR("Unable to map ioctl image format to std image format");
  1332. goto unlock;
  1333. }
  1334. /* Calculate uncompressed-buffer size. */
  1335. ret = ubwcp_calc_ula_params(ubwcp, attr, &ula_size, &ula_y_plane_size, &uv_start_offset);
  1336. if (ret) {
  1337. ERR("ubwcp_calc_ula_params() failed: %d", ret);
  1338. goto unlock;
  1339. }
  1340. ret = ubwcp_validate_uv_align(ubwcp, attr, ula_y_plane_size, uv_start_offset);
  1341. if (ret) {
  1342. ERR("ubwcp_validate_uv_align() failed: %d", ret);
  1343. goto unlock;
  1344. }
  1345. ret = ubwcp_calc_ubwcp_buf_params(ubwcp, attr, &metadata_p0, &pixeldata_p0, &metadata_p1,
  1346. &pixeldata_p1, &stride_tp10_b);
  1347. if (ret) {
  1348. ERR("ubwcp_calc_buf_params() failed: %d", ret);
  1349. goto unlock;
  1350. }
  1351. iova_min_size = metadata_p0 + pixeldata_p0 + metadata_p1 + pixeldata_p1;
  1352. DBG_BUF_ATTR("");
  1353. DBG_BUF_ATTR("");
  1354. DBG_BUF_ATTR("------Summary ULA Calculated Params ------");
  1355. DBG_BUF_ATTR("ULA Size : %8zu (0x%8zx)", ula_size, ula_size);
  1356. DBG_BUF_ATTR("UV Start Offset : %8zu (0x%8zx)", uv_start_offset, uv_start_offset);
  1357. DBG_BUF_ATTR("------Summary UBCP Calculated Params ------");
  1358. DBG_BUF_ATTR("metadata_p0 : %8d (0x%8zx)", metadata_p0, metadata_p0);
  1359. DBG_BUF_ATTR("pixeldata_p0 : %8d (0x%8zx)", pixeldata_p0, pixeldata_p0);
  1360. DBG_BUF_ATTR("metadata_p1 : %8d (0x%8zx)", metadata_p1, metadata_p1);
  1361. DBG_BUF_ATTR("pixeldata_p1 : %8d (0x%8zx)", pixeldata_p1, pixeldata_p1);
  1362. DBG_BUF_ATTR("stride_tp10 : %8d (0x%8zx)", stride_tp10_b, stride_tp10_b);
  1363. DBG_BUF_ATTR("iova_min_size : %8d (0x%8zx)", iova_min_size, iova_min_size);
  1364. DBG_BUF_ATTR("");
  1365. /* assign ULA PA with uncompressed-size range */
  1366. ula_pa = ubwcp_ula_realloc(ubwcp, buf->ula_pa, buf->ula_size, ula_size);
  1367. if (!ula_pa) {
  1368. ERR("ubwcp_ula_alloc/realloc() failed. running out of ULA PA space?");
  1369. goto err;
  1370. }
  1371. buf->ula_size = ula_size;
  1372. buf->ula_pa = ula_pa;
  1373. DBG_BUF_ATTR("Allocated ULA_PA: 0x%p of size: 0x%zx", ula_pa, ula_size);
  1374. DBG_BUF_ATTR("");
  1375. /* dma map only the first time attribute is set */
  1376. if (!buf->buf_attr_set) {
  1377. /* linear -> ubwcp. map ubwcp buffer */
  1378. ret = ubwcp_dma_map(buf, ubwcp->dev_buf_cb, &iova_base);
  1379. if (ret) {
  1380. ERR("ubwcp_dma_map() failed: %d", ret);
  1381. goto err;
  1382. }
  1383. DBG_BUF_ATTR("dma_buf IOVA range: 0x%llx + min_size (0x%zx): 0x%llx",
  1384. iova_base, iova_min_size, iova_base + iova_min_size);
  1385. }
  1386. if(!verify_dma_buf_size(buf, iova_min_size))
  1387. goto err;
  1388. uv_start = ula_pa + uv_start_offset;
  1389. if (!IS_ALIGNED(uv_start, 64)) {
  1390. ERR("ERROR: uv_start is NOT aligned to cache line");
  1391. goto err;
  1392. }
  1393. /* Convert height and width to bytes for writing to mmdata */
  1394. if (std_image_format != TP10) {
  1395. ubwcp_pixel_to_bytes(ubwcp, std_image_format, attr->width,
  1396. attr->height, &width_b, &height_b);
  1397. } else {
  1398. /* for tp10 image compression, we need to program p010 width/height */
  1399. ubwcp_pixel_to_bytes(ubwcp, P010, attr->width,
  1400. attr->height, &width_b, &height_b);
  1401. }
  1402. stride_b = attr->stride;
  1403. /* create the mmdata descriptor */
  1404. memset(mmdata, 0, sizeof(*mmdata));
  1405. mmdata->uv_start_addr = CACHE_ADDR(uv_start);
  1406. mmdata->format = ubwcp_get_hw_image_format_value(attr->image_format);
  1407. if (std_image_format != TP10) {
  1408. mmdata->stride = CACHE_ADDR(stride_b); /* uncompressed stride */
  1409. } else {
  1410. mmdata->stride = CACHE_ADDR(stride_tp10_b); /* compressed stride */
  1411. mmdata->stride_ubwcp = CACHE_ADDR(stride_b); /* uncompressed stride */
  1412. }
  1413. mmdata->metadata_base_y = PAGE_ADDR(iova_base);
  1414. mmdata->metadata_base_uv = PAGE_ADDR(iova_base + metadata_p0 + pixeldata_p0);
  1415. mmdata->buffer_y_offset = PAGE_ADDR(metadata_p0);
  1416. mmdata->buffer_uv_offset = PAGE_ADDR(metadata_p1);
  1417. /* NOTE: For version 1.1, both width & height needs to be in bytes.
  1418. * For other versions, width in bytes & height in pixels.
  1419. */
  1420. if ((ubwcp->hw_ver_major == 1) && (ubwcp->hw_ver_minor == 1))
  1421. mmdata->width_height = width_b << 16 | height_b;
  1422. else
  1423. mmdata->width_height = width_b << 16 | attr->height;
  1424. print_mmdata_desc(mmdata);
  1425. if (!is_non_lin_buf) {
  1426. /*
  1427. * Changing buffer from linear to ubwc so increment
  1428. * number of ubwc buffers
  1429. */
  1430. ret = inc_num_non_lin_buffers(ubwcp);
  1431. }
  1432. if (ret) {
  1433. ERR("inc_num_non_lin_buffers failed: %d", ret);
  1434. goto err;
  1435. }
  1436. /* inform ULA-PA to dma-heap */
  1437. DBG_BUF_ATTR("Calling mmap_config(): ULA_PA: 0x%p size: 0x%zx", ula_pa, ula_size);
  1438. ret = ubwcp->mmap_config_fptr(buf->dma_buf, false, buf->ula_pa, buf->ula_size);
  1439. if (ret) {
  1440. ERR("dma_buf_mmap_config() failed: %d", ret);
  1441. if (!is_non_lin_buf)
  1442. dec_num_non_lin_buffers(ubwcp);
  1443. goto err;
  1444. }
  1445. buf->buf_attr = *attr;
  1446. buf->buf_attr_set = true;
  1447. mutex_unlock(&buf->lock);
  1448. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1449. return 0;
  1450. err:
  1451. reset_buf_attrs(buf);
  1452. if (is_non_lin_buf) {
  1453. /*
  1454. * Changing buffer from ubwc to linear so decrement
  1455. * number of ubwc buffers
  1456. */
  1457. dec_num_non_lin_buffers(ubwcp);
  1458. }
  1459. unlock:
  1460. mutex_unlock(&buf->lock);
  1461. if (!ret)
  1462. ret = -1;
  1463. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1464. return ret;
  1465. }
  1466. EXPORT_SYMBOL(ubwcp_set_buf_attrs);
  1467. /* Set buffer attributes ioctl */
  1468. static int ubwcp_set_buf_attrs_ioctl(struct ubwcp_ioctl_buffer_attrs *attr_ioctl)
  1469. {
  1470. int ret;
  1471. struct dma_buf *dmabuf;
  1472. dmabuf = dma_buf_get(attr_ioctl->fd);
  1473. if (IS_ERR(dmabuf)) {
  1474. ERR("dmabuf ptr not found for dma_buf_fd = %d", dma_buf_fd);
  1475. return PTR_ERR(dmabuf);
  1476. }
  1477. ret = ubwcp_set_buf_attrs(dmabuf, &attr_ioctl->attr);
  1478. dma_buf_put(dmabuf);
  1479. return ret;
  1480. }
  1481. /* Free up the buffer descriptor */
  1482. static void ubwcp_buf_desc_free(struct ubwcp_driver *ubwcp, struct ubwcp_desc *desc)
  1483. {
  1484. int idx = desc->idx;
  1485. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1486. mutex_lock(&ubwcp->desc_lock);
  1487. desc_list[idx].idx = -1;
  1488. desc_list[idx].ptr = NULL;
  1489. DBG("freed descriptor_id: %d", idx);
  1490. mutex_unlock(&ubwcp->desc_lock);
  1491. }
  1492. /* Allocate next available buffer descriptor. */
  1493. static struct ubwcp_desc *ubwcp_buf_desc_allocate(struct ubwcp_driver *ubwcp)
  1494. {
  1495. int idx;
  1496. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1497. mutex_lock(&ubwcp->desc_lock);
  1498. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  1499. if (desc_list[idx].idx == -1) {
  1500. desc_list[idx].idx = idx;
  1501. desc_list[idx].ptr = ubwcp->buffer_desc_base +
  1502. idx*UBWCP_BUFFER_DESC_OFFSET;
  1503. DBG("allocated descriptor_id: %d", idx);
  1504. mutex_unlock(&ubwcp->desc_lock);
  1505. return &desc_list[idx];
  1506. }
  1507. }
  1508. mutex_unlock(&ubwcp->desc_lock);
  1509. return NULL;
  1510. }
  1511. static int ubwcp_flush(struct ubwcp_driver *ubwcp)
  1512. {
  1513. int ret = 0;
  1514. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1515. trace_ubwcp_hw_flush_start(0);
  1516. ret = ubwcp_hw_flush(ubwcp->base);
  1517. trace_ubwcp_hw_flush_end(0);
  1518. if (ret)
  1519. ERR("ubwcp_hw_flush() failed, ret = %d", ret);
  1520. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1521. return ret;
  1522. }
  1523. static int range_check_disable(struct ubwcp_driver *ubwcp, int idx)
  1524. {
  1525. int ret;
  1526. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1527. mutex_lock(&ubwcp->hw_range_ck_lock);
  1528. trace_ubwcp_hw_flush_start(0);
  1529. ret = ubwcp_hw_disable_range_check_with_flush(ubwcp->base, idx);
  1530. trace_ubwcp_hw_flush_end(0);
  1531. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1532. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1533. return ret;
  1534. }
  1535. static void range_check_enable(struct ubwcp_driver *ubwcp, int idx)
  1536. {
  1537. mutex_lock(&ubwcp->hw_range_ck_lock);
  1538. ubwcp_hw_enable_range_check(ubwcp->base, idx);
  1539. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1540. }
  1541. /**
  1542. * Lock buffer for CPU access. This prepares ubwcp hw to allow
  1543. * CPU access to the compressed buffer. It will perform
  1544. * necessary address translation configuration and cache maintenance ops
  1545. * so that CPU can safely access ubwcp buffer, if this call is
  1546. * successful.
  1547. * Allocate descriptor if not already,
  1548. * perform CMO and then enable range check
  1549. *
  1550. * @param dmabuf : ptr to the dma buf
  1551. * @param direction : direction of access
  1552. *
  1553. * @return int : 0 on success, otherwise error code
  1554. */
  1555. static int ubwcp_lock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1556. {
  1557. int ret = 0;
  1558. struct ubwcp_buf *buf;
  1559. struct ubwcp_driver *ubwcp;
  1560. FENTRY();
  1561. trace_ubwcp_lock_start(dmabuf);
  1562. if (!dmabuf) {
  1563. ERR("NULL dmabuf input ptr");
  1564. trace_ubwcp_lock_end(dmabuf);
  1565. return -EINVAL;
  1566. }
  1567. if (!valid_dma_direction(dir)) {
  1568. ERR("invalid direction: %d", dir);
  1569. trace_ubwcp_lock_end(dmabuf);
  1570. return -EINVAL;
  1571. }
  1572. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1573. if (!buf) {
  1574. ERR("ubwcp_buf ptr not found");
  1575. trace_ubwcp_lock_end(dmabuf);
  1576. return -1;
  1577. }
  1578. ubwcp = buf->ubwcp;
  1579. if (ubwcp->state != UBWCP_STATE_READY) {
  1580. ERR("driver in invalid state: %d", ubwcp->state);
  1581. trace_ubwcp_lock_end(dmabuf);
  1582. return -EPERM;
  1583. }
  1584. mutex_lock(&buf->lock);
  1585. if (!buf->buf_attr_set) {
  1586. ERR("lock() called on buffer, but attr not set");
  1587. goto err;
  1588. }
  1589. if (buf->buf_attr.image_format == UBWCP_LINEAR) {
  1590. ERR("lock() called on linear buffer");
  1591. goto err;
  1592. }
  1593. if (!buf->lock_count) {
  1594. DBG("first lock on buffer");
  1595. /* buf->desc could already be allocated because of perm range xlation */
  1596. if (!buf->desc) {
  1597. /* allocate a buffer descriptor */
  1598. buf->desc = ubwcp_buf_desc_allocate(buf->ubwcp);
  1599. if (!buf->desc) {
  1600. ERR("ubwcp_allocate_buf_desc() failed");
  1601. goto err;
  1602. }
  1603. memcpy(buf->desc->ptr, &buf->mmdata, sizeof(buf->mmdata));
  1604. /* Flushing of updated mmdata:
  1605. * mmdata is iocoherent and ubwcp will get it from CPU cache -
  1606. * *as long as* it has not cached that itself during previous
  1607. * access to the same descriptor.
  1608. *
  1609. * During unlock of previous use of this descriptor,
  1610. * we do hw flush, which will get rid of this mmdata from
  1611. * ubwcp cache.
  1612. *
  1613. * In addition, we also do a hw flush after enable_range_ck().
  1614. * That will also get rid of any speculative fetch of mmdata
  1615. * by the ubwcp hw. At this time, the assumption is that ubwcp
  1616. * will cache mmdata only for active descriptor. But if ubwcp
  1617. * is speculatively fetching mmdata for all descriptors
  1618. * (irrespetive of enabled or not), the flush during lock
  1619. * will be necessary to make sure ubwcp sees updated mmdata
  1620. * that we just updated
  1621. */
  1622. /* program ULA range for this buffer */
  1623. DBG("setting range check: descriptor_id: %d, addr: %p, size: %zx",
  1624. buf->desc->idx, buf->ula_pa, buf->ula_size);
  1625. ubwcp_hw_set_range_check(ubwcp->base, buf->desc->idx, buf->ula_pa,
  1626. buf->ula_size);
  1627. }
  1628. /* enable range check */
  1629. DBG("enabling range check, descriptor_id: %d", buf->desc->idx);
  1630. range_check_enable(ubwcp, buf->desc->idx);
  1631. /* Flush/invalidate UBWCP caches */
  1632. /* Why: cpu could have done a speculative fetch before
  1633. * enable_range_ck() and ubwcp in process of returning "default" data
  1634. * we don't want that stashing of default data pending.
  1635. * we force completion of that and then we also cpu invalidate which
  1636. * will get rid of that line.
  1637. */
  1638. ret = ubwcp_flush(ubwcp);
  1639. if (ret) {
  1640. ubwcp->state = UBWCP_STATE_FAULT;
  1641. ERR("ubwcp_flush() failed: %d, driver state set to FAULT", ret);
  1642. goto err_flush_failed;
  1643. }
  1644. /* Flush/invalidate ULA PA from CPU caches
  1645. * TBD: if (dir == READ or BIDIRECTION) //NOT for write
  1646. * -- Confirm with Chris if this can be skipped for write
  1647. */
  1648. trace_ubwcp_dma_sync_single_for_cpu_start(buf->ula_size);
  1649. dma_sync_single_for_cpu(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1650. trace_ubwcp_dma_sync_single_for_cpu_end(buf->ula_size);
  1651. buf->lock_dir = dir;
  1652. } else {
  1653. DBG("buf already locked");
  1654. /* TBD: what if new buffer direction is not same as previous?
  1655. * must update the dir.
  1656. */
  1657. }
  1658. buf->lock_count++;
  1659. DBG("new lock_count: %d", buf->lock_count);
  1660. mutex_unlock(&buf->lock);
  1661. trace_ubwcp_lock_end(dmabuf);
  1662. return ret;
  1663. err_flush_failed:
  1664. range_check_disable(ubwcp, buf->desc->idx);
  1665. ubwcp_buf_desc_free(ubwcp, buf->desc);
  1666. buf->desc = NULL;
  1667. err:
  1668. mutex_unlock(&buf->lock);
  1669. if (!ret)
  1670. ret = -1;
  1671. trace_ubwcp_lock_end(dmabuf);
  1672. return ret;
  1673. }
  1674. /* This can be called as a result of external unlock() call or
  1675. * internally if free() is called without unlock().
  1676. */
  1677. static int unlock_internal(struct ubwcp_buf *buf, enum dma_data_direction dir, bool free_buffer)
  1678. {
  1679. int ret = 0;
  1680. struct ubwcp_driver *ubwcp;
  1681. DBG("current lock_count: %d", buf->lock_count);
  1682. if (free_buffer) {
  1683. buf->lock_count = 0;
  1684. DBG("Forced lock_count: %d", buf->lock_count);
  1685. } else {
  1686. buf->lock_count--;
  1687. DBG("new lock_count: %d", buf->lock_count);
  1688. if (buf->lock_count) {
  1689. DBG("more than 1 lock on buffer. waiting until last unlock");
  1690. return 0;
  1691. }
  1692. }
  1693. ubwcp = buf->ubwcp;
  1694. /* Flush/invalidate ULA PA from CPU caches */
  1695. //TBD: if (dir == WRITE or BIDIRECTION)
  1696. trace_ubwcp_dma_sync_single_for_device_start(buf->ula_size);
  1697. dma_sync_single_for_device(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1698. trace_ubwcp_dma_sync_single_for_device_end(buf->ula_size);
  1699. /* disable range check */
  1700. DBG("disabling range check");
  1701. ret = range_check_disable(ubwcp, buf->desc->idx);
  1702. if (ret) {
  1703. ubwcp->state = UBWCP_STATE_FAULT;
  1704. ERR("disable_range_check_with_flush() failed: %d, driver state set to FAULT", ret);
  1705. }
  1706. /* release descriptor if perm range xlation is not set */
  1707. if (!buf->perm) {
  1708. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1709. buf->desc = NULL;
  1710. }
  1711. return ret;
  1712. }
  1713. /**
  1714. * Unlock buffer from CPU access. This prepares ubwcp hw to
  1715. * safely allow for device access to the compressed buffer including any
  1716. * necessary cache maintenance ops. It may also free up certain ubwcp
  1717. * resources that could result in error when accessed by CPU in
  1718. * unlocked state.
  1719. *
  1720. * @param dmabuf : ptr to the dma buf
  1721. * @param direction : direction of access
  1722. *
  1723. * @return int : 0 on success, otherwise error code
  1724. */
  1725. static int ubwcp_unlock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1726. {
  1727. struct ubwcp_buf *buf;
  1728. int ret;
  1729. FENTRY();
  1730. trace_ubwcp_unlock_start(dmabuf);
  1731. if (!dmabuf) {
  1732. ERR("NULL dmabuf input ptr");
  1733. trace_ubwcp_unlock_end(dmabuf);
  1734. return -EINVAL;
  1735. }
  1736. if (!valid_dma_direction(dir)) {
  1737. ERR("invalid direction: %d", dir);
  1738. trace_ubwcp_unlock_end(dmabuf);
  1739. return -EINVAL;
  1740. }
  1741. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1742. if (!buf) {
  1743. ERR("ubwcp_buf not found");
  1744. trace_ubwcp_unlock_end(dmabuf);
  1745. return -1;
  1746. }
  1747. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1748. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1749. trace_ubwcp_unlock_end(dmabuf);
  1750. return -EPERM;
  1751. }
  1752. mutex_lock(&buf->lock);
  1753. if (!buf->lock_count) {
  1754. ERR("unlock() called on buffer which not in locked state");
  1755. trace_ubwcp_unlock_end(dmabuf);
  1756. mutex_unlock(&buf->lock);
  1757. return -1;
  1758. }
  1759. ret = unlock_internal(buf, dir, false);
  1760. mutex_unlock(&buf->lock);
  1761. trace_ubwcp_unlock_end(dmabuf);
  1762. return ret;
  1763. }
  1764. /* Return buffer attributes for the given buffer */
  1765. int ubwcp_get_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1766. {
  1767. int ret = 0;
  1768. struct ubwcp_buf *buf;
  1769. FENTRY();
  1770. if (!dmabuf) {
  1771. ERR("NULL dmabuf input ptr");
  1772. return -EINVAL;
  1773. }
  1774. if (!attr) {
  1775. ERR("NULL attr ptr");
  1776. return -EINVAL;
  1777. }
  1778. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1779. if (!buf) {
  1780. ERR("ubwcp_buf ptr not found");
  1781. return -1;
  1782. }
  1783. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1784. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1785. return -EPERM;
  1786. }
  1787. mutex_lock(&buf->lock);
  1788. if (!buf->buf_attr_set) {
  1789. ERR("buffer attributes not set");
  1790. mutex_unlock(&buf->lock);
  1791. return -1;
  1792. }
  1793. *attr = buf->buf_attr;
  1794. mutex_unlock(&buf->lock);
  1795. return ret;
  1796. }
  1797. EXPORT_SYMBOL(ubwcp_get_buf_attrs);
  1798. /* Set permanent range translation.
  1799. * enable: Descriptor will be reserved for this buffer until disabled,
  1800. * making lock/unlock quicker.
  1801. * disable: Descriptor will not be reserved for this buffer. Instead,
  1802. * descriptor will be allocated and released for each lock/unlock.
  1803. * If currently allocated but not being used, descriptor will be
  1804. * released.
  1805. */
  1806. int ubwcp_set_perm_range_translation(struct dma_buf *dmabuf, bool enable)
  1807. {
  1808. int ret = 0;
  1809. struct ubwcp_buf *buf;
  1810. FENTRY();
  1811. if (!dmabuf) {
  1812. ERR("NULL dmabuf input ptr");
  1813. return -EINVAL;
  1814. }
  1815. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1816. if (!buf) {
  1817. ERR("ubwcp_buf not found");
  1818. return -1;
  1819. }
  1820. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1821. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1822. return -EPERM;
  1823. }
  1824. /* not implemented */
  1825. if (1) {
  1826. ERR("API not implemented yet");
  1827. return -1;
  1828. }
  1829. /* TBD: make sure we acquire buf lock while setting this so there is
  1830. * no race condition with attr_set/lock/unlock
  1831. */
  1832. buf->perm = enable;
  1833. /* if "disable" and we have allocated a desc and it is not being
  1834. * used currently, release it
  1835. */
  1836. if (!enable && buf->desc && !buf->lock_count) {
  1837. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1838. buf->desc = NULL;
  1839. /* Flush/invalidate UBWCP caches */
  1840. //TBD: need to do anything?
  1841. }
  1842. return ret;
  1843. }
  1844. EXPORT_SYMBOL(ubwcp_set_perm_range_translation);
  1845. /**
  1846. * Free up ubwcp resources for this buffer.
  1847. *
  1848. * @param dmabuf : ptr to the dma buf
  1849. *
  1850. * @return int : 0 on success, otherwise error code
  1851. */
  1852. static int ubwcp_free_buffer(struct dma_buf *dmabuf)
  1853. {
  1854. int ret = 0;
  1855. struct ubwcp_buf *buf;
  1856. struct ubwcp_driver *ubwcp;
  1857. unsigned long flags;
  1858. bool is_non_lin_buf;
  1859. FENTRY();
  1860. trace_ubwcp_free_buffer_start(dmabuf);
  1861. if (!dmabuf) {
  1862. ERR("NULL dmabuf input ptr");
  1863. trace_ubwcp_free_buffer_end(dmabuf);
  1864. return -EINVAL;
  1865. }
  1866. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1867. if (!buf) {
  1868. ERR("ubwcp_buf ptr not found");
  1869. trace_ubwcp_free_buffer_end(dmabuf);
  1870. return -1;
  1871. }
  1872. ubwcp = buf->ubwcp;
  1873. if (ubwcp->state != UBWCP_STATE_READY) {
  1874. ERR("driver in invalid state: %d", ubwcp->state);
  1875. trace_ubwcp_free_buffer_end(dmabuf);
  1876. return -EPERM;
  1877. }
  1878. mutex_lock(&buf->lock);
  1879. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1880. if (buf->lock_count) {
  1881. DBG("free before unlock (lock_count: %d). unlock()'ing first", buf->lock_count);
  1882. ret = unlock_internal(buf, buf->lock_dir, true);
  1883. if (ret)
  1884. ERR("unlock_internal(): failed : %d, but continuing free()", ret);
  1885. }
  1886. /* if we are still holding a desc, release it. this can happen only if perm == true */
  1887. if (buf->desc) {
  1888. if (!buf->perm) {
  1889. ubwcp->state = UBWCP_STATE_FAULT;
  1890. WARN_ON(true);
  1891. }
  1892. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1893. buf->desc = NULL;
  1894. }
  1895. if (buf->buf_attr_set)
  1896. reset_buf_attrs(buf);
  1897. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  1898. hash_del(&buf->hnode);
  1899. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  1900. mutex_unlock(&buf->lock);
  1901. kfree(buf);
  1902. if (is_non_lin_buf)
  1903. dec_num_non_lin_buffers(ubwcp);
  1904. trace_ubwcp_free_buffer_end(dmabuf);
  1905. return ret;
  1906. }
  1907. /* file open: TBD: increment ref count? */
  1908. static int ubwcp_open(struct inode *i, struct file *f)
  1909. {
  1910. return 0;
  1911. }
  1912. /* file open: TBD: decrement ref count? */
  1913. static int ubwcp_close(struct inode *i, struct file *f)
  1914. {
  1915. return 0;
  1916. }
  1917. /* handle IOCTLs */
  1918. static long ubwcp_ioctl(struct file *file, unsigned int ioctl_num, unsigned long ioctl_param)
  1919. {
  1920. struct ubwcp_ioctl_buffer_attrs buf_attr_ioctl;
  1921. struct ubwcp_ioctl_hw_version hw_ver;
  1922. struct ubwcp_ioctl_validate_stride validate_stride_ioctl;
  1923. struct ubwcp_ioctl_stride_align stride_align_ioctl;
  1924. enum ubwcp_std_image_format format;
  1925. struct ubwcp_driver *ubwcp;
  1926. ubwcp = ubwcp_get_driver();
  1927. if (!ubwcp)
  1928. return -EINVAL;
  1929. if (ubwcp->state != UBWCP_STATE_READY) {
  1930. ERR("driver in invalid state: %d", ubwcp->state);
  1931. return -EPERM;
  1932. }
  1933. switch (ioctl_num) {
  1934. case UBWCP_IOCTL_SET_BUF_ATTR:
  1935. if (copy_from_user(&buf_attr_ioctl, (const void __user *) ioctl_param,
  1936. sizeof(buf_attr_ioctl))) {
  1937. ERR("ERROR: copy_from_user() failed");
  1938. return -EFAULT;
  1939. }
  1940. DBG("IOCTL : SET_BUF_ATTR: fd = %d", buf_attr_ioctl.fd);
  1941. if (buf_attr_ioctl.attr.unused1 || buf_attr_ioctl.attr.unused2
  1942. || buf_attr_ioctl.attr.unused3 || buf_attr_ioctl.attr.unused4
  1943. || buf_attr_ioctl.attr.unused5 || buf_attr_ioctl.attr.unused6
  1944. || buf_attr_ioctl.attr.unused7 || buf_attr_ioctl.attr.unused8
  1945. || buf_attr_ioctl.attr.unused9) {
  1946. ERR("ERROR: buf attr unused values must be set to 0");
  1947. return -EINVAL;
  1948. }
  1949. return ubwcp_set_buf_attrs_ioctl(&buf_attr_ioctl);
  1950. case UBWCP_IOCTL_GET_HW_VER:
  1951. DBG("IOCTL : GET_HW_VER");
  1952. if (ubwcp_get_hw_version(&hw_ver))
  1953. return -EINVAL;
  1954. if (copy_to_user((void __user *)ioctl_param, &hw_ver, sizeof(hw_ver))) {
  1955. ERR("ERROR: copy_to_user() failed");
  1956. return -EFAULT;
  1957. }
  1958. break;
  1959. case UBWCP_IOCTL_GET_STRIDE_ALIGN:
  1960. DBG("IOCTL : GET_STRIDE_ALIGN");
  1961. if (copy_from_user(&stride_align_ioctl, (const void __user *) ioctl_param,
  1962. sizeof(stride_align_ioctl))) {
  1963. ERR("ERROR: copy_from_user() failed");
  1964. return -EFAULT;
  1965. }
  1966. format = to_std_format(stride_align_ioctl.image_format);
  1967. if (format == STD_IMAGE_FORMAT_INVALID)
  1968. return -EINVAL;
  1969. if (stride_align_ioctl.unused != 0)
  1970. return -EINVAL;
  1971. if (get_stride_alignment(format, &stride_align_ioctl.stride_align)) {
  1972. ERR("ERROR: copy_to_user() failed");
  1973. return -EFAULT;
  1974. }
  1975. if (copy_to_user((void __user *)ioctl_param, &stride_align_ioctl,
  1976. sizeof(stride_align_ioctl))) {
  1977. ERR("ERROR: copy_to_user() failed");
  1978. return -EFAULT;
  1979. }
  1980. break;
  1981. case UBWCP_IOCTL_VALIDATE_STRIDE:
  1982. DBG("IOCTL : VALIDATE_STRIDE");
  1983. if (copy_from_user(&validate_stride_ioctl, (const void __user *) ioctl_param,
  1984. sizeof(validate_stride_ioctl))) {
  1985. ERR("ERROR: copy_from_user() failed");
  1986. return -EFAULT;
  1987. }
  1988. format = to_std_format(validate_stride_ioctl.image_format);
  1989. if (format == STD_IMAGE_FORMAT_INVALID) {
  1990. ERR("ERROR: invalid format: %d", validate_stride_ioctl.image_format);
  1991. return -EINVAL;
  1992. }
  1993. if (validate_stride_ioctl.unused1 || validate_stride_ioctl.unused2) {
  1994. ERR("ERROR: unused values must be set to 0");
  1995. return -EINVAL;
  1996. }
  1997. validate_stride_ioctl.valid = stride_is_valid(ubwcp,
  1998. validate_stride_ioctl.image_format,
  1999. validate_stride_ioctl.width,
  2000. validate_stride_ioctl.stride);
  2001. if (copy_to_user((void __user *)ioctl_param, &validate_stride_ioctl,
  2002. sizeof(validate_stride_ioctl))) {
  2003. ERR("ERROR: copy_to_user() failed");
  2004. return -EFAULT;
  2005. }
  2006. break;
  2007. default:
  2008. ERR("Invalid ioctl_num = %d", ioctl_num);
  2009. return -EINVAL;
  2010. }
  2011. return 0;
  2012. }
  2013. static const struct file_operations ubwcp_fops = {
  2014. .owner = THIS_MODULE,
  2015. .open = ubwcp_open,
  2016. .release = ubwcp_close,
  2017. .unlocked_ioctl = ubwcp_ioctl,
  2018. };
  2019. static int read_err_r_op(void *data, u64 *value)
  2020. {
  2021. struct ubwcp_driver *ubwcp = data;
  2022. *value = ubwcp->read_err_irq_en;
  2023. return 0;
  2024. }
  2025. static int read_err_w_op(void *data, u64 value)
  2026. {
  2027. struct ubwcp_driver *ubwcp = data;
  2028. if (ubwcp->state != UBWCP_STATE_READY)
  2029. return -EPERM;
  2030. if (ubwcp_power(ubwcp, true))
  2031. goto err;
  2032. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, value);
  2033. ubwcp->read_err_irq_en = value;
  2034. if (ubwcp_power(ubwcp, false))
  2035. goto err;
  2036. return 0;
  2037. err:
  2038. ubwcp->state = UBWCP_STATE_FAULT;
  2039. return -1;
  2040. }
  2041. static int write_err_r_op(void *data, u64 *value)
  2042. {
  2043. struct ubwcp_driver *ubwcp = data;
  2044. if (ubwcp->state != UBWCP_STATE_READY)
  2045. return -EPERM;
  2046. *value = ubwcp->write_err_irq_en;
  2047. return 0;
  2048. }
  2049. static int write_err_w_op(void *data, u64 value)
  2050. {
  2051. struct ubwcp_driver *ubwcp = data;
  2052. if (ubwcp->state != UBWCP_STATE_READY)
  2053. return -EPERM;
  2054. if (ubwcp_power(ubwcp, true))
  2055. goto err;
  2056. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, value);
  2057. ubwcp->write_err_irq_en = value;
  2058. if (ubwcp_power(ubwcp, false))
  2059. goto err;
  2060. return 0;
  2061. err:
  2062. ubwcp->state = UBWCP_STATE_FAULT;
  2063. return -1;
  2064. }
  2065. static int decode_err_r_op(void *data, u64 *value)
  2066. {
  2067. struct ubwcp_driver *ubwcp = data;
  2068. if (ubwcp->state != UBWCP_STATE_READY)
  2069. return -EPERM;
  2070. *value = ubwcp->decode_err_irq_en;
  2071. return 0;
  2072. }
  2073. static int decode_err_w_op(void *data, u64 value)
  2074. {
  2075. struct ubwcp_driver *ubwcp = data;
  2076. if (ubwcp->state != UBWCP_STATE_READY)
  2077. return -EPERM;
  2078. if (ubwcp_power(ubwcp, true))
  2079. goto err;
  2080. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, value);
  2081. ubwcp->decode_err_irq_en = value;
  2082. if (ubwcp_power(ubwcp, false))
  2083. goto err;
  2084. return 0;
  2085. err:
  2086. ubwcp->state = UBWCP_STATE_FAULT;
  2087. return -1;
  2088. }
  2089. static int encode_err_r_op(void *data, u64 *value)
  2090. {
  2091. struct ubwcp_driver *ubwcp = data;
  2092. if (ubwcp->state != UBWCP_STATE_READY)
  2093. return -EPERM;
  2094. *value = ubwcp->encode_err_irq_en;
  2095. return 0;
  2096. }
  2097. static int encode_err_w_op(void *data, u64 value)
  2098. {
  2099. struct ubwcp_driver *ubwcp = data;
  2100. if (ubwcp->state != UBWCP_STATE_READY)
  2101. return -EPERM;
  2102. if (ubwcp_power(ubwcp, true))
  2103. goto err;
  2104. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, value);
  2105. ubwcp->encode_err_irq_en = value;
  2106. if (ubwcp_power(ubwcp, false))
  2107. goto err;
  2108. return 0;
  2109. err:
  2110. ubwcp->state = UBWCP_STATE_FAULT;
  2111. return -1;
  2112. }
  2113. static int reg_rw_trace_w_op(void *data, u64 value)
  2114. {
  2115. struct ubwcp_driver *ubwcp = data;
  2116. if (ubwcp->state != UBWCP_STATE_READY)
  2117. return -EPERM;
  2118. ubwcp_hw_trace_set(value);
  2119. return 0;
  2120. }
  2121. static int reg_rw_trace_r_op(void *data, u64 *value)
  2122. {
  2123. struct ubwcp_driver *ubwcp = data;
  2124. bool trace_status;
  2125. if (ubwcp->state != UBWCP_STATE_READY)
  2126. return -EPERM;
  2127. ubwcp_hw_trace_get(&trace_status);
  2128. *value = trace_status;
  2129. return 0;
  2130. }
  2131. DEFINE_DEBUGFS_ATTRIBUTE(read_err_fops, read_err_r_op, read_err_w_op, "%d\n");
  2132. DEFINE_DEBUGFS_ATTRIBUTE(decode_err_fops, decode_err_r_op, decode_err_w_op, "%d\n");
  2133. DEFINE_DEBUGFS_ATTRIBUTE(write_err_fops, write_err_r_op, write_err_w_op, "%d\n");
  2134. DEFINE_DEBUGFS_ATTRIBUTE(encode_err_fops, encode_err_r_op, encode_err_w_op, "%d\n");
  2135. DEFINE_DEBUGFS_ATTRIBUTE(reg_rw_trace_fops, reg_rw_trace_r_op, reg_rw_trace_w_op, "%d\n");
  2136. static void ubwcp_debugfs_init(struct ubwcp_driver *ubwcp)
  2137. {
  2138. struct dentry *debugfs_root;
  2139. struct dentry *dfile;
  2140. debugfs_root = debugfs_create_dir("ubwcp", NULL);
  2141. if (IS_ERR_OR_NULL(debugfs_root)) {
  2142. ERR("Failed to create debugfs for ubwcp\n");
  2143. return;
  2144. }
  2145. debugfs_create_u32("debug_trace_enable", 0644, debugfs_root, &ubwcp_debug_trace_enable);
  2146. dfile = debugfs_create_file("reg_rw_trace_en", 0644, debugfs_root, ubwcp, &reg_rw_trace_fops);
  2147. if (IS_ERR_OR_NULL(dfile)) {
  2148. ERR("failed to create reg_rw_trace_en debugfs file");
  2149. goto err;
  2150. }
  2151. dfile = debugfs_create_file("read_err_irq_en", 0644, debugfs_root, ubwcp, &read_err_fops);
  2152. if (IS_ERR_OR_NULL(dfile)) {
  2153. ERR("failed to create read_err_irq debugfs file");
  2154. goto err;
  2155. }
  2156. dfile = debugfs_create_file("write_err_irq_en", 0644, debugfs_root, ubwcp, &write_err_fops);
  2157. if (IS_ERR_OR_NULL(dfile)) {
  2158. ERR("failed to create write_err_irq debugfs file");
  2159. goto err;
  2160. }
  2161. dfile = debugfs_create_file("decode_err_irq_en", 0644, debugfs_root, ubwcp,
  2162. &decode_err_fops);
  2163. if (IS_ERR_OR_NULL(dfile)) {
  2164. ERR("failed to create decode_err_irq debugfs file");
  2165. goto err;
  2166. }
  2167. dfile = debugfs_create_file("encode_err_irq_en", 0644, debugfs_root, ubwcp,
  2168. &encode_err_fops);
  2169. if (IS_ERR_OR_NULL(dfile)) {
  2170. ERR("failed to create encode_err_irq debugfs file");
  2171. goto err;
  2172. }
  2173. ubwcp->debugfs_root = debugfs_root;
  2174. return;
  2175. err:
  2176. debugfs_remove_recursive(ubwcp->debugfs_root);
  2177. ubwcp->debugfs_root = NULL;
  2178. }
  2179. static void ubwcp_debugfs_deinit(struct ubwcp_driver *ubwcp)
  2180. {
  2181. debugfs_remove_recursive(ubwcp->debugfs_root);
  2182. }
  2183. /* ubwcp char device initialization */
  2184. static int ubwcp_cdev_init(struct ubwcp_driver *ubwcp)
  2185. {
  2186. int ret;
  2187. dev_t devt;
  2188. struct class *dev_class;
  2189. struct device *dev_sys;
  2190. /* allocate major device number (/proc/devices -> major_num ubwcp) */
  2191. ret = alloc_chrdev_region(&devt, 0, UBWCP_NUM_DEVICES, UBWCP_DEVICE_NAME);
  2192. if (ret) {
  2193. ERR("alloc_chrdev_region() failed: %d", ret);
  2194. return ret;
  2195. }
  2196. /* create device class (/sys/class/ubwcp_class) */
  2197. dev_class = class_create(THIS_MODULE, "ubwcp_class");
  2198. if (IS_ERR(dev_class)) {
  2199. ret = PTR_ERR(dev_class);
  2200. ERR("class_create() failed, ret: %d", ret);
  2201. goto err;
  2202. }
  2203. /* Create device and register with sysfs
  2204. * (/sys/class/ubwcp_class/ubwcp/... -> dev/power/subsystem/uevent)
  2205. */
  2206. dev_sys = device_create(dev_class, NULL, devt, NULL,
  2207. UBWCP_DEVICE_NAME);
  2208. if (IS_ERR(dev_sys)) {
  2209. ret = PTR_ERR(dev_sys);
  2210. ERR("device_create() failed, ret: %d", ret);
  2211. goto err_device_create;
  2212. }
  2213. /* register file operations and get cdev */
  2214. cdev_init(&ubwcp->cdev, &ubwcp_fops);
  2215. /* associate cdev and device major/minor with file system
  2216. * can do file ops on /dev/ubwcp after this
  2217. */
  2218. ret = cdev_add(&ubwcp->cdev, devt, 1);
  2219. if (ret) {
  2220. ERR("cdev_add() failed, ret: %d", ret);
  2221. goto err_cdev_add;
  2222. }
  2223. ubwcp->devt = devt;
  2224. ubwcp->dev_class = dev_class;
  2225. ubwcp->dev_sys = dev_sys;
  2226. return 0;
  2227. err_cdev_add:
  2228. device_destroy(dev_class, devt);
  2229. err_device_create:
  2230. class_destroy(dev_class);
  2231. err:
  2232. unregister_chrdev_region(devt, UBWCP_NUM_DEVICES);
  2233. return ret;
  2234. }
  2235. static void ubwcp_cdev_deinit(struct ubwcp_driver *ubwcp)
  2236. {
  2237. device_destroy(ubwcp->dev_class, ubwcp->devt);
  2238. class_destroy(ubwcp->dev_class);
  2239. cdev_del(&ubwcp->cdev);
  2240. unregister_chrdev_region(ubwcp->devt, UBWCP_NUM_DEVICES);
  2241. }
  2242. struct handler_node {
  2243. struct list_head list;
  2244. u32 client_id;
  2245. ubwcp_error_handler_t handler;
  2246. void *data;
  2247. };
  2248. int ubwcp_register_error_handler(u32 client_id, ubwcp_error_handler_t handler,
  2249. void *data)
  2250. {
  2251. struct handler_node *node;
  2252. unsigned long flags;
  2253. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2254. if (!ubwcp)
  2255. return -EINVAL;
  2256. if (client_id != -1)
  2257. return -EINVAL;
  2258. if (!handler)
  2259. return -EINVAL;
  2260. if (ubwcp->state != UBWCP_STATE_READY)
  2261. return -EPERM;
  2262. node = kzalloc(sizeof(*node), GFP_KERNEL);
  2263. if (!node)
  2264. return -ENOMEM;
  2265. node->client_id = client_id;
  2266. node->handler = handler;
  2267. node->data = data;
  2268. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2269. list_add_tail(&node->list, &ubwcp->err_handler_list);
  2270. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2271. return 0;
  2272. }
  2273. EXPORT_SYMBOL(ubwcp_register_error_handler);
  2274. static void ubwcp_notify_error_handlers(struct ubwcp_err_info *err)
  2275. {
  2276. struct handler_node *node;
  2277. unsigned long flags;
  2278. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2279. if (!ubwcp)
  2280. return;
  2281. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2282. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2283. node->handler(err, node->data);
  2284. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2285. }
  2286. int ubwcp_unregister_error_handler(u32 client_id)
  2287. {
  2288. int ret = -EINVAL;
  2289. struct handler_node *node;
  2290. unsigned long flags;
  2291. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2292. if (!ubwcp)
  2293. return -EINVAL;
  2294. if (ubwcp->state != UBWCP_STATE_INVALID)
  2295. return -EPERM;
  2296. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2297. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2298. if (node->client_id == client_id) {
  2299. list_del(&node->list);
  2300. kfree(node);
  2301. ret = 0;
  2302. break;
  2303. }
  2304. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2305. return ret;
  2306. }
  2307. EXPORT_SYMBOL(ubwcp_unregister_error_handler);
  2308. /* get ubwcp_buf corresponding to the ULA PA*/
  2309. static struct dma_buf *get_dma_buf_from_ulapa(phys_addr_t addr)
  2310. {
  2311. struct ubwcp_buf *buf = NULL;
  2312. struct dma_buf *ret_buf = NULL;
  2313. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2314. unsigned long flags;
  2315. u32 i;
  2316. if (!ubwcp)
  2317. return NULL;
  2318. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2319. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2320. if (buf->ula_pa <= addr && addr < buf->ula_pa + buf->ula_size) {
  2321. ret_buf = buf->dma_buf;
  2322. break;
  2323. }
  2324. }
  2325. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2326. return ret_buf;
  2327. }
  2328. /* get ubwcp_buf corresponding to the IOVA*/
  2329. static struct dma_buf *get_dma_buf_from_iova(unsigned long addr)
  2330. {
  2331. struct ubwcp_buf *buf = NULL;
  2332. struct dma_buf *ret_buf = NULL;
  2333. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2334. unsigned long flags;
  2335. u32 i;
  2336. if (!ubwcp)
  2337. return NULL;
  2338. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2339. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2340. unsigned long iova_base;
  2341. unsigned int iova_size;
  2342. if (!buf->sgt)
  2343. continue;
  2344. iova_base = sg_dma_address(buf->sgt->sgl);
  2345. iova_size = sg_dma_len(buf->sgt->sgl);
  2346. if (iova_base <= addr && addr < iova_base + iova_size) {
  2347. ret_buf = buf->dma_buf;
  2348. break;
  2349. }
  2350. }
  2351. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2352. return ret_buf;
  2353. }
  2354. int ubwcp_iommu_fault_handler(struct iommu_domain *domain, struct device *dev,
  2355. unsigned long iova, int flags, void *data)
  2356. {
  2357. int ret = 0;
  2358. struct ubwcp_err_info err;
  2359. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2360. struct device *cb_dev = (struct device *)data;
  2361. if (!ubwcp) {
  2362. ret = -EINVAL;
  2363. goto err;
  2364. }
  2365. err.err_code = UBWCP_SMMU_FAULT;
  2366. if (cb_dev == ubwcp->dev_desc_cb)
  2367. err.smmu_err.iommu_dev_id = UBWCP_DESC_CB_ID;
  2368. else if (cb_dev == ubwcp->dev_buf_cb)
  2369. err.smmu_err.iommu_dev_id = UBWCP_BUF_CB_ID;
  2370. else
  2371. err.smmu_err.iommu_dev_id = UBWCP_UNKNOWN_CB_ID;
  2372. err.smmu_err.dmabuf = get_dma_buf_from_iova(iova);
  2373. err.smmu_err.iova = iova;
  2374. err.smmu_err.iommu_fault_flags = flags;
  2375. ERR_RATE_LIMIT("ubwcp_err: err code: %d (smmu), iommu_dev_id: %d, iova: 0x%llx, flags: 0x%x",
  2376. err.err_code, err.smmu_err.iommu_dev_id, err.smmu_err.iova,
  2377. err.smmu_err.iommu_fault_flags);
  2378. ubwcp_notify_error_handlers(&err);
  2379. err:
  2380. return ret;
  2381. }
  2382. static irqreturn_t ubwcp_irq_handler(int irq, void *ptr)
  2383. {
  2384. struct ubwcp_driver *ubwcp;
  2385. void __iomem *base;
  2386. phys_addr_t addr;
  2387. struct ubwcp_err_info err;
  2388. ubwcp = (struct ubwcp_driver *) ptr;
  2389. base = ubwcp->base;
  2390. if (irq == ubwcp->irq_range_ck_rd) {
  2391. addr = ubwcp_hw_interrupt_src_address(base, 0) << 6;
  2392. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2393. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2394. err.translation_err.ula_pa = addr;
  2395. err.translation_err.read = true;
  2396. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2397. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2398. ubwcp_notify_error_handlers(&err);
  2399. ubwcp_hw_interrupt_clear(ubwcp->base, 0);
  2400. } else if (irq == ubwcp->irq_range_ck_wr) {
  2401. addr = ubwcp_hw_interrupt_src_address(base, 1) << 6;
  2402. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2403. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2404. err.translation_err.ula_pa = addr;
  2405. err.translation_err.read = false;
  2406. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2407. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2408. ubwcp_notify_error_handlers(&err);
  2409. ubwcp_hw_interrupt_clear(ubwcp->base, 1);
  2410. } else if (irq == ubwcp->irq_encode) {
  2411. addr = ubwcp_hw_interrupt_src_address(base, 3) << 6;
  2412. err.err_code = UBWCP_ENCODE_ERROR;
  2413. err.enc_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2414. err.enc_err.ula_pa = addr;
  2415. ERR_RATE_LIMIT("ubwcp_err: err code: %d (encode), dmabuf: 0x%llx, addr: 0x%llx",
  2416. err.err_code, err.enc_err.dmabuf, addr);
  2417. ubwcp_notify_error_handlers(&err);
  2418. ubwcp_hw_interrupt_clear(ubwcp->base, 3);
  2419. } else if (irq == ubwcp->irq_decode) {
  2420. addr = ubwcp_hw_interrupt_src_address(base, 2) << 6;
  2421. err.err_code = UBWCP_DECODE_ERROR;
  2422. err.dec_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2423. err.dec_err.ula_pa = addr;
  2424. ERR_RATE_LIMIT("ubwcp_err: err code: %d (decode), dmabuf: 0x%llx, addr: 0x%llx",
  2425. err.err_code, err.enc_err.dmabuf, addr);
  2426. ubwcp_notify_error_handlers(&err);
  2427. ubwcp_hw_interrupt_clear(ubwcp->base, 2);
  2428. } else {
  2429. ERR("unknown irq: %d", irq);
  2430. return IRQ_NONE;
  2431. }
  2432. return IRQ_HANDLED;
  2433. }
  2434. static int ubwcp_interrupt_register(struct platform_device *pdev, struct ubwcp_driver *ubwcp)
  2435. {
  2436. int ret = 0;
  2437. struct device *dev = &pdev->dev;
  2438. FENTRY();
  2439. ubwcp->irq_range_ck_rd = platform_get_irq(pdev, 0);
  2440. if (ubwcp->irq_range_ck_rd < 0)
  2441. return ubwcp->irq_range_ck_rd;
  2442. ubwcp->irq_range_ck_wr = platform_get_irq(pdev, 1);
  2443. if (ubwcp->irq_range_ck_wr < 0)
  2444. return ubwcp->irq_range_ck_wr;
  2445. ubwcp->irq_encode = platform_get_irq(pdev, 2);
  2446. if (ubwcp->irq_encode < 0)
  2447. return ubwcp->irq_encode;
  2448. ubwcp->irq_decode = platform_get_irq(pdev, 3);
  2449. if (ubwcp->irq_decode < 0)
  2450. return ubwcp->irq_decode;
  2451. DBG("got irqs: %d %d %d %d", ubwcp->irq_range_ck_rd,
  2452. ubwcp->irq_range_ck_wr,
  2453. ubwcp->irq_encode,
  2454. ubwcp->irq_decode);
  2455. ret = devm_request_irq(dev, ubwcp->irq_range_ck_rd, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2456. if (ret) {
  2457. ERR("request_irq() failed. irq: %d ret: %d",
  2458. ubwcp->irq_range_ck_rd, ret);
  2459. return ret;
  2460. }
  2461. ret = devm_request_irq(dev, ubwcp->irq_range_ck_wr, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2462. if (ret) {
  2463. ERR("request_irq() failed. irq: %d ret: %d",
  2464. ubwcp->irq_range_ck_wr, ret);
  2465. return ret;
  2466. }
  2467. ret = devm_request_irq(dev, ubwcp->irq_encode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2468. if (ret) {
  2469. ERR("request_irq() failed. irq: %d ret: %d",
  2470. ubwcp->irq_encode, ret);
  2471. return ret;
  2472. }
  2473. ret = devm_request_irq(dev, ubwcp->irq_decode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2474. if (ret) {
  2475. ERR("request_irq() failed. irq: %d ret: %d",
  2476. ubwcp->irq_decode, ret);
  2477. return ret;
  2478. }
  2479. return ret;
  2480. }
  2481. /* ubwcp device probe */
  2482. static int qcom_ubwcp_probe(struct platform_device *pdev)
  2483. {
  2484. int ret = 0;
  2485. struct ubwcp_driver *ubwcp;
  2486. struct device *ubwcp_dev = &pdev->dev;
  2487. FENTRY();
  2488. ubwcp = devm_kzalloc(ubwcp_dev, sizeof(*ubwcp), GFP_KERNEL);
  2489. if (!ubwcp) {
  2490. ERR("devm_kzalloc() failed");
  2491. return -ENOMEM;
  2492. }
  2493. ubwcp->dev = &pdev->dev;
  2494. ret = dma_set_mask_and_coherent(ubwcp->dev, DMA_BIT_MASK(64));
  2495. ubwcp->base = devm_platform_ioremap_resource(pdev, 0);
  2496. if (IS_ERR(ubwcp->base)) {
  2497. ERR("devm ioremap() failed: %d", PTR_ERR(ubwcp->base));
  2498. return PTR_ERR(ubwcp->base);
  2499. }
  2500. DBG("ubwcp->base: %p", ubwcp->base);
  2501. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 0, &ubwcp->ula_pool_base);
  2502. if (ret) {
  2503. ERR("failed reading ula_range (base): %d", ret);
  2504. return ret;
  2505. }
  2506. DBG("ubwcp: ula_range: base = 0x%lx", ubwcp->ula_pool_base);
  2507. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 1, &ubwcp->ula_pool_size);
  2508. if (ret) {
  2509. ERR("failed reading ula_range (size): %d", ret);
  2510. return ret;
  2511. }
  2512. DBG("ubwcp: ula_range: size = 0x%lx", ubwcp->ula_pool_size);
  2513. INIT_LIST_HEAD(&ubwcp->err_handler_list);
  2514. /* driver initial state */
  2515. ubwcp->state = UBWCP_STATE_INVALID;
  2516. atomic_set(&ubwcp->num_non_lin_buffers, 0);
  2517. ubwcp->mem_online = false;
  2518. mutex_init(&ubwcp->desc_lock);
  2519. spin_lock_init(&ubwcp->buf_table_lock);
  2520. mutex_init(&ubwcp->mem_hotplug_lock);
  2521. mutex_init(&ubwcp->ula_lock);
  2522. mutex_init(&ubwcp->ubwcp_flush_lock);
  2523. mutex_init(&ubwcp->hw_range_ck_lock);
  2524. spin_lock_init(&ubwcp->err_handler_list_lock);
  2525. /* Regulator */
  2526. ubwcp->vdd = devm_regulator_get(ubwcp_dev, "vdd");
  2527. if (IS_ERR_OR_NULL(ubwcp->vdd)) {
  2528. ret = PTR_ERR(ubwcp->vdd);
  2529. ERR("devm_regulator_get() failed: %d", ret);
  2530. return ret;
  2531. }
  2532. ret = ubwcp_init_clocks(ubwcp, ubwcp_dev);
  2533. if (ret) {
  2534. ERR("failed to initialize ubwcp clocks err: %d", ret);
  2535. return ret;
  2536. }
  2537. if (ubwcp_power(ubwcp, true))
  2538. return -1;
  2539. if (ubwcp_cdev_init(ubwcp))
  2540. return -1;
  2541. /* disable all interrupts (reset value has some interrupts enabled by default) */
  2542. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2543. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2544. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2545. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2546. if (ubwcp_interrupt_register(pdev, ubwcp))
  2547. return -1;
  2548. ubwcp_debugfs_init(ubwcp);
  2549. /* create ULA pool */
  2550. ubwcp->ula_pool = gen_pool_create(12, -1);
  2551. if (!ubwcp->ula_pool) {
  2552. ERR("failed gen_pool_create()");
  2553. ret = -1;
  2554. goto err_pool_create;
  2555. }
  2556. ret = gen_pool_add(ubwcp->ula_pool, ubwcp->ula_pool_base, ubwcp->ula_pool_size, -1);
  2557. if (ret) {
  2558. ERR("failed gen_pool_add(): %d", ret);
  2559. ret = -1;
  2560. goto err_pool_add;
  2561. }
  2562. /* register the default config mmap function. */
  2563. ubwcp->mmap_config_fptr = msm_ubwcp_dma_buf_configure_mmap;
  2564. hash_init(ubwcp->buf_table);
  2565. ubwcp_buf_desc_list_init(ubwcp);
  2566. image_format_init(ubwcp);
  2567. /* one time hw init */
  2568. ubwcp_hw_one_time_init(ubwcp->base);
  2569. ubwcp_hw_version(ubwcp->base, &ubwcp->hw_ver_major, &ubwcp->hw_ver_minor);
  2570. pr_err("ubwcp: hw version: major %d, minor %d\n", ubwcp->hw_ver_major, ubwcp->hw_ver_minor);
  2571. if (ubwcp->hw_ver_major == 0) {
  2572. ERR("Failed to read HW version");
  2573. ret = -1;
  2574. goto err_pool_add;
  2575. }
  2576. /* set pdev->dev->driver_data = ubwcp */
  2577. platform_set_drvdata(pdev, ubwcp);
  2578. /* enable interrupts */
  2579. if (ubwcp->read_err_irq_en)
  2580. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, true);
  2581. if (ubwcp->write_err_irq_en)
  2582. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, true);
  2583. if (ubwcp->decode_err_irq_en)
  2584. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, true);
  2585. if (ubwcp->encode_err_irq_en)
  2586. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, true);
  2587. /* Turn OFF until buffers are allocated */
  2588. if (ubwcp_power(ubwcp, false)) {
  2589. ret = -1;
  2590. goto err_power_off;
  2591. }
  2592. ret = msm_ubwcp_set_ops(ubwcp_init_buffer, ubwcp_free_buffer, ubwcp_lock, ubwcp_unlock);
  2593. if (ret) {
  2594. ERR("msm_ubwcp_set_ops() failed: %d", ret);
  2595. goto err_power_off;
  2596. } else {
  2597. DBG("msm_ubwcp_set_ops(): success"); }
  2598. me = ubwcp;
  2599. return ret;
  2600. err_power_off:
  2601. if (!ubwcp_power(ubwcp, true)) {
  2602. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2603. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2604. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2605. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2606. ubwcp_power(ubwcp, false);
  2607. }
  2608. err_pool_add:
  2609. gen_pool_destroy(ubwcp->ula_pool);
  2610. err_pool_create:
  2611. ubwcp_debugfs_deinit(ubwcp);
  2612. ubwcp_cdev_deinit(ubwcp);
  2613. return ret;
  2614. }
  2615. /* buffer context bank device probe */
  2616. static int ubwcp_probe_cb_buf(struct platform_device *pdev)
  2617. {
  2618. struct ubwcp_driver *ubwcp;
  2619. struct iommu_domain *domain = NULL;
  2620. FENTRY();
  2621. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2622. if (!ubwcp) {
  2623. ERR("failed to get ubwcp ptr");
  2624. return -EINVAL;
  2625. }
  2626. ubwcp->dev_buf_cb = &pdev->dev;
  2627. domain = iommu_get_domain_for_dev(ubwcp->dev_buf_cb);
  2628. if (domain)
  2629. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_buf_cb);
  2630. if (ubwcp->dev_desc_cb)
  2631. ubwcp->state = UBWCP_STATE_READY;
  2632. return 0;
  2633. }
  2634. /* descriptor context bank device probe */
  2635. static int ubwcp_probe_cb_desc(struct platform_device *pdev)
  2636. {
  2637. int ret = 0;
  2638. struct ubwcp_driver *ubwcp;
  2639. struct iommu_domain *domain = NULL;
  2640. FENTRY();
  2641. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2642. if (!ubwcp) {
  2643. ERR("failed to get ubwcp ptr");
  2644. return -EINVAL;
  2645. }
  2646. ubwcp->buffer_desc_size = UBWCP_BUFFER_DESC_OFFSET *
  2647. UBWCP_BUFFER_DESC_COUNT;
  2648. ubwcp->dev_desc_cb = &pdev->dev;
  2649. dma_set_max_seg_size(ubwcp->dev_desc_cb, DMA_BIT_MASK(32));
  2650. dma_set_seg_boundary(ubwcp->dev_desc_cb, (unsigned long)DMA_BIT_MASK(64));
  2651. /* Allocate buffer descriptors. UBWCP is iocoherent device.
  2652. * Thus we don't need to flush after updates to buffer descriptors.
  2653. */
  2654. ubwcp->buffer_desc_base = dma_alloc_coherent(ubwcp->dev_desc_cb,
  2655. ubwcp->buffer_desc_size,
  2656. &ubwcp->buffer_desc_dma_handle,
  2657. GFP_KERNEL);
  2658. if (!ubwcp->buffer_desc_base) {
  2659. ERR("failed to allocate desc buffer");
  2660. return -ENOMEM;
  2661. }
  2662. DBG("desc_base = %p size = %zu", ubwcp->buffer_desc_base,
  2663. ubwcp->buffer_desc_size);
  2664. ret = ubwcp_power(ubwcp, true);
  2665. if (ret) {
  2666. ERR("failed to power on");
  2667. goto err;
  2668. }
  2669. ubwcp_hw_set_buf_desc(ubwcp->base, (u64) ubwcp->buffer_desc_dma_handle,
  2670. UBWCP_BUFFER_DESC_OFFSET);
  2671. ret = ubwcp_power(ubwcp, false);
  2672. if (ret) {
  2673. ERR("failed to power off");
  2674. goto err;
  2675. }
  2676. domain = iommu_get_domain_for_dev(ubwcp->dev_desc_cb);
  2677. if (domain)
  2678. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_desc_cb);
  2679. if (ubwcp->dev_buf_cb)
  2680. ubwcp->state = UBWCP_STATE_READY;
  2681. return ret;
  2682. err:
  2683. dma_free_coherent(ubwcp->dev_desc_cb,
  2684. ubwcp->buffer_desc_size,
  2685. ubwcp->buffer_desc_base,
  2686. ubwcp->buffer_desc_dma_handle);
  2687. ubwcp->buffer_desc_base = NULL;
  2688. ubwcp->buffer_desc_dma_handle = 0;
  2689. ubwcp->dev_desc_cb = NULL;
  2690. return -1;
  2691. }
  2692. /* buffer context bank device remove */
  2693. static int ubwcp_remove_cb_buf(struct platform_device *pdev)
  2694. {
  2695. struct ubwcp_driver *ubwcp;
  2696. FENTRY();
  2697. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2698. if (!ubwcp) {
  2699. ERR("failed to get ubwcp ptr");
  2700. return -EINVAL;
  2701. }
  2702. ubwcp->state = UBWCP_STATE_INVALID;
  2703. ubwcp->dev_buf_cb = NULL;
  2704. return 0;
  2705. }
  2706. /* descriptor context bank device remove */
  2707. static int ubwcp_remove_cb_desc(struct platform_device *pdev)
  2708. {
  2709. struct ubwcp_driver *ubwcp;
  2710. FENTRY();
  2711. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2712. if (!ubwcp) {
  2713. ERR("failed to get ubwcp ptr");
  2714. return -EINVAL;
  2715. }
  2716. if (!ubwcp->dev_desc_cb) {
  2717. ERR("ubwcp->dev_desc_cb == NULL");
  2718. return -1;
  2719. }
  2720. if (!ubwcp_power(ubwcp, true)) {
  2721. ubwcp_hw_set_buf_desc(ubwcp->base, 0x0, 0x0);
  2722. ubwcp_power(ubwcp, false);
  2723. }
  2724. ubwcp->state = UBWCP_STATE_INVALID;
  2725. dma_free_coherent(ubwcp->dev_desc_cb,
  2726. ubwcp->buffer_desc_size,
  2727. ubwcp->buffer_desc_base,
  2728. ubwcp->buffer_desc_dma_handle);
  2729. ubwcp->buffer_desc_base = NULL;
  2730. ubwcp->buffer_desc_dma_handle = 0;
  2731. return 0;
  2732. }
  2733. /* ubwcp device remove */
  2734. static int qcom_ubwcp_remove(struct platform_device *pdev)
  2735. {
  2736. size_t avail;
  2737. size_t psize;
  2738. struct ubwcp_driver *ubwcp;
  2739. FENTRY();
  2740. /* get pdev->dev->driver_data = ubwcp */
  2741. ubwcp = platform_get_drvdata(pdev);
  2742. if (!ubwcp) {
  2743. ERR("ubwcp == NULL");
  2744. return -1;
  2745. }
  2746. if (!ubwcp_power(ubwcp, true)) {
  2747. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2748. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2749. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2750. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2751. ubwcp_power(ubwcp, false);
  2752. }
  2753. ubwcp->state = UBWCP_STATE_INVALID;
  2754. /* before destroying, make sure pool is empty. otherwise pool_destroy() panics. */
  2755. avail = gen_pool_avail(ubwcp->ula_pool);
  2756. psize = gen_pool_size(ubwcp->ula_pool);
  2757. if (psize != avail) {
  2758. ERR("gen_pool is not empty! avail: %zx size: %zx", avail, psize);
  2759. ERR("skipping pool destroy....cause it will PANIC. Fix this!!!!");
  2760. WARN(1, "Fix this!");
  2761. } else {
  2762. gen_pool_destroy(ubwcp->ula_pool);
  2763. }
  2764. ubwcp_debugfs_deinit(ubwcp);
  2765. ubwcp_cdev_deinit(ubwcp);
  2766. return 0;
  2767. }
  2768. /* top level ubwcp device probe function */
  2769. static int ubwcp_probe(struct platform_device *pdev)
  2770. {
  2771. const char *compatible = "";
  2772. FENTRY();
  2773. trace_ubwcp_probe(pdev);
  2774. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2775. return qcom_ubwcp_probe(pdev);
  2776. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2777. return ubwcp_probe_cb_desc(pdev);
  2778. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2779. return ubwcp_probe_cb_buf(pdev);
  2780. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2781. ERR("unknown device: %s", compatible);
  2782. WARN_ON(1);
  2783. return -EINVAL;
  2784. }
  2785. /* top level ubwcp device remove function */
  2786. static int ubwcp_remove(struct platform_device *pdev)
  2787. {
  2788. const char *compatible = "";
  2789. FENTRY();
  2790. trace_ubwcp_remove(pdev);
  2791. /* TBD: what if buffers are still allocated? locked? etc.
  2792. * also should turn off power?
  2793. */
  2794. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2795. return qcom_ubwcp_remove(pdev);
  2796. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2797. return ubwcp_remove_cb_desc(pdev);
  2798. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2799. return ubwcp_remove_cb_buf(pdev);
  2800. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2801. ERR("unknown device: %s", compatible);
  2802. WARN_ON(1);
  2803. return -EINVAL;
  2804. }
  2805. static const struct of_device_id ubwcp_dt_match[] = {
  2806. {.compatible = "qcom,ubwcp"},
  2807. {.compatible = "qcom,ubwcp-context-bank-desc"},
  2808. {.compatible = "qcom,ubwcp-context-bank-buf"},
  2809. {}
  2810. };
  2811. struct platform_driver ubwcp_platform_driver = {
  2812. .probe = ubwcp_probe,
  2813. .remove = ubwcp_remove,
  2814. .driver = {
  2815. .name = "qcom,ubwcp",
  2816. .of_match_table = ubwcp_dt_match,
  2817. },
  2818. };
  2819. int ubwcp_init(void)
  2820. {
  2821. int ret = 0;
  2822. DBG("+++++++++++");
  2823. ret = platform_driver_register(&ubwcp_platform_driver);
  2824. if (ret)
  2825. ERR("platform_driver_register() failed: %d", ret);
  2826. return ret;
  2827. }
  2828. void ubwcp_exit(void)
  2829. {
  2830. platform_driver_unregister(&ubwcp_platform_driver);
  2831. DBG("-----------");
  2832. }
  2833. module_init(ubwcp_init);
  2834. module_exit(ubwcp_exit);
  2835. MODULE_LICENSE("GPL");