cvp_hfi.c 148 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <asm/memory.h>
  7. #include <linux/coresight-stm.h>
  8. #include <linux/delay.h>
  9. #include <linux/devfreq.h>
  10. #include <linux/hash.h>
  11. #include <linux/io.h>
  12. #include <linux/iommu.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/of.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/soc/qcom/llcc-qcom.h>
  21. #include <linux/qcom_scm.h>
  22. #include <linux/soc/qcom/smem.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/reset.h>
  25. #include <linux/pm_wakeup.h>
  26. #include "hfi_packetization.h"
  27. #include "msm_cvp_debug.h"
  28. #include "cvp_core_hfi.h"
  29. #include "cvp_hfi_helper.h"
  30. #include "cvp_hfi_io.h"
  31. #include "msm_cvp_dsp.h"
  32. #include "msm_cvp_clocks.h"
  33. #include "vm/cvp_vm.h"
  34. #include "cvp_dump.h"
  35. // ysi - added for debug
  36. #include <linux/clk/qcom.h>
  37. #include "msm_cvp_common.h"
  38. #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
  39. #define QDSS_IOVA_START 0x80001000
  40. #define MIN_PAYLOAD_SIZE 3
  41. struct cvp_tzbsp_memprot {
  42. u32 cp_start;
  43. u32 cp_size;
  44. u32 cp_nonpixel_start;
  45. u32 cp_nonpixel_size;
  46. };
  47. #define TZBSP_CVP_PAS_ID 26
  48. /* Poll interval in uS */
  49. #define POLL_INTERVAL_US 50
  50. enum tzbsp_subsys_state {
  51. TZ_SUBSYS_STATE_SUSPEND = 0,
  52. TZ_SUBSYS_STATE_RESUME = 1,
  53. TZ_SUBSYS_STATE_RESTORE_THRESHOLD = 2,
  54. };
  55. const struct msm_cvp_gov_data CVP_DEFAULT_BUS_VOTE = {
  56. .data = NULL,
  57. .data_count = 0,
  58. };
  59. const int cvp_max_packets = 32;
  60. static void iris_hfi_pm_handler(struct work_struct *work);
  61. static DECLARE_DELAYED_WORK(iris_hfi_pm_work, iris_hfi_pm_handler);
  62. static inline int __resume(struct iris_hfi_device *device);
  63. static inline int __suspend(struct iris_hfi_device *device);
  64. static int __disable_regulator(struct iris_hfi_device *device,
  65. const char *name);
  66. static int __enable_regulator(struct iris_hfi_device *device,
  67. const char *name);
  68. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet);
  69. static int __initialize_packetization(struct iris_hfi_device *device);
  70. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  71. u32 session_id);
  72. static bool __is_session_valid(struct iris_hfi_device *device,
  73. struct cvp_hal_session *session, const char *func);
  74. static int __iface_cmdq_write(struct iris_hfi_device *device,
  75. void *pkt);
  76. static int __load_fw(struct iris_hfi_device *device);
  77. static int __power_on_init(struct iris_hfi_device *device);
  78. static void __unload_fw(struct iris_hfi_device *device);
  79. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state);
  80. static int __enable_subcaches(struct iris_hfi_device *device);
  81. static int __set_subcaches(struct iris_hfi_device *device);
  82. static int __release_subcaches(struct iris_hfi_device *device);
  83. static int __disable_subcaches(struct iris_hfi_device *device);
  84. static int __power_collapse(struct iris_hfi_device *device, bool force);
  85. static int iris_hfi_noc_error_info(void *dev);
  86. static void interrupt_init_iris2(struct iris_hfi_device *device);
  87. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device);
  88. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device);
  89. static void power_off_iris2(struct iris_hfi_device *device);
  90. static int __set_ubwc_config(struct iris_hfi_device *device);
  91. static void __noc_error_info_iris2(struct iris_hfi_device *device);
  92. static int __enable_hw_power_collapse(struct iris_hfi_device *device);
  93. static int __disable_hw_power_collapse(struct iris_hfi_device *device);
  94. static int __power_off_controller(struct iris_hfi_device *device);
  95. static int __hwfence_regs_map(struct iris_hfi_device *device);
  96. static int __hwfence_regs_unmap(struct iris_hfi_device *device);
  97. static int __reset_control_assert_name(struct iris_hfi_device *device, const char *name);
  98. static int __reset_control_deassert_name(struct iris_hfi_device *device, const char *name);
  99. static int __reset_control_acquire(struct iris_hfi_device *device, const char *name);
  100. static int __reset_control_release(struct iris_hfi_device *device, const char *name);
  101. static bool __is_ctl_power_on(struct iris_hfi_device *device);
  102. static void __print_sidebandmanager_regs(struct iris_hfi_device *device);
  103. static void dump_noc_reg(struct iris_hfi_device *device);
  104. static struct cvp_hal_ops hal_ops = {
  105. .interrupt_init = interrupt_init_iris2,
  106. .setup_dsp_uc_memmap = setup_dsp_uc_memmap_vpu5,
  107. .clock_config_on_enable = clock_config_on_enable_vpu5,
  108. .power_off = power_off_iris2,
  109. .noc_error_info = __noc_error_info_iris2,
  110. .reset_control_assert_name = __reset_control_assert_name,
  111. .reset_control_deassert_name = __reset_control_deassert_name,
  112. .reset_control_acquire_name = __reset_control_acquire,
  113. .reset_control_release_name = __reset_control_release,
  114. };
  115. /**
  116. * Utility function to enforce some of our assumptions. Spam calls to this
  117. * in hotspots in code to double check some of the assumptions that we hold.
  118. */
  119. static inline void __strict_check(struct iris_hfi_device *device)
  120. {
  121. msm_cvp_res_handle_fatal_hw_error(device->res,
  122. !mutex_is_locked(&device->lock));
  123. }
  124. static inline void __set_state(struct iris_hfi_device *device,
  125. enum iris_hfi_state state)
  126. {
  127. device->state = state;
  128. }
  129. static inline bool __core_in_valid_state(struct iris_hfi_device *device)
  130. {
  131. return device->state != IRIS_STATE_DEINIT;
  132. }
  133. static inline bool is_sys_cache_present(struct iris_hfi_device *device)
  134. {
  135. return device->res->sys_cache_present;
  136. }
  137. static int cvp_synx_recover(void)
  138. {
  139. #ifdef CVP_SYNX_ENABLED
  140. return synx_recover(SYNX_CLIENT_EVA_CTX0);
  141. #else
  142. return 0;
  143. #endif /* End of CVP_SYNX_ENABLED */
  144. }
  145. #define ROW_SIZE 32
  146. unsigned long long get_aon_time(void)
  147. {
  148. unsigned long long val;
  149. asm volatile("mrs %0, cntvct_el0" : "=r" (val));
  150. return val;
  151. }
  152. int get_hfi_version(void)
  153. {
  154. struct msm_cvp_core *core;
  155. struct iris_hfi_device *hfi;
  156. core = cvp_driver->cvp_core;
  157. hfi = (struct iris_hfi_device *)core->dev_ops->hfi_device_data;
  158. return hfi->version;
  159. }
  160. unsigned int get_msg_size(struct cvp_hfi_msg_session_hdr *hdr)
  161. {
  162. struct msm_cvp_core *core;
  163. struct iris_hfi_device *device;
  164. u32 minor_ver;
  165. core = cvp_driver->cvp_core;
  166. if (core)
  167. device = core->dev_ops->hfi_device_data;
  168. else
  169. return 0;
  170. if (!device) {
  171. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  172. return 0;
  173. }
  174. minor_ver = (device->version & HFI_VERSION_MINOR_MASK) >>
  175. HFI_VERSION_MINOR_SHIFT;
  176. if (minor_ver < 2)
  177. return sizeof(struct cvp_hfi_msg_session_hdr);
  178. if (hdr->packet_type == HFI_MSG_SESSION_CVP_FD)
  179. return sizeof(struct cvp_hfi_msg_session_hdr_ext);
  180. else
  181. return sizeof(struct cvp_hfi_msg_session_hdr);
  182. }
  183. unsigned int get_msg_session_id(void *msg)
  184. {
  185. struct cvp_hfi_msg_session_hdr *hdr =
  186. (struct cvp_hfi_msg_session_hdr *)msg;
  187. return hdr->session_id;
  188. }
  189. unsigned int get_msg_errorcode(void *msg)
  190. {
  191. struct cvp_hfi_msg_session_hdr *hdr =
  192. (struct cvp_hfi_msg_session_hdr *)msg;
  193. return hdr->error_type;
  194. }
  195. int get_msg_opconfigs(void *msg, unsigned int *session_id,
  196. unsigned int *error_type, unsigned int *config_id)
  197. {
  198. struct cvp_hfi_msg_session_op_cfg_packet *cfg =
  199. (struct cvp_hfi_msg_session_op_cfg_packet *)msg;
  200. *session_id = cfg->session_id;
  201. *error_type = cfg->error_type;
  202. *config_id = cfg->op_conf_id;
  203. return 0;
  204. }
  205. static void __dump_packet(u8 *packet, enum cvp_msg_prio log_level)
  206. {
  207. u32 c = 0, packet_size = *(u32 *)packet;
  208. /*
  209. * row must contain enough for 0xdeadbaad * 8 to be converted into
  210. * "de ad ba ab " * 8 + '\0'
  211. */
  212. char row[3 * ROW_SIZE];
  213. for (c = 0; c * ROW_SIZE < packet_size; ++c) {
  214. int bytes_to_read = ((c + 1) * ROW_SIZE > packet_size) ?
  215. packet_size % ROW_SIZE : ROW_SIZE;
  216. hex_dump_to_buffer(packet + c * ROW_SIZE, bytes_to_read,
  217. ROW_SIZE, 4, row, sizeof(row), false);
  218. dprintk(log_level, "%s\n", row);
  219. }
  220. }
  221. static int __dsp_suspend(struct iris_hfi_device *device, bool force)
  222. {
  223. int rc;
  224. if (msm_cvp_dsp_disable)
  225. return 0;
  226. dprintk(CVP_DSP, "%s: suspend dsp\n", __func__);
  227. rc = cvp_dsp_suspend(force);
  228. if (rc) {
  229. if (rc != -EBUSY)
  230. dprintk(CVP_ERR,
  231. "%s: dsp suspend failed with error %d\n",
  232. __func__, rc);
  233. return rc;
  234. }
  235. dprintk(CVP_DSP, "%s: dsp suspended\n", __func__);
  236. return 0;
  237. }
  238. static int __dsp_resume(struct iris_hfi_device *device)
  239. {
  240. int rc;
  241. if (msm_cvp_dsp_disable)
  242. return 0;
  243. dprintk(CVP_DSP, "%s: resume dsp\n", __func__);
  244. rc = cvp_dsp_resume();
  245. if (rc) {
  246. dprintk(CVP_ERR,
  247. "%s: dsp resume failed with error %d\n",
  248. __func__, rc);
  249. return rc;
  250. }
  251. dprintk(CVP_DSP, "%s: dsp resumed\n", __func__);
  252. return rc;
  253. }
  254. static int __dsp_shutdown(struct iris_hfi_device *device)
  255. {
  256. int rc;
  257. if (msm_cvp_dsp_disable)
  258. return 0;
  259. dprintk(CVP_DSP, "%s: shutdown dsp\n", __func__);
  260. rc = cvp_dsp_shutdown();
  261. if (rc) {
  262. dprintk(CVP_ERR,
  263. "%s: dsp shutdown failed with error %d\n",
  264. __func__, rc);
  265. WARN_ON(1);
  266. }
  267. dprintk(CVP_DSP, "%s: dsp shutdown successful\n", __func__);
  268. return rc;
  269. }
  270. static int __acquire_regulator(struct regulator_info *rinfo,
  271. struct iris_hfi_device *device)
  272. {
  273. int rc = 0;
  274. if (rinfo->has_hw_power_collapse) {
  275. rc = regulator_set_mode(rinfo->regulator,
  276. REGULATOR_MODE_NORMAL);
  277. if (rc) {
  278. /*
  279. * This is somewhat fatal, but nothing we can do
  280. * about it. We can't disable the regulator w/o
  281. * getting it back under s/w control
  282. */
  283. dprintk(CVP_WARN,
  284. "Failed to acquire regulator control: %s\n",
  285. rinfo->name);
  286. } else {
  287. dprintk(CVP_PWR,
  288. "Acquire regulator control from HW: %s\n",
  289. rinfo->name);
  290. }
  291. }
  292. if (!regulator_is_enabled(rinfo->regulator)) {
  293. dprintk(CVP_WARN, "Regulator is not enabled %s\n",
  294. rinfo->name);
  295. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  296. }
  297. return rc;
  298. }
  299. static int __hand_off_regulator(struct regulator_info *rinfo)
  300. {
  301. int rc = 0;
  302. if (rinfo->has_hw_power_collapse) {
  303. rc = regulator_set_mode(rinfo->regulator,
  304. REGULATOR_MODE_FAST);
  305. if (rc) {
  306. dprintk(CVP_WARN,
  307. "Failed to hand off regulator control: %s\n",
  308. rinfo->name);
  309. } else {
  310. dprintk(CVP_PWR,
  311. "Hand off regulator control to HW: %s\n",
  312. rinfo->name);
  313. }
  314. }
  315. return rc;
  316. }
  317. static int __hand_off_regulators(struct iris_hfi_device *device)
  318. {
  319. struct regulator_info *rinfo;
  320. int rc = 0, c = 0;
  321. iris_hfi_for_each_regulator(device, rinfo) {
  322. rc = __hand_off_regulator(rinfo);
  323. /*
  324. * If one regulator hand off failed, driver should take
  325. * the control for other regulators back.
  326. */
  327. if (rc)
  328. goto err_reg_handoff_failed;
  329. c++;
  330. }
  331. return rc;
  332. err_reg_handoff_failed:
  333. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  334. __acquire_regulator(rinfo, device);
  335. return rc;
  336. }
  337. static int __take_back_regulators(struct iris_hfi_device *device)
  338. {
  339. struct regulator_info *rinfo;
  340. int rc = 0;
  341. iris_hfi_for_each_regulator(device, rinfo) {
  342. rc = __acquire_regulator(rinfo, device);
  343. /*
  344. * if one regulator hand off failed, driver should take
  345. * the control for other regulators back.
  346. */
  347. if (rc)
  348. return rc;
  349. }
  350. return rc;
  351. }
  352. static int __write_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  353. bool *rx_req_is_set)
  354. {
  355. struct cvp_hfi_queue_header *queue;
  356. struct cvp_hfi_cmd_session_hdr *cmd_pkt;
  357. u32 packet_size_in_words, new_write_idx;
  358. u32 empty_space, read_idx, write_idx;
  359. u32 *write_ptr;
  360. if (!qinfo || !packet) {
  361. dprintk(CVP_ERR, "Invalid Params\n");
  362. return -EINVAL;
  363. } else if (!qinfo->q_array.align_virtual_addr) {
  364. dprintk(CVP_WARN, "Queues have already been freed\n");
  365. return -EINVAL;
  366. }
  367. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  368. if (!queue) {
  369. dprintk(CVP_ERR, "queue not present\n");
  370. return -ENOENT;
  371. }
  372. cmd_pkt = (struct cvp_hfi_cmd_session_hdr *)packet;
  373. if (cmd_pkt->size >= sizeof(struct cvp_hfi_cmd_session_hdr))
  374. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  375. __func__, cmd_pkt->packet_type,
  376. cmd_pkt->session_id,
  377. cmd_pkt->client_data.transaction_id,
  378. cmd_pkt->client_data.kdata & (FENCE_BIT - 1));
  379. else if (cmd_pkt->size >= 12)
  380. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x\n", __func__,
  381. cmd_pkt->packet_type, cmd_pkt->session_id);
  382. if (msm_cvp_debug & CVP_PKT) {
  383. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  384. __dump_packet(packet, CVP_PKT);
  385. }
  386. packet_size_in_words = (*(u32 *)packet) >> 2;
  387. if (!packet_size_in_words || packet_size_in_words >
  388. qinfo->q_array.mem_size>>2) {
  389. dprintk(CVP_ERR, "Invalid packet size\n");
  390. return -ENODATA;
  391. }
  392. spin_lock(&qinfo->hfi_lock);
  393. read_idx = queue->qhdr_read_idx;
  394. write_idx = queue->qhdr_write_idx;
  395. empty_space = (write_idx >= read_idx) ?
  396. ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) :
  397. (read_idx - write_idx);
  398. if (empty_space <= packet_size_in_words) {
  399. queue->qhdr_tx_req = 1;
  400. spin_unlock(&qinfo->hfi_lock);
  401. dprintk(CVP_ERR, "Insufficient size (%d) to write (%d)\n",
  402. empty_space, packet_size_in_words);
  403. return -ENOTEMPTY;
  404. }
  405. queue->qhdr_tx_req = 0;
  406. new_write_idx = write_idx + packet_size_in_words;
  407. write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  408. (write_idx << 2));
  409. if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  410. write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  411. qinfo->q_array.mem_size)) {
  412. spin_unlock(&qinfo->hfi_lock);
  413. dprintk(CVP_ERR, "Invalid write index\n");
  414. return -ENODATA;
  415. }
  416. if (new_write_idx < (qinfo->q_array.mem_size >> 2)) {
  417. memcpy(write_ptr, packet, packet_size_in_words << 2);
  418. } else {
  419. new_write_idx -= qinfo->q_array.mem_size >> 2;
  420. memcpy(write_ptr, packet, (packet_size_in_words -
  421. new_write_idx) << 2);
  422. memcpy((void *)qinfo->q_array.align_virtual_addr,
  423. packet + ((packet_size_in_words - new_write_idx) << 2),
  424. new_write_idx << 2);
  425. }
  426. /*
  427. * Memory barrier to make sure packet is written before updating the
  428. * write index
  429. */
  430. mb();
  431. queue->qhdr_write_idx = new_write_idx;
  432. if (rx_req_is_set)
  433. *rx_req_is_set = queue->qhdr_rx_req == 1;
  434. /*
  435. * Memory barrier to make sure write index is updated before an
  436. * interrupt is raised.
  437. */
  438. mb();
  439. spin_unlock(&qinfo->hfi_lock);
  440. return 0;
  441. }
  442. static int __read_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  443. u32 *pb_tx_req_is_set)
  444. {
  445. struct cvp_hfi_queue_header *queue;
  446. struct cvp_hfi_msg_session_hdr *msg_pkt;
  447. u32 packet_size_in_words, new_read_idx;
  448. u32 *read_ptr;
  449. u32 receive_request = 0;
  450. u32 read_idx, write_idx;
  451. int rc = 0;
  452. if (!qinfo || !packet || !pb_tx_req_is_set) {
  453. dprintk(CVP_ERR, "Invalid Params\n");
  454. return -EINVAL;
  455. } else if (!qinfo->q_array.align_virtual_addr) {
  456. dprintk(CVP_WARN, "Queues have already been freed\n");
  457. return -EINVAL;
  458. }
  459. /*
  460. * Memory barrier to make sure data is valid before
  461. *reading it
  462. */
  463. mb();
  464. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  465. if (!queue) {
  466. dprintk(CVP_ERR, "Queue memory is not allocated\n");
  467. return -ENOMEM;
  468. }
  469. /*
  470. * Do not set receive request for debug queue, if set,
  471. * Iris generates interrupt for debug messages even
  472. * when there is no response message available.
  473. * In general debug queue will not become full as it
  474. * is being emptied out for every interrupt from Iris.
  475. * Iris will anyway generates interrupt if it is full.
  476. */
  477. spin_lock(&qinfo->hfi_lock);
  478. if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q)
  479. receive_request = 1;
  480. read_idx = queue->qhdr_read_idx;
  481. write_idx = queue->qhdr_write_idx;
  482. if (read_idx == write_idx) {
  483. queue->qhdr_rx_req = receive_request;
  484. /*
  485. * mb() to ensure qhdr is updated in main memory
  486. * so that iris reads the updated header values
  487. */
  488. mb();
  489. *pb_tx_req_is_set = 0;
  490. if (write_idx != queue->qhdr_write_idx) {
  491. queue->qhdr_rx_req = 0;
  492. } else {
  493. spin_unlock(&qinfo->hfi_lock);
  494. dprintk(CVP_HFI,
  495. "%s queue is empty, rx_req = %u, tx_req = %u, read_idx = %u\n",
  496. receive_request ? "message" : "debug",
  497. queue->qhdr_rx_req, queue->qhdr_tx_req,
  498. queue->qhdr_read_idx);
  499. return -ENODATA;
  500. }
  501. }
  502. read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  503. (read_idx << 2));
  504. if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  505. read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  506. qinfo->q_array.mem_size - sizeof(*read_ptr))) {
  507. spin_unlock(&qinfo->hfi_lock);
  508. dprintk(CVP_ERR, "Invalid read index\n");
  509. return -ENODATA;
  510. }
  511. packet_size_in_words = (*read_ptr) >> 2;
  512. if (!packet_size_in_words) {
  513. spin_unlock(&qinfo->hfi_lock);
  514. dprintk(CVP_ERR, "Zero packet size\n");
  515. return -ENODATA;
  516. }
  517. new_read_idx = read_idx + packet_size_in_words;
  518. if (((packet_size_in_words << 2) <= CVP_IFACEQ_VAR_HUGE_PKT_SIZE)
  519. && read_idx <= (qinfo->q_array.mem_size >> 2)) {
  520. if (new_read_idx < (qinfo->q_array.mem_size >> 2)) {
  521. memcpy(packet, read_ptr,
  522. packet_size_in_words << 2);
  523. } else {
  524. new_read_idx -= (qinfo->q_array.mem_size >> 2);
  525. memcpy(packet, read_ptr,
  526. (packet_size_in_words - new_read_idx) << 2);
  527. memcpy(packet + ((packet_size_in_words -
  528. new_read_idx) << 2),
  529. (u8 *)qinfo->q_array.align_virtual_addr,
  530. new_read_idx << 2);
  531. }
  532. } else {
  533. dprintk(CVP_WARN,
  534. "BAD packet received, read_idx: %#x, pkt_size: %d\n",
  535. read_idx, packet_size_in_words << 2);
  536. dprintk(CVP_WARN, "Dropping this packet\n");
  537. new_read_idx = write_idx;
  538. rc = -ENODATA;
  539. }
  540. if (new_read_idx != queue->qhdr_write_idx)
  541. queue->qhdr_rx_req = 0;
  542. else
  543. queue->qhdr_rx_req = receive_request;
  544. queue->qhdr_read_idx = new_read_idx;
  545. /*
  546. * mb() to ensure qhdr is updated in main memory
  547. * so that iris reads the updated header values
  548. */
  549. mb();
  550. *pb_tx_req_is_set = (queue->qhdr_tx_req == 1) ? 1 : 0;
  551. spin_unlock(&qinfo->hfi_lock);
  552. if (!(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  553. msg_pkt = (struct cvp_hfi_msg_session_hdr *)packet;
  554. dprintk(CVP_CMD, "%s: "
  555. "pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  556. __func__, msg_pkt->packet_type,
  557. msg_pkt->session_id,
  558. msg_pkt->client_data.transaction_id,
  559. msg_pkt->client_data.kdata & (FENCE_BIT - 1));
  560. }
  561. if ((msm_cvp_debug & CVP_PKT) &&
  562. !(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  563. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  564. __dump_packet(packet, CVP_PKT);
  565. }
  566. return rc;
  567. }
  568. static int __smem_alloc(struct iris_hfi_device *dev, struct cvp_mem_addr *mem,
  569. u32 size, u32 align, u32 flags)
  570. {
  571. struct msm_cvp_smem *alloc = &mem->mem_data;
  572. int rc = 0;
  573. if (!dev || !mem || !size) {
  574. dprintk(CVP_ERR, "Invalid Params\n");
  575. return -EINVAL;
  576. }
  577. dprintk(CVP_INFO, "start to alloc size: %d, flags: %d\n", size, flags);
  578. alloc->flags = flags;
  579. rc = msm_cvp_smem_alloc(size, align, 1, (void *)dev->res, alloc);
  580. if (rc) {
  581. dprintk(CVP_ERR, "Alloc failed\n");
  582. rc = -ENOMEM;
  583. goto fail_smem_alloc;
  584. }
  585. dprintk(CVP_MEM, "%s: ptr = %pK, size = %d\n", __func__,
  586. alloc->kvaddr, size);
  587. mem->mem_size = alloc->size;
  588. mem->align_virtual_addr = alloc->kvaddr;
  589. mem->align_device_addr = alloc->device_addr;
  590. alloc->pkt_type = 0;
  591. alloc->buf_idx = 0;
  592. return rc;
  593. fail_smem_alloc:
  594. return rc;
  595. }
  596. static void __smem_free(struct iris_hfi_device *dev, struct msm_cvp_smem *mem)
  597. {
  598. if (!dev || !mem) {
  599. dprintk(CVP_ERR, "invalid param %pK %pK\n", dev, mem);
  600. return;
  601. }
  602. msm_cvp_smem_free(mem);
  603. }
  604. static void __write_register(struct iris_hfi_device *device,
  605. u32 reg, u32 value)
  606. {
  607. u32 hwiosymaddr = reg;
  608. u8 *base_addr;
  609. if (!device) {
  610. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  611. return;
  612. }
  613. __strict_check(device);
  614. if (!device->power_enabled) {
  615. dprintk(CVP_WARN,
  616. "HFI Write register failed : Power is OFF\n");
  617. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  618. return;
  619. }
  620. base_addr = device->cvp_hal_data->register_base;
  621. dprintk(CVP_REG, "Base addr: %pK, written to: %#x, Value: %#x...\n",
  622. base_addr, hwiosymaddr, value);
  623. base_addr += hwiosymaddr;
  624. writel_relaxed(value, base_addr);
  625. /*
  626. * Memory barrier to make sure value is written into the register.
  627. */
  628. wmb();
  629. }
  630. static int __read_gcc_register(struct iris_hfi_device *device, u32 reg)
  631. {
  632. int rc = 0;
  633. u8 *base_addr;
  634. if (!device) {
  635. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  636. return -EINVAL;
  637. }
  638. __strict_check(device);
  639. if (!device->power_enabled) {
  640. dprintk(CVP_WARN,
  641. "%s HFI Read register failed : Power is OFF\n",
  642. __func__);
  643. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  644. return -EINVAL;
  645. }
  646. base_addr = device->cvp_hal_data->gcc_reg_base;
  647. rc = readl_relaxed(base_addr + reg);
  648. /*
  649. * Memory barrier to make sure value is read correctly from the
  650. * register.
  651. */
  652. rmb();
  653. dprintk(CVP_REG,
  654. "GCC Base addr: %pK, read from: %#x, value: %#x...\n",
  655. base_addr, reg, rc);
  656. return rc;
  657. }
  658. static int __read_register(struct iris_hfi_device *device, u32 reg)
  659. {
  660. int rc = 0;
  661. u8 *base_addr;
  662. if (!device) {
  663. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  664. return -EINVAL;
  665. }
  666. __strict_check(device);
  667. if (!device->power_enabled) {
  668. dprintk(CVP_WARN,
  669. "HFI Read register failed : Power is OFF\n");
  670. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  671. return -EINVAL;
  672. }
  673. base_addr = device->cvp_hal_data->register_base;
  674. rc = readl_relaxed(base_addr + reg);
  675. /*
  676. * Memory barrier to make sure value is read correctly from the
  677. * register.
  678. */
  679. rmb();
  680. dprintk(CVP_REG, "Base addr: %pK, read from: %#x, value: %#x...\n",
  681. base_addr, reg, rc);
  682. return rc;
  683. }
  684. static bool __is_ctl_power_on(struct iris_hfi_device *device)
  685. {
  686. u32 reg;
  687. reg = __read_register(device, CVP_CC_MVS1C_GDSCR);
  688. if (!(reg & 0x80000000))
  689. return false;
  690. reg = __read_register(device, CVP_CC_MVS1C_CBCR);
  691. if (reg & 0x80000000)
  692. return false;
  693. return true;
  694. }
  695. static int __set_registers(struct iris_hfi_device *device)
  696. {
  697. struct msm_cvp_core *core;
  698. struct msm_cvp_platform_data *pdata;
  699. struct reg_set *reg_set;
  700. int i;
  701. if (!device->res) {
  702. dprintk(CVP_ERR,
  703. "device resources null, cannot set registers\n");
  704. return -EINVAL ;
  705. }
  706. core = cvp_driver->cvp_core;
  707. pdata = core->platform_data;
  708. reg_set = &device->res->reg_set;
  709. for (i = 0; i < reg_set->count; i++) {
  710. __write_register(device, reg_set->reg_tbl[i].reg,
  711. reg_set->reg_tbl[i].value);
  712. dprintk(CVP_REG, "write_reg offset=%x, val=%x\n",
  713. reg_set->reg_tbl[i].reg,
  714. reg_set->reg_tbl[i].value);
  715. }
  716. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  717. if (i) {
  718. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  719. return -EINVAL;
  720. }
  721. __write_register(device, CVP_CPU_CS_AXI4_QOS,
  722. pdata->noc_qos->axi_qos);
  723. __write_register(device,
  724. CVP_NOC_RGE_PRIORITYLUT_LOW +
  725. device->res->qos_noc_rge_niu_offset,
  726. pdata->noc_qos->prioritylut_low);
  727. __write_register(device,
  728. CVP_NOC_RGE_PRIORITYLUT_HIGH +
  729. device->res->qos_noc_rge_niu_offset,
  730. pdata->noc_qos->prioritylut_high);
  731. __write_register(device,
  732. CVP_NOC_RGE_URGENCY_LOW +
  733. device->res->qos_noc_rge_niu_offset,
  734. pdata->noc_qos->urgency_low);
  735. __write_register(device,
  736. CVP_NOC_RGE_DANGERLUT_LOW +
  737. device->res->qos_noc_rge_niu_offset,
  738. pdata->noc_qos->dangerlut_low);
  739. __write_register(device,
  740. CVP_NOC_RGE_SAFELUT_LOW +
  741. device->res->qos_noc_rge_niu_offset,
  742. pdata->noc_qos->safelut_low);
  743. __write_register(device,
  744. CVP_NOC_GCE_PRIORITYLUT_LOW +
  745. device->res->qos_noc_gce_vadl_tof_niu_offset,
  746. pdata->noc_qos->prioritylut_low);
  747. __write_register(device,
  748. CVP_NOC_GCE_PRIORITYLUT_HIGH +
  749. device->res->qos_noc_gce_vadl_tof_niu_offset,
  750. pdata->noc_qos->prioritylut_high);
  751. __write_register(device,
  752. CVP_NOC_GCE_URGENCY_LOW +
  753. device->res->qos_noc_gce_vadl_tof_niu_offset,
  754. pdata->noc_qos->urgency_low);
  755. __write_register(device,
  756. CVP_NOC_GCE_DANGERLUT_LOW +
  757. device->res->qos_noc_gce_vadl_tof_niu_offset,
  758. pdata->noc_qos->dangerlut_low);
  759. __write_register(device,
  760. CVP_NOC_GCE_SAFELUT_LOW +
  761. device->res->qos_noc_gce_vadl_tof_niu_offset,
  762. pdata->noc_qos->safelut_low);
  763. __write_register(device,
  764. CVP_NOC_CDM_PRIORITYLUT_LOW +
  765. device->res->qos_noc_cdm_niu_offset,
  766. pdata->noc_qos->prioritylut_low);
  767. __write_register(device,
  768. CVP_NOC_CDM_PRIORITYLUT_HIGH +
  769. device->res->qos_noc_cdm_niu_offset,
  770. pdata->noc_qos->prioritylut_high);
  771. __write_register(device,
  772. CVP_NOC_CDM_URGENCY_LOW +
  773. device->res->qos_noc_cdm_niu_offset,
  774. pdata->noc_qos->urgency_low_ro);
  775. __write_register(device,
  776. CVP_NOC_CDM_DANGERLUT_LOW +
  777. device->res->qos_noc_cdm_niu_offset,
  778. pdata->noc_qos->dangerlut_low);
  779. __write_register(device,
  780. CVP_NOC_CDM_SAFELUT_LOW +
  781. device->res->qos_noc_cdm_niu_offset,
  782. pdata->noc_qos->safelut_low);
  783. /* Below registers write moved from FW to SW to enable UBWC */
  784. __write_register(device,
  785. CVP_NOC_RGE_NIU_DECCTL_LOW +
  786. device->res->qos_noc_rge_niu_offset,
  787. 0x1);
  788. __write_register(device,
  789. CVP_NOC_RGE_NIU_ENCCTL_LOW +
  790. device->res->qos_noc_rge_niu_offset,
  791. 0x1);
  792. __write_register(device,
  793. CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW +
  794. device->res->qos_noc_gce_vadl_tof_niu_offset,
  795. 0x1);
  796. __write_register(device,
  797. CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW +
  798. device->res->qos_noc_gce_vadl_tof_niu_offset,
  799. 0x1);
  800. __write_register(device,
  801. CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS +
  802. device->res->noc_core_err_offset,
  803. 0x3);
  804. __write_register(device,
  805. CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW +
  806. device->res->noc_main_sidebandmanager_offset,
  807. 0x1);
  808. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  809. return 0;
  810. }
  811. /*
  812. * The existence of this function is a hack for 8996 (or certain Iris versions)
  813. * to overcome a hardware bug. Whenever the GDSCs momentarily power collapse
  814. * (after calling __hand_off_regulators()), the values of the threshold
  815. * registers (typically programmed by TZ) are incorrectly reset. As a result
  816. * reprogram these registers at certain agreed upon points.
  817. */
  818. static void __set_threshold_registers(struct iris_hfi_device *device)
  819. {
  820. u32 version = __read_register(device, CVP_WRAPPER_HW_VERSION);
  821. version &= ~GENMASK(15, 0);
  822. if (version != (0x3 << 28 | 0x43 << 16))
  823. return;
  824. if (__tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESTORE_THRESHOLD))
  825. dprintk(CVP_ERR, "Failed to restore threshold values\n");
  826. }
  827. static int __unvote_buses(struct iris_hfi_device *device)
  828. {
  829. int rc = 0;
  830. struct bus_info *bus = NULL;
  831. kfree(device->bus_vote.data);
  832. device->bus_vote.data = NULL;
  833. device->bus_vote.data_count = 0;
  834. iris_hfi_for_each_bus(device, bus) {
  835. rc = cvp_set_bw(bus, 0);
  836. if (rc) {
  837. dprintk(CVP_ERR,
  838. "%s: Failed unvoting bus\n", __func__);
  839. goto err_unknown_device;
  840. }
  841. }
  842. err_unknown_device:
  843. return rc;
  844. }
  845. static int __vote_buses(struct iris_hfi_device *device,
  846. struct cvp_bus_vote_data *data, int num_data)
  847. {
  848. int rc = 0;
  849. struct bus_info *bus = NULL;
  850. struct cvp_bus_vote_data *new_data = NULL;
  851. if (!num_data) {
  852. dprintk(CVP_PWR, "No vote data available\n");
  853. goto no_data_count;
  854. } else if (!data) {
  855. dprintk(CVP_ERR, "Invalid voting data\n");
  856. return -EINVAL;
  857. }
  858. new_data = kmemdup(data, num_data * sizeof(*new_data), GFP_KERNEL);
  859. if (!new_data) {
  860. dprintk(CVP_ERR, "Can't alloc memory to cache bus votes\n");
  861. rc = -ENOMEM;
  862. goto err_no_mem;
  863. }
  864. no_data_count:
  865. kfree(device->bus_vote.data);
  866. device->bus_vote.data = new_data;
  867. device->bus_vote.data_count = num_data;
  868. iris_hfi_for_each_bus(device, bus) {
  869. if (bus) {
  870. rc = cvp_set_bw(bus, bus->range[1]);
  871. if (rc)
  872. dprintk(CVP_ERR,
  873. "Failed voting bus %s to ab %u\n",
  874. bus->name, bus->range[1]*1000);
  875. }
  876. }
  877. err_no_mem:
  878. return rc;
  879. }
  880. static int iris_hfi_vote_buses(void *dev, struct bus_info *bus, unsigned long bw)
  881. {
  882. int rc = 0;
  883. struct iris_hfi_device *device = dev;
  884. if (!device)
  885. return -EINVAL;
  886. mutex_lock(&device->lock);
  887. rc = cvp_set_bw(bus, bw);
  888. mutex_unlock(&device->lock);
  889. return rc;
  890. }
  891. static int __core_set_resource(struct iris_hfi_device *device,
  892. struct cvp_resource_hdr *resource_hdr, void *resource_value)
  893. {
  894. struct cvp_hfi_cmd_sys_set_resource_packet *pkt;
  895. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  896. int rc = 0;
  897. if (!device || !resource_hdr || !resource_value) {
  898. dprintk(CVP_ERR, "set_res: Invalid Params\n");
  899. return -EINVAL;
  900. }
  901. pkt = (struct cvp_hfi_cmd_sys_set_resource_packet *) packet;
  902. rc = call_hfi_pkt_op(device, sys_set_resource,
  903. pkt, resource_hdr, resource_value);
  904. if (rc) {
  905. dprintk(CVP_ERR, "set_res: failed to create packet\n");
  906. goto err_create_pkt;
  907. }
  908. rc = __iface_cmdq_write(device, pkt);
  909. if (rc)
  910. rc = -ENOTEMPTY;
  911. err_create_pkt:
  912. return rc;
  913. }
  914. static int __core_release_resource(struct iris_hfi_device *device,
  915. struct cvp_resource_hdr *resource_hdr)
  916. {
  917. struct cvp_hfi_cmd_sys_release_resource_packet *pkt;
  918. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  919. int rc = 0;
  920. if (!device || !resource_hdr) {
  921. dprintk(CVP_ERR, "release_res: Invalid Params\n");
  922. return -EINVAL;
  923. }
  924. pkt = (struct cvp_hfi_cmd_sys_release_resource_packet *) packet;
  925. rc = call_hfi_pkt_op(device, sys_release_resource,
  926. pkt, resource_hdr);
  927. if (rc) {
  928. dprintk(CVP_ERR, "release_res: failed to create packet\n");
  929. goto err_create_pkt;
  930. }
  931. rc = __iface_cmdq_write(device, pkt);
  932. if (rc)
  933. rc = -ENOTEMPTY;
  934. err_create_pkt:
  935. return rc;
  936. }
  937. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state)
  938. {
  939. int rc = 0;
  940. rc = qcom_scm_set_remote_state(state, TZBSP_CVP_PAS_ID);
  941. dprintk(CVP_CORE, "Set state %d, resp %d\n", state, rc);
  942. if (rc) {
  943. dprintk(CVP_ERR, "Failed qcom_scm_set_remote_state %d\n", rc);
  944. return rc;
  945. }
  946. return 0;
  947. }
  948. /*
  949. * Based on fal10_veto, X2RPMh, core_pwr_on and PWAitMode value, infer
  950. * value of xtss_sw_reset. xtss_sw_reset is a TZ register bit. Driver
  951. * cannot access it directly.
  952. *
  953. * In __boot_firmware() function, the caller of this function. It checks
  954. * "core_pwr_on" == false, basically core powered off. So this function
  955. * doesn't check core_pwr_on. Assume core_pwr_on = false.
  956. *
  957. * fal10_veto = VPU_CPU_CS_X2RPMh[2] |
  958. * ( ~VPU_CPU_CS_X2RPMh[1] & core_pwr_on ) |
  959. * ( ~VPU_CPU_CS_X2RPMh[0] & ~( xtss_sw_reset | PWaitMode ) ) ;
  960. */
  961. static inline void check_tensilica_in_reset(struct iris_hfi_device *device)
  962. {
  963. u32 X2RPMh, fal10_veto, wait_mode;
  964. X2RPMh = __read_register(device, CVP_CPU_CS_X2RPMh);
  965. X2RPMh = X2RPMh & 0x7;
  966. /* wait_mode = 1: Tensilica is in WFI mode (PWaitMode = true) */
  967. wait_mode = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  968. wait_mode = wait_mode & 0x1;
  969. fal10_veto = __read_register(device, CVP_CPU_CS_X2RPMh_STATUS);
  970. fal10_veto = fal10_veto & 0x1;
  971. dprintk(CVP_WARN, "tensilica reset check %#x %#x %#x\n",
  972. X2RPMh, wait_mode, fal10_veto);
  973. }
  974. static const char boot_states[0x40][32] = {
  975. "NOT INIT",
  976. "RST_START",
  977. "INIT_MEMCTL",
  978. "INTENABLE_RST",
  979. "LITBASE_RST",
  980. "PREFETCH_EN",
  981. "MPU_INIT",
  982. "CTRL_INIT_READ",
  983. "MEMCTL_L1_FIX",
  984. "RESTORE_EXTRA_NW",
  985. "CORE_RESTORE",
  986. "COLD_BOOT",
  987. "DISABLE_CACHE",
  988. "BEFORE_MPU_C",
  989. "RET_MPU_C",
  990. "IN_MPU_C",
  991. "IN_MPU_DEFAULT",
  992. "IN_MPU_SYNX",
  993. "UCR_SIZE_FAIL",
  994. "UCR_ADDR_FAIL",
  995. "UCR1_SIZE_FAIL",
  996. "UCR1_ADDR_FAIL",
  997. "UCR_OVERLAPPED_UCR1",
  998. "UCR1_OVERLAPPED_UCR",
  999. "UCR_EQ_UCR1",
  1000. "MPU_CHECK_DONE",
  1001. "BEFORE_INT_LOCK",
  1002. "AFTER_INT_LOCK",
  1003. "BEFORE_INT_UNLOCK",
  1004. "AFTER_INT_UNLOCK",
  1005. "CALL_START",
  1006. "MAIN_ENTRY",
  1007. "VENUS_INIT_ENTRY",
  1008. "VSYS_INIT_ENTRY",
  1009. "BEFORE_XOS_CLK",
  1010. "AFTER_XOS_CLK",
  1011. "LOG_MUTEX_INIT",
  1012. "CREATE_FRAMEWORK_ENTRY",
  1013. "DTG_INIT",
  1014. "IDLE_TASK_INIT",
  1015. "VENUS_CORE_INIT",
  1016. "HW_CORES_INIT",
  1017. "RST_THREAD_INIT",
  1018. "HOST_THREAD_INIT",
  1019. "ALL_THREADS_INIT",
  1020. "TASK_MEMPOOL",
  1021. "SESSION_MUTEX",
  1022. "SIGNALS_INIT",
  1023. "RST_SIGNAL_INIT",
  1024. "INTR_EN_HOST",
  1025. "INTR_REG_HOST",
  1026. "INTR_EN_DSP",
  1027. "INTR_REG_DSP",
  1028. "X2HSOFTINTEN",
  1029. "H2XSOFTINTEN",
  1030. "CPU2DSPINTEN",
  1031. "DSP2CPUINT_SWRESET",
  1032. "THREADS_START",
  1033. "RST_THREAD_START",
  1034. "HST_THREAD_START",
  1035. "HST_THREAD_ENTRY"
  1036. };
  1037. static inline int __boot_firmware(struct iris_hfi_device *device)
  1038. {
  1039. int rc = 0, loop = 10;
  1040. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 5000;
  1041. u32 reg_gdsc;
  1042. /*
  1043. * Hand off control of regulators to h/w _after_ enabling clocks.
  1044. * Note that the GDSC will turn off when switching from normal
  1045. * (s/w triggered) to fast (HW triggered) unless the h/w vote is
  1046. * present. Since Iris isn't up yet, the GDSC will be off briefly.
  1047. */
  1048. if (__enable_hw_power_collapse(device))
  1049. dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
  1050. if (!msm_cvp_fw_low_power_mode)
  1051. goto skip_core_power_check;
  1052. while (loop) {
  1053. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  1054. if (reg_gdsc & 0x80000000) {
  1055. usleep_range(100, 200);
  1056. loop--;
  1057. } else {
  1058. break;
  1059. }
  1060. }
  1061. if (!loop)
  1062. dprintk(CVP_ERR, "fail to power off CORE during resume\n");
  1063. skip_core_power_check:
  1064. ctrl_init_val = BIT(0);
  1065. /* RUMI: CVP_CTRL_INIT in MPTest has bit 0 and 3 set */
  1066. __write_register(device, CVP_CTRL_INIT, ctrl_init_val);
  1067. while (!(ctrl_status & CVP_CTRL_INIT_STATUS__M) && count < max_tries) {
  1068. ctrl_status = __read_register(device, CVP_CTRL_STATUS);
  1069. if ((ctrl_status & CVP_CTRL_ERROR_STATUS__M) == 0x4) {
  1070. dprintk(CVP_ERR, "invalid setting for UC_REGION\n");
  1071. rc = -ENODATA;
  1072. break;
  1073. }
  1074. /* Reduce to 50, 100 on silicon */
  1075. usleep_range(50, 100);
  1076. count++;
  1077. }
  1078. if (!(ctrl_status & CVP_CTRL_INIT_STATUS__M)) {
  1079. ctrl_init_val = __read_register(device, CVP_CTRL_INIT);
  1080. dprintk(CVP_ERR,
  1081. "Failed to boot FW status: %x %x %s\n",
  1082. ctrl_status, ctrl_init_val,
  1083. boot_states[(ctrl_status >> 9) & 0x3f]);
  1084. check_tensilica_in_reset(device);
  1085. rc = -ENODEV;
  1086. }
  1087. /* Enable interrupt before sending commands to tensilica */
  1088. __write_register(device, CVP_CPU_CS_H2XSOFTINTEN, 0x1);
  1089. __write_register(device, CVP_CPU_CS_X2RPMh, 0x0);
  1090. return rc;
  1091. }
  1092. static int iris_hfi_resume(void *dev)
  1093. {
  1094. int rc = 0;
  1095. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1096. if (!device) {
  1097. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1098. return -EINVAL;
  1099. }
  1100. dprintk(CVP_CORE, "Resuming Iris\n");
  1101. mutex_lock(&device->lock);
  1102. rc = __resume(device);
  1103. mutex_unlock(&device->lock);
  1104. return rc;
  1105. }
  1106. static int iris_hfi_suspend(void *dev)
  1107. {
  1108. int rc = 0;
  1109. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1110. if (!device) {
  1111. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1112. return -EINVAL;
  1113. } else if (!device->res->sw_power_collapsible) {
  1114. return -ENOTSUPP;
  1115. }
  1116. dprintk(CVP_CORE, "Suspending Iris\n");
  1117. mutex_lock(&device->lock);
  1118. rc = __power_collapse(device, true);
  1119. if (rc) {
  1120. dprintk(CVP_WARN, "%s: Iris is busy\n", __func__);
  1121. rc = -EBUSY;
  1122. }
  1123. mutex_unlock(&device->lock);
  1124. /* Cancel pending delayed works if any */
  1125. if (!rc)
  1126. cancel_delayed_work(&iris_hfi_pm_work);
  1127. return rc;
  1128. }
  1129. void cvp_dump_csr(struct iris_hfi_device *dev)
  1130. {
  1131. u32 reg;
  1132. if (!dev)
  1133. return;
  1134. if (!dev->power_enabled || dev->reg_dumped)
  1135. return;
  1136. reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
  1137. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
  1138. reg = __read_register(dev, CVP_CPU_CS_SCIACMDARG0);
  1139. dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
  1140. reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
  1141. dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
  1142. reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
  1143. dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
  1144. reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
  1145. dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
  1146. reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
  1147. dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
  1148. reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
  1149. dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
  1150. reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
  1151. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
  1152. reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  1153. dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
  1154. dump_noc_reg(dev);
  1155. dev->reg_dumped = true;
  1156. }
  1157. static int iris_hfi_flush_debug_queue(void *dev)
  1158. {
  1159. int rc = 0;
  1160. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1161. if (!device) {
  1162. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1163. return -EINVAL;
  1164. }
  1165. mutex_lock(&device->lock);
  1166. if (!device->power_enabled) {
  1167. dprintk(CVP_WARN, "%s: iris power off\n", __func__);
  1168. rc = -EINVAL;
  1169. goto exit;
  1170. }
  1171. cvp_dump_csr(device);
  1172. __flush_debug_queue(device, NULL);
  1173. exit:
  1174. mutex_unlock(&device->lock);
  1175. return rc;
  1176. }
  1177. static int iris_hfi_scale_clocks(void *dev, u32 freq)
  1178. {
  1179. int rc = 0;
  1180. struct iris_hfi_device *device = dev;
  1181. if (!device) {
  1182. dprintk(CVP_ERR, "Invalid args: %pK\n", device);
  1183. return -EINVAL;
  1184. }
  1185. mutex_lock(&device->lock);
  1186. if (__resume(device)) {
  1187. dprintk(CVP_ERR, "Resume from power collapse failed\n");
  1188. rc = -ENODEV;
  1189. goto exit;
  1190. }
  1191. rc = msm_cvp_set_clocks_impl(device, freq);
  1192. exit:
  1193. mutex_unlock(&device->lock);
  1194. return rc;
  1195. }
  1196. /* Writes into cmdq without raising an interrupt */
  1197. static int __iface_cmdq_write_relaxed(struct iris_hfi_device *device,
  1198. void *pkt, bool *requires_interrupt)
  1199. {
  1200. struct cvp_iface_q_info *q_info;
  1201. struct cvp_hal_cmd_pkt_hdr *cmd_packet;
  1202. int result = -E2BIG;
  1203. if (!device || !pkt) {
  1204. dprintk(CVP_ERR, "Invalid Params\n");
  1205. return -EINVAL;
  1206. }
  1207. __strict_check(device);
  1208. if (!__core_in_valid_state(device)) {
  1209. dprintk(CVP_ERR, "%s - fw not in init state\n", __func__);
  1210. result = -EINVAL;
  1211. goto err_q_null;
  1212. }
  1213. cmd_packet = (struct cvp_hal_cmd_pkt_hdr *)pkt;
  1214. device->last_packet_type = cmd_packet->packet_type;
  1215. q_info = &device->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1216. if (!q_info) {
  1217. dprintk(CVP_ERR, "cannot write to shared Q's\n");
  1218. goto err_q_null;
  1219. }
  1220. if (!q_info->q_array.align_virtual_addr) {
  1221. dprintk(CVP_ERR, "cannot write to shared CMD Q's\n");
  1222. result = -ENODATA;
  1223. goto err_q_null;
  1224. }
  1225. if (__resume(device)) {
  1226. dprintk(CVP_ERR, "%s: Power on failed\n", __func__);
  1227. goto err_q_write;
  1228. }
  1229. if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) {
  1230. if (device->res->sw_power_collapsible) {
  1231. cancel_delayed_work(&iris_hfi_pm_work);
  1232. if (!queue_delayed_work(device->iris_pm_workq,
  1233. &iris_hfi_pm_work,
  1234. msecs_to_jiffies(
  1235. device->res->msm_cvp_pwr_collapse_delay))) {
  1236. dprintk(CVP_PWR,
  1237. "PM work already scheduled\n");
  1238. }
  1239. }
  1240. result = 0;
  1241. } else {
  1242. dprintk(CVP_ERR, "__iface_cmdq_write: queue full\n");
  1243. }
  1244. err_q_write:
  1245. err_q_null:
  1246. return result;
  1247. }
  1248. static int __iface_cmdq_write(struct iris_hfi_device *device, void *pkt)
  1249. {
  1250. bool needs_interrupt = false;
  1251. int rc = __iface_cmdq_write_relaxed(device, pkt, &needs_interrupt);
  1252. if (!rc && needs_interrupt) {
  1253. /* Consumer of cmdq prefers that we raise an interrupt */
  1254. rc = 0;
  1255. if (!__is_ctl_power_on(device))
  1256. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1257. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1258. }
  1259. return rc;
  1260. }
  1261. static int __iface_msgq_read(struct iris_hfi_device *device, void *pkt)
  1262. {
  1263. u32 tx_req_is_set = 0;
  1264. int rc = 0;
  1265. struct cvp_iface_q_info *q_info;
  1266. if (!pkt) {
  1267. dprintk(CVP_ERR, "Invalid Params\n");
  1268. return -EINVAL;
  1269. }
  1270. __strict_check(device);
  1271. if (!__core_in_valid_state(device)) {
  1272. dprintk(CVP_WARN, "%s - fw not in init state\n", __func__);
  1273. rc = -EINVAL;
  1274. goto read_error_null;
  1275. }
  1276. q_info = &device->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1277. if (q_info->q_array.align_virtual_addr == NULL) {
  1278. dprintk(CVP_ERR, "cannot read from shared MSG Q's\n");
  1279. rc = -ENODATA;
  1280. goto read_error_null;
  1281. }
  1282. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1283. if (tx_req_is_set) {
  1284. if (!__is_ctl_power_on(device))
  1285. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1286. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1287. }
  1288. rc = 0;
  1289. } else
  1290. rc = -ENODATA;
  1291. read_error_null:
  1292. return rc;
  1293. }
  1294. static int __iface_dbgq_read(struct iris_hfi_device *device, void *pkt)
  1295. {
  1296. u32 tx_req_is_set = 0;
  1297. int rc = 0;
  1298. struct cvp_iface_q_info *q_info;
  1299. if (!pkt) {
  1300. dprintk(CVP_ERR, "Invalid Params\n");
  1301. return -EINVAL;
  1302. }
  1303. __strict_check(device);
  1304. q_info = &device->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1305. if (q_info->q_array.align_virtual_addr == NULL) {
  1306. dprintk(CVP_ERR, "cannot read from shared DBG Q's\n");
  1307. rc = -ENODATA;
  1308. goto dbg_error_null;
  1309. }
  1310. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1311. if (tx_req_is_set) {
  1312. if (!__is_ctl_power_on(device))
  1313. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1314. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1315. }
  1316. rc = 0;
  1317. } else
  1318. rc = -ENODATA;
  1319. dbg_error_null:
  1320. return rc;
  1321. }
  1322. static void __set_queue_hdr_defaults(struct cvp_hfi_queue_header *q_hdr)
  1323. {
  1324. q_hdr->qhdr_status = 0x1;
  1325. q_hdr->qhdr_type = CVP_IFACEQ_DFLT_QHDR;
  1326. q_hdr->qhdr_q_size = CVP_IFACEQ_QUEUE_SIZE / 4;
  1327. q_hdr->qhdr_pkt_size = 0;
  1328. q_hdr->qhdr_rx_wm = 0x1;
  1329. q_hdr->qhdr_tx_wm = 0x1;
  1330. q_hdr->qhdr_rx_req = 0x1;
  1331. q_hdr->qhdr_tx_req = 0x0;
  1332. q_hdr->qhdr_rx_irq_status = 0x0;
  1333. q_hdr->qhdr_tx_irq_status = 0x0;
  1334. q_hdr->qhdr_read_idx = 0x0;
  1335. q_hdr->qhdr_write_idx = 0x0;
  1336. }
  1337. /*
  1338. *Unused, keep for reference
  1339. */
  1340. /*
  1341. static void __interface_dsp_queues_release(struct iris_hfi_device *device)
  1342. {
  1343. int i;
  1344. struct msm_cvp_smem *mem_data = &device->dsp_iface_q_table.mem_data;
  1345. struct context_bank_info *cb = mem_data->mapping_info.cb_info;
  1346. if (!device->dsp_iface_q_table.align_virtual_addr) {
  1347. dprintk(CVP_ERR, "%s: already released\n", __func__);
  1348. return;
  1349. }
  1350. dma_unmap_single_attrs(cb->dev, mem_data->device_addr,
  1351. mem_data->size, DMA_BIDIRECTIONAL, 0);
  1352. dma_free_coherent(device->res->mem_cdsp.dev, mem_data->size,
  1353. mem_data->kvaddr, mem_data->dma_handle);
  1354. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1355. device->dsp_iface_queues[i].q_hdr = NULL;
  1356. device->dsp_iface_queues[i].q_array.align_virtual_addr = NULL;
  1357. device->dsp_iface_queues[i].q_array.align_device_addr = 0;
  1358. }
  1359. device->dsp_iface_q_table.align_virtual_addr = NULL;
  1360. device->dsp_iface_q_table.align_device_addr = 0;
  1361. }
  1362. */
  1363. static int __interface_dsp_queues_init(struct iris_hfi_device *dev)
  1364. {
  1365. int rc = 0;
  1366. u32 i;
  1367. struct cvp_iface_q_info *iface_q;
  1368. int offset = 0;
  1369. phys_addr_t fw_bias = 0;
  1370. size_t q_size;
  1371. struct msm_cvp_smem *mem_data;
  1372. void *kvaddr;
  1373. dma_addr_t dma_handle;
  1374. dma_addr_t iova;
  1375. struct context_bank_info *cb;
  1376. q_size = ALIGN(QUEUE_SIZE, SZ_1M);
  1377. mem_data = &dev->dsp_iface_q_table.mem_data;
  1378. if (mem_data->kvaddr) {
  1379. memset((void *)mem_data->kvaddr, 0, q_size);
  1380. cvp_dsp_init_hfi_queue_hdr(dev);
  1381. return 0;
  1382. }
  1383. /* Allocate dsp queues from CDSP device memory */
  1384. kvaddr = dma_alloc_coherent(dev->res->mem_cdsp.dev, q_size,
  1385. &dma_handle, GFP_KERNEL);
  1386. if (IS_ERR_OR_NULL(kvaddr)) {
  1387. dprintk(CVP_ERR, "%s: failed dma allocation\n", __func__);
  1388. goto fail_dma_alloc;
  1389. }
  1390. cb = msm_cvp_smem_get_context_bank(dev->res, SMEM_CDSP);
  1391. if (!cb) {
  1392. dprintk(CVP_ERR,
  1393. "%s: failed to get DSP context bank\n", __func__);
  1394. goto fail_dma_map;
  1395. }
  1396. iova = dma_map_single_attrs(cb->dev, phys_to_virt(dma_handle),
  1397. q_size, DMA_BIDIRECTIONAL, 0);
  1398. if (dma_mapping_error(cb->dev, iova)) {
  1399. dprintk(CVP_ERR, "%s: failed dma mapping\n", __func__);
  1400. goto fail_dma_map;
  1401. }
  1402. dprintk(CVP_DSP,
  1403. "%s: kvaddr %pK dma_handle %#llx iova %#llx size %zd\n",
  1404. __func__, kvaddr, dma_handle, iova, q_size);
  1405. memset(mem_data, 0, sizeof(struct msm_cvp_smem));
  1406. mem_data->kvaddr = kvaddr;
  1407. mem_data->device_addr = iova;
  1408. mem_data->dma_handle = dma_handle;
  1409. mem_data->size = q_size;
  1410. mem_data->mapping_info.cb_info = cb;
  1411. if (!is_iommu_present(dev->res))
  1412. fw_bias = dev->cvp_hal_data->firmware_base;
  1413. dev->dsp_iface_q_table.align_virtual_addr = kvaddr;
  1414. dev->dsp_iface_q_table.align_device_addr = iova - fw_bias;
  1415. dev->dsp_iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1416. offset = dev->dsp_iface_q_table.mem_size;
  1417. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1418. iface_q = &dev->dsp_iface_queues[i];
  1419. iface_q->q_array.align_device_addr = iova + offset - fw_bias;
  1420. iface_q->q_array.align_virtual_addr = kvaddr + offset;
  1421. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1422. offset += iface_q->q_array.mem_size;
  1423. spin_lock_init(&iface_q->hfi_lock);
  1424. }
  1425. cvp_dsp_init_hfi_queue_hdr(dev);
  1426. return rc;
  1427. fail_dma_map:
  1428. dma_free_coherent(dev->res->mem_cdsp.dev, q_size, kvaddr, dma_handle);
  1429. fail_dma_alloc:
  1430. return -ENOMEM;
  1431. }
  1432. static void __interface_queues_release(struct iris_hfi_device *device)
  1433. {
  1434. #ifdef CONFIG_EVA_TVM
  1435. int i;
  1436. struct cvp_hfi_mem_map_table *qdss;
  1437. struct cvp_hfi_mem_map *mem_map;
  1438. int num_entries = device->res->qdss_addr_set.count;
  1439. unsigned long mem_map_table_base_addr;
  1440. struct context_bank_info *cb;
  1441. if (device->qdss.align_virtual_addr) {
  1442. qdss = (struct cvp_hfi_mem_map_table *)
  1443. device->qdss.align_virtual_addr;
  1444. qdss->mem_map_num_entries = num_entries;
  1445. mem_map_table_base_addr =
  1446. device->qdss.align_device_addr +
  1447. sizeof(struct cvp_hfi_mem_map_table);
  1448. qdss->mem_map_table_base_addr =
  1449. (u32)mem_map_table_base_addr;
  1450. if ((unsigned long)qdss->mem_map_table_base_addr !=
  1451. mem_map_table_base_addr) {
  1452. dprintk(CVP_ERR,
  1453. "Invalid mem_map_table_base_addr %#lx",
  1454. mem_map_table_base_addr);
  1455. }
  1456. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1457. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1458. for (i = 0; cb && i < num_entries; i++) {
  1459. iommu_unmap(cb->domain,
  1460. mem_map[i].virtual_addr,
  1461. mem_map[i].size);
  1462. }
  1463. __smem_free(device, &device->qdss.mem_data);
  1464. }
  1465. __smem_free(device, &device->iface_q_table.mem_data);
  1466. __smem_free(device, &device->sfr.mem_data);
  1467. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1468. device->iface_queues[i].q_hdr = NULL;
  1469. device->iface_queues[i].q_array.align_virtual_addr = NULL;
  1470. device->iface_queues[i].q_array.align_device_addr = 0;
  1471. }
  1472. device->iface_q_table.align_virtual_addr = NULL;
  1473. device->iface_q_table.align_device_addr = 0;
  1474. device->qdss.align_virtual_addr = NULL;
  1475. device->qdss.align_device_addr = 0;
  1476. device->sfr.align_virtual_addr = NULL;
  1477. device->sfr.align_device_addr = 0;
  1478. device->mem_addr.align_virtual_addr = NULL;
  1479. device->mem_addr.align_device_addr = 0;
  1480. #endif
  1481. }
  1482. static int __get_qdss_iommu_virtual_addr(struct iris_hfi_device *dev,
  1483. struct cvp_hfi_mem_map *mem_map,
  1484. struct iommu_domain *domain)
  1485. {
  1486. int i;
  1487. int rc = 0;
  1488. dma_addr_t iova = QDSS_IOVA_START;
  1489. int num_entries = dev->res->qdss_addr_set.count;
  1490. struct addr_range *qdss_addr_tbl = dev->res->qdss_addr_set.addr_tbl;
  1491. if (!num_entries)
  1492. return -ENODATA;
  1493. for (i = 0; i < num_entries; i++) {
  1494. if (domain) {
  1495. rc = iommu_map(domain, iova,
  1496. qdss_addr_tbl[i].start,
  1497. qdss_addr_tbl[i].size,
  1498. IOMMU_READ | IOMMU_WRITE);
  1499. if (rc) {
  1500. dprintk(CVP_ERR,
  1501. "IOMMU QDSS mapping failed for addr %#x\n",
  1502. qdss_addr_tbl[i].start);
  1503. rc = -ENOMEM;
  1504. break;
  1505. }
  1506. } else {
  1507. iova = qdss_addr_tbl[i].start;
  1508. }
  1509. mem_map[i].virtual_addr = (u32)iova;
  1510. mem_map[i].physical_addr = qdss_addr_tbl[i].start;
  1511. mem_map[i].size = qdss_addr_tbl[i].size;
  1512. mem_map[i].attr = 0x0;
  1513. iova += mem_map[i].size;
  1514. }
  1515. if (i < num_entries) {
  1516. dprintk(CVP_ERR,
  1517. "QDSS mapping failed, Freeing other entries %d\n", i);
  1518. for (--i; domain && i >= 0; i--) {
  1519. iommu_unmap(domain,
  1520. mem_map[i].virtual_addr,
  1521. mem_map[i].size);
  1522. }
  1523. }
  1524. return rc;
  1525. }
  1526. static void __setup_ucregion_memory_map(struct iris_hfi_device *device)
  1527. {
  1528. __write_register(device, CVP_UC_REGION_ADDR,
  1529. (u32)device->iface_q_table.align_device_addr);
  1530. __write_register(device, CVP_UC_REGION_SIZE, SHARED_QSIZE);
  1531. __write_register(device, CVP_QTBL_ADDR,
  1532. (u32)device->iface_q_table.align_device_addr);
  1533. __write_register(device, CVP_QTBL_INFO, 0x01);
  1534. if (device->sfr.align_device_addr)
  1535. __write_register(device, CVP_SFR_ADDR,
  1536. (u32)device->sfr.align_device_addr);
  1537. if (device->qdss.align_device_addr)
  1538. __write_register(device, CVP_MMAP_ADDR,
  1539. (u32)device->qdss.align_device_addr);
  1540. call_iris_op(device, setup_dsp_uc_memmap, device);
  1541. }
  1542. static void __hfi_queue_init(struct iris_hfi_device *dev)
  1543. {
  1544. int i, offset = 0;
  1545. struct cvp_hfi_queue_table_header *q_tbl_hdr;
  1546. struct cvp_iface_q_info *iface_q;
  1547. struct cvp_hfi_queue_header *q_hdr;
  1548. if (!dev)
  1549. return;
  1550. offset += dev->iface_q_table.mem_size;
  1551. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1552. iface_q = &dev->iface_queues[i];
  1553. iface_q->q_array.align_device_addr =
  1554. dev->iface_q_table.align_device_addr + offset;
  1555. iface_q->q_array.align_virtual_addr =
  1556. dev->iface_q_table.align_virtual_addr + offset;
  1557. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1558. offset += iface_q->q_array.mem_size;
  1559. iface_q->q_hdr = CVP_IFACEQ_GET_QHDR_START_ADDR(
  1560. dev->iface_q_table.align_virtual_addr, i);
  1561. __set_queue_hdr_defaults(iface_q->q_hdr);
  1562. spin_lock_init(&iface_q->hfi_lock);
  1563. }
  1564. q_tbl_hdr = (struct cvp_hfi_queue_table_header *)
  1565. dev->iface_q_table.align_virtual_addr;
  1566. q_tbl_hdr->qtbl_version = 0;
  1567. q_tbl_hdr->device_addr = (void *)dev;
  1568. strlcpy(q_tbl_hdr->name, "msm_cvp", sizeof(q_tbl_hdr->name));
  1569. q_tbl_hdr->qtbl_size = CVP_IFACEQ_TABLE_SIZE;
  1570. q_tbl_hdr->qtbl_qhdr0_offset =
  1571. sizeof(struct cvp_hfi_queue_table_header);
  1572. q_tbl_hdr->qtbl_qhdr_size = sizeof(struct cvp_hfi_queue_header);
  1573. q_tbl_hdr->qtbl_num_q = CVP_IFACEQ_NUMQ;
  1574. q_tbl_hdr->qtbl_num_active_q = CVP_IFACEQ_NUMQ;
  1575. iface_q = &dev->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1576. q_hdr = iface_q->q_hdr;
  1577. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1578. q_hdr->qhdr_type |= HFI_Q_ID_HOST_TO_CTRL_CMD_Q;
  1579. iface_q = &dev->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1580. q_hdr = iface_q->q_hdr;
  1581. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1582. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_MSG_Q;
  1583. iface_q = &dev->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1584. q_hdr = iface_q->q_hdr;
  1585. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1586. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
  1587. /*
  1588. * Set receive request to zero on debug queue as there is no
  1589. * need of interrupt from cvp hardware for debug messages
  1590. */
  1591. q_hdr->qhdr_rx_req = 0;
  1592. }
  1593. static void __sfr_init(struct iris_hfi_device *dev)
  1594. {
  1595. struct cvp_hfi_sfr_struct *vsfr;
  1596. if (!dev)
  1597. return;
  1598. vsfr = (struct cvp_hfi_sfr_struct *) dev->sfr.align_virtual_addr;
  1599. if (vsfr)
  1600. vsfr->bufSize = ALIGNED_SFR_SIZE;
  1601. }
  1602. static int __interface_queues_init(struct iris_hfi_device *dev)
  1603. {
  1604. int rc = 0;
  1605. struct cvp_hfi_mem_map_table *qdss;
  1606. struct cvp_hfi_mem_map *mem_map;
  1607. struct cvp_mem_addr *mem_addr;
  1608. int num_entries = dev->res->qdss_addr_set.count;
  1609. phys_addr_t fw_bias = 0;
  1610. size_t q_size;
  1611. unsigned long mem_map_table_base_addr;
  1612. struct context_bank_info *cb;
  1613. q_size = SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE;
  1614. mem_addr = &dev->mem_addr;
  1615. if (!is_iommu_present(dev->res))
  1616. fw_bias = dev->cvp_hal_data->firmware_base;
  1617. if (dev->iface_q_table.align_virtual_addr) {
  1618. memset((void *)dev->iface_q_table.align_virtual_addr,
  1619. 0, q_size);
  1620. goto hfi_queue_init;
  1621. }
  1622. rc = __smem_alloc(dev, mem_addr, q_size, 1, SMEM_UNCACHED);
  1623. if (rc) {
  1624. dprintk(CVP_ERR, "iface_q_table_alloc_fail\n");
  1625. goto fail_alloc_queue;
  1626. }
  1627. dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
  1628. dev->iface_q_table.align_device_addr = mem_addr->align_device_addr -
  1629. fw_bias;
  1630. dev->iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1631. dev->iface_q_table.mem_data = mem_addr->mem_data;
  1632. hfi_queue_init:
  1633. __hfi_queue_init(dev);
  1634. if (dev->sfr.align_virtual_addr) {
  1635. memset((void *)dev->sfr.align_virtual_addr,
  1636. 0, ALIGNED_SFR_SIZE);
  1637. goto sfr_init;
  1638. }
  1639. rc = __smem_alloc(dev, mem_addr, ALIGNED_SFR_SIZE, 1, SMEM_UNCACHED);
  1640. if (rc) {
  1641. dprintk(CVP_WARN, "sfr_alloc_fail: SFR not will work\n");
  1642. dev->sfr.align_device_addr = 0;
  1643. } else {
  1644. dev->sfr.align_device_addr = mem_addr->align_device_addr -
  1645. fw_bias;
  1646. dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr;
  1647. dev->sfr.mem_size = ALIGNED_SFR_SIZE;
  1648. dev->sfr.mem_data = mem_addr->mem_data;
  1649. }
  1650. sfr_init:
  1651. __sfr_init(dev);
  1652. if (dev->qdss.align_virtual_addr)
  1653. goto dsp_hfi_queue_init;
  1654. if ((msm_cvp_fw_debug_mode & HFI_DEBUG_MODE_QDSS) && num_entries) {
  1655. rc = __smem_alloc(dev, mem_addr, ALIGNED_QDSS_SIZE, 1,
  1656. SMEM_UNCACHED);
  1657. if (rc) {
  1658. dprintk(CVP_WARN,
  1659. "qdss_alloc_fail: QDSS messages logging will not work\n");
  1660. dev->qdss.align_device_addr = 0;
  1661. } else {
  1662. dev->qdss.align_device_addr =
  1663. mem_addr->align_device_addr - fw_bias;
  1664. dev->qdss.align_virtual_addr =
  1665. mem_addr->align_virtual_addr;
  1666. dev->qdss.mem_size = ALIGNED_QDSS_SIZE;
  1667. dev->qdss.mem_data = mem_addr->mem_data;
  1668. }
  1669. }
  1670. if (dev->qdss.align_virtual_addr) {
  1671. qdss =
  1672. (struct cvp_hfi_mem_map_table *)dev->qdss.align_virtual_addr;
  1673. qdss->mem_map_num_entries = num_entries;
  1674. mem_map_table_base_addr = dev->qdss.align_device_addr +
  1675. sizeof(struct cvp_hfi_mem_map_table);
  1676. qdss->mem_map_table_base_addr = mem_map_table_base_addr;
  1677. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1678. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1679. if (!cb) {
  1680. dprintk(CVP_ERR,
  1681. "%s: failed to get context bank\n", __func__);
  1682. return -EINVAL;
  1683. }
  1684. rc = __get_qdss_iommu_virtual_addr(dev, mem_map, cb->domain);
  1685. if (rc) {
  1686. dprintk(CVP_ERR,
  1687. "IOMMU mapping failed, Freeing qdss memdata\n");
  1688. __smem_free(dev, &dev->qdss.mem_data);
  1689. dev->qdss.align_virtual_addr = NULL;
  1690. dev->qdss.align_device_addr = 0;
  1691. }
  1692. }
  1693. dsp_hfi_queue_init:
  1694. rc = __interface_dsp_queues_init(dev);
  1695. if (rc) {
  1696. dprintk(CVP_ERR, "dsp_queues_init failed\n");
  1697. goto fail_alloc_queue;
  1698. }
  1699. __setup_ucregion_memory_map(dev);
  1700. return 0;
  1701. fail_alloc_queue:
  1702. return -ENOMEM;
  1703. }
  1704. static int __sys_set_debug(struct iris_hfi_device *device, u32 debug)
  1705. {
  1706. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1707. int rc = 0;
  1708. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1709. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1710. rc = call_hfi_pkt_op(device, sys_debug_config, pkt, debug);
  1711. if (rc) {
  1712. dprintk(CVP_WARN,
  1713. "Debug mode setting to FW failed\n");
  1714. return -ENOTEMPTY;
  1715. }
  1716. if (__iface_cmdq_write(device, pkt))
  1717. return -ENOTEMPTY;
  1718. return 0;
  1719. }
  1720. static int __sys_set_idle_indicator(struct iris_hfi_device *device,
  1721. bool enable)
  1722. {
  1723. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1724. int rc = 0;
  1725. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1726. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1727. rc = call_hfi_pkt_op(device, sys_set_idle_indicator, pkt, enable);
  1728. if (__iface_cmdq_write(device, pkt))
  1729. return -ENOTEMPTY;
  1730. return 0;
  1731. }
  1732. static int __sys_set_coverage(struct iris_hfi_device *device, u32 mode)
  1733. {
  1734. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1735. int rc = 0;
  1736. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1737. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1738. rc = call_hfi_pkt_op(device, sys_coverage_config,
  1739. pkt, mode);
  1740. if (rc) {
  1741. dprintk(CVP_WARN,
  1742. "Coverage mode setting to FW failed\n");
  1743. return -ENOTEMPTY;
  1744. }
  1745. if (__iface_cmdq_write(device, pkt)) {
  1746. dprintk(CVP_WARN, "Failed to send coverage pkt to f/w\n");
  1747. return -ENOTEMPTY;
  1748. }
  1749. return 0;
  1750. }
  1751. static int __sys_set_power_control(struct iris_hfi_device *device,
  1752. bool enable)
  1753. {
  1754. struct regulator_info *rinfo;
  1755. bool supported = false;
  1756. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1757. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1758. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1759. iris_hfi_for_each_regulator(device, rinfo) {
  1760. if (rinfo->has_hw_power_collapse) {
  1761. supported = true;
  1762. break;
  1763. }
  1764. }
  1765. if (!supported)
  1766. return 0;
  1767. call_hfi_pkt_op(device, sys_power_control, pkt, enable);
  1768. if (__iface_cmdq_write(device, pkt))
  1769. return -ENOTEMPTY;
  1770. return 0;
  1771. }
  1772. static void cvp_pm_qos_update(struct iris_hfi_device *device, bool vote_on)
  1773. {
  1774. u32 latency, off_vote_cnt;
  1775. int i, err = 0;
  1776. spin_lock(&device->res->pm_qos.lock);
  1777. off_vote_cnt = device->res->pm_qos.off_vote_cnt;
  1778. spin_unlock(&device->res->pm_qos.lock);
  1779. if (vote_on && off_vote_cnt)
  1780. return;
  1781. latency = vote_on ? device->res->pm_qos.latency_us :
  1782. PM_QOS_RESUME_LATENCY_DEFAULT_VALUE;
  1783. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  1784. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  1785. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  1786. continue;
  1787. err = dev_pm_qos_update_request(
  1788. &device->res->pm_qos.pm_qos_hdls[i],
  1789. latency);
  1790. if (err < 0) {
  1791. if (vote_on) {
  1792. dprintk(CVP_WARN,
  1793. "pm qos on failed %d\n", err);
  1794. } else {
  1795. dprintk(CVP_WARN,
  1796. "pm qos off failed %d\n", err);
  1797. }
  1798. }
  1799. }
  1800. }
  1801. static int iris_pm_qos_update(void *device)
  1802. {
  1803. struct iris_hfi_device *dev;
  1804. if (!device) {
  1805. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  1806. return -ENODEV;
  1807. }
  1808. dev = device;
  1809. mutex_lock(&dev->lock);
  1810. cvp_pm_qos_update(dev, true);
  1811. mutex_unlock(&dev->lock);
  1812. return 0;
  1813. }
  1814. static int __hwfence_regs_map(struct iris_hfi_device *device)
  1815. {
  1816. int rc = 0;
  1817. struct context_bank_info *cb;
  1818. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1819. if (!cb) {
  1820. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1821. return -EINVAL;
  1822. }
  1823. if (device->res->reg_mappings.ipclite_phyaddr != 0) {
  1824. rc = iommu_map(cb->domain,
  1825. device->res->reg_mappings.ipclite_iova,
  1826. device->res->reg_mappings.ipclite_phyaddr,
  1827. device->res->reg_mappings.ipclite_size,
  1828. IOMMU_READ | IOMMU_WRITE);
  1829. if (rc) {
  1830. dprintk(CVP_ERR, "map ipclite fail %d %#x %#x %#x\n",
  1831. rc, device->res->reg_mappings.ipclite_iova,
  1832. device->res->reg_mappings.ipclite_phyaddr,
  1833. device->res->reg_mappings.ipclite_size);
  1834. return rc;
  1835. }
  1836. }
  1837. if (device->res->reg_mappings.hwmutex_phyaddr != 0) {
  1838. rc = iommu_map(cb->domain,
  1839. device->res->reg_mappings.hwmutex_iova,
  1840. device->res->reg_mappings.hwmutex_phyaddr,
  1841. device->res->reg_mappings.hwmutex_size,
  1842. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1843. if (rc) {
  1844. dprintk(CVP_ERR, "map hwmutex fail %d %#x %#x %#x\n",
  1845. rc, device->res->reg_mappings.hwmutex_iova,
  1846. device->res->reg_mappings.hwmutex_phyaddr,
  1847. device->res->reg_mappings.hwmutex_size);
  1848. return rc;
  1849. }
  1850. }
  1851. if (device->res->reg_mappings.aon_phyaddr != 0) {
  1852. rc = iommu_map(cb->domain,
  1853. device->res->reg_mappings.aon_iova,
  1854. device->res->reg_mappings.aon_phyaddr,
  1855. device->res->reg_mappings.aon_size,
  1856. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1857. if (rc) {
  1858. dprintk(CVP_ERR, "map aon fail %d %#x %#x %#x\n",
  1859. rc, device->res->reg_mappings.aon_iova,
  1860. device->res->reg_mappings.aon_phyaddr,
  1861. device->res->reg_mappings.aon_size);
  1862. return rc;
  1863. }
  1864. }
  1865. if (device->res->reg_mappings.timer_phyaddr != 0) {
  1866. rc = iommu_map(cb->domain,
  1867. device->res->reg_mappings.timer_iova,
  1868. device->res->reg_mappings.timer_phyaddr,
  1869. device->res->reg_mappings.timer_size,
  1870. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1871. if (rc) {
  1872. dprintk(CVP_ERR, "map timer fail %d %#x %#x %#x\n",
  1873. rc, device->res->reg_mappings.timer_iova,
  1874. device->res->reg_mappings.timer_phyaddr,
  1875. device->res->reg_mappings.timer_size);
  1876. return rc;
  1877. }
  1878. }
  1879. return rc;
  1880. }
  1881. static int __hwfence_regs_unmap(struct iris_hfi_device *device)
  1882. {
  1883. int rc = 0;
  1884. struct context_bank_info *cb;
  1885. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1886. if (!cb) {
  1887. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1888. return -EINVAL;
  1889. }
  1890. if (device->res->reg_mappings.ipclite_iova != 0) {
  1891. iommu_unmap(cb->domain,
  1892. device->res->reg_mappings.ipclite_iova,
  1893. device->res->reg_mappings.ipclite_size);
  1894. }
  1895. if (device->res->reg_mappings.hwmutex_iova != 0) {
  1896. iommu_unmap(cb->domain,
  1897. device->res->reg_mappings.hwmutex_iova,
  1898. device->res->reg_mappings.hwmutex_size);
  1899. }
  1900. if (device->res->reg_mappings.aon_iova != 0) {
  1901. iommu_unmap(cb->domain,
  1902. device->res->reg_mappings.aon_iova,
  1903. device->res->reg_mappings.aon_size);
  1904. }
  1905. if (device->res->reg_mappings.timer_iova != 0) {
  1906. iommu_unmap(cb->domain,
  1907. device->res->reg_mappings.timer_iova,
  1908. device->res->reg_mappings.timer_size);
  1909. }
  1910. return rc;
  1911. }
  1912. static int iris_hfi_core_init(void *device)
  1913. {
  1914. int rc = 0;
  1915. u32 ipcc_iova;
  1916. struct cvp_hfi_cmd_sys_init_packet pkt;
  1917. struct cvp_hfi_cmd_sys_get_property_packet version_pkt;
  1918. struct iris_hfi_device *dev;
  1919. if (!device) {
  1920. dprintk(CVP_ERR, "Invalid device\n");
  1921. return -ENODEV;
  1922. }
  1923. dev = device;
  1924. dprintk(CVP_CORE, "Core initializing\n");
  1925. pm_stay_awake(dev->res->pdev->dev.parent);
  1926. mutex_lock(&dev->lock);
  1927. dev->bus_vote.data =
  1928. kzalloc(sizeof(struct cvp_bus_vote_data), GFP_KERNEL);
  1929. if (!dev->bus_vote.data) {
  1930. dprintk(CVP_ERR, "Bus vote data memory is not allocated\n");
  1931. rc = -ENOMEM;
  1932. goto err_no_mem;
  1933. }
  1934. dev->bus_vote.data_count = 1;
  1935. dev->bus_vote.data->power_mode = CVP_POWER_TURBO;
  1936. __hwfence_regs_map(dev);
  1937. rc = __power_on_init(dev);
  1938. if (rc) {
  1939. dprintk(CVP_ERR, "Failed to power on init EVA\n");
  1940. goto err_load_fw;
  1941. }
  1942. rc = cvp_synx_recover();
  1943. if (rc) {
  1944. dprintk(CVP_ERR, "Failed to recover synx\n");
  1945. goto err_core_init;
  1946. }
  1947. /* mmrm registration */
  1948. if (msm_cvp_mmrm_enabled) {
  1949. rc = msm_cvp_mmrm_register(device);
  1950. if (rc) {
  1951. dprintk(CVP_ERR, "Failed to register mmrm client\n");
  1952. goto err_core_init;
  1953. }
  1954. }
  1955. __set_state(dev, IRIS_STATE_INIT);
  1956. dev->reg_dumped = false;
  1957. dprintk(CVP_CORE, "Dev_Virt: %pa, Reg_Virt: %pK\n",
  1958. &dev->cvp_hal_data->firmware_base,
  1959. dev->cvp_hal_data->register_base);
  1960. rc = __interface_queues_init(dev);
  1961. if (rc) {
  1962. dprintk(CVP_ERR, "failed to init queues\n");
  1963. rc = -ENOMEM;
  1964. goto err_core_init;
  1965. }
  1966. cvp_register_va_md_region();
  1967. // Add node for dev struct
  1968. add_va_node_to_list(CVP_QUEUE_DUMP, dev,
  1969. sizeof(struct iris_hfi_device),
  1970. "iris_hfi_device-dev", false);
  1971. add_queue_header_to_va_md_list((void*)dev);
  1972. add_hfi_queue_to_va_md_list((void*)dev);
  1973. rc = msm_cvp_map_ipcc_regs(&ipcc_iova);
  1974. if (!rc) {
  1975. dprintk(CVP_CORE, "IPCC iova 0x%x\n", ipcc_iova);
  1976. __write_register(dev, CVP_MMAP_ADDR, ipcc_iova);
  1977. }
  1978. rc = __load_fw(dev);
  1979. if (rc) {
  1980. dprintk(CVP_ERR, "Failed to load Iris FW\n");
  1981. goto err_core_init;
  1982. }
  1983. rc = __boot_firmware(dev);
  1984. if (rc) {
  1985. dprintk(CVP_ERR, "Failed to start core\n");
  1986. rc = -ENODEV;
  1987. goto err_core_init;
  1988. }
  1989. dev->version = __read_register(dev, CVP_VERSION_INFO);
  1990. rc = call_hfi_pkt_op(dev, sys_init, &pkt, 0);
  1991. if (rc) {
  1992. dprintk(CVP_ERR, "Failed to create sys init pkt\n");
  1993. goto err_core_init;
  1994. }
  1995. if (__iface_cmdq_write(dev, &pkt)) {
  1996. rc = -ENOTEMPTY;
  1997. goto err_core_init;
  1998. }
  1999. rc = call_hfi_pkt_op(dev, sys_image_version, &version_pkt);
  2000. if (rc || __iface_cmdq_write(dev, &version_pkt))
  2001. dprintk(CVP_WARN, "Failed to send image version pkt to f/w\n");
  2002. __sys_set_debug(device, msm_cvp_fw_debug);
  2003. __enable_subcaches(device);
  2004. __set_subcaches(device);
  2005. __set_ubwc_config(device);
  2006. __sys_set_idle_indicator(device, true);
  2007. if (dev->res->pm_qos.latency_us) {
  2008. int err = 0;
  2009. u32 i, cpu;
  2010. dev->res->pm_qos.pm_qos_hdls = kcalloc(
  2011. dev->res->pm_qos.silver_count,
  2012. sizeof(struct dev_pm_qos_request),
  2013. GFP_KERNEL);
  2014. if (!dev->res->pm_qos.pm_qos_hdls) {
  2015. dprintk(CVP_WARN, "Failed allocate pm_qos_hdls\n");
  2016. goto pm_qos_bail;
  2017. }
  2018. for (i = 0; i < dev->res->pm_qos.silver_count; i++) {
  2019. cpu = dev->res->pm_qos.silver_cores[i];
  2020. if (!cpu_possible(cpu))
  2021. continue;
  2022. err = dev_pm_qos_add_request(
  2023. get_cpu_device(cpu),
  2024. &dev->res->pm_qos.pm_qos_hdls[i],
  2025. DEV_PM_QOS_RESUME_LATENCY,
  2026. dev->res->pm_qos.latency_us);
  2027. if (err < 0)
  2028. dprintk(CVP_WARN,
  2029. "%s pm_qos_add_req %d failed\n",
  2030. __func__, i);
  2031. }
  2032. }
  2033. pm_qos_bail:
  2034. mutex_unlock(&dev->lock);
  2035. cvp_dsp_send_hfi_queue();
  2036. pm_relax(dev->res->pdev->dev.parent);
  2037. dprintk(CVP_CORE, "Core inited successfully\n");
  2038. return 0;
  2039. err_core_init:
  2040. __set_state(dev, IRIS_STATE_DEINIT);
  2041. __unload_fw(dev);
  2042. if (dev->mmrm_cvp)
  2043. {
  2044. msm_cvp_mmrm_deregister(dev);
  2045. }
  2046. err_load_fw:
  2047. __hwfence_regs_unmap(dev);
  2048. err_no_mem:
  2049. dprintk(CVP_ERR, "Core init failed\n");
  2050. mutex_unlock(&dev->lock);
  2051. pm_relax(dev->res->pdev->dev.parent);
  2052. return rc;
  2053. }
  2054. static int iris_hfi_core_release(void *dev)
  2055. {
  2056. int rc = 0, i;
  2057. struct iris_hfi_device *device = dev;
  2058. struct cvp_hal_session *session, *next;
  2059. struct dev_pm_qos_request *qos_hdl;
  2060. u32 ipcc_iova;
  2061. if (!device) {
  2062. dprintk(CVP_ERR, "invalid device\n");
  2063. return -ENODEV;
  2064. }
  2065. mutex_lock(&device->lock);
  2066. dprintk(CVP_WARN, "Core releasing\n");
  2067. if (device->res->pm_qos.latency_us &&
  2068. device->res->pm_qos.pm_qos_hdls) {
  2069. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  2070. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  2071. continue;
  2072. qos_hdl = &device->res->pm_qos.pm_qos_hdls[i];
  2073. if ((qos_hdl != NULL) && dev_pm_qos_request_active(qos_hdl))
  2074. dev_pm_qos_remove_request(qos_hdl);
  2075. }
  2076. kfree(device->res->pm_qos.pm_qos_hdls);
  2077. device->res->pm_qos.pm_qos_hdls = NULL;
  2078. }
  2079. __resume(device);
  2080. __set_state(device, IRIS_STATE_DEINIT);
  2081. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  2082. if (rc)
  2083. dprintk(CVP_WARN, "Failed to suspend cvp FW%d\n", rc);
  2084. __dsp_shutdown(device);
  2085. __disable_subcaches(device);
  2086. ipcc_iova = __read_register(device, CVP_MMAP_ADDR);
  2087. msm_cvp_unmap_ipcc_regs(ipcc_iova);
  2088. __unload_fw(device);
  2089. __hwfence_regs_unmap(device);
  2090. if (msm_cvp_mmrm_enabled) {
  2091. rc = msm_cvp_mmrm_deregister(device);
  2092. if (rc) {
  2093. dprintk(CVP_ERR,
  2094. "%s: Failed msm_cvp_mmrm_deregister:%d\n",
  2095. __func__, rc);
  2096. }
  2097. }
  2098. /* unlink all sessions from device */
  2099. list_for_each_entry_safe(session, next, &device->sess_head, list) {
  2100. list_del(&session->list);
  2101. session->device = NULL;
  2102. }
  2103. dprintk(CVP_CORE, "Core released successfully\n");
  2104. mutex_unlock(&device->lock);
  2105. return rc;
  2106. }
  2107. static void __core_clear_interrupt(struct iris_hfi_device *device)
  2108. {
  2109. u32 intr_status = 0, mask = 0;
  2110. if (!device) {
  2111. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2112. return;
  2113. }
  2114. intr_status = __read_register(device, CVP_WRAPPER_INTR_STATUS);
  2115. mask = (CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK | CVP_FATAL_INTR_BMSK);
  2116. if (intr_status & mask) {
  2117. device->intr_status |= intr_status;
  2118. device->reg_count++;
  2119. dprintk(CVP_CORE,
  2120. "INTERRUPT for device: %pK: times: %d status: %d\n",
  2121. device, device->reg_count, intr_status);
  2122. } else {
  2123. device->spur_count++;
  2124. }
  2125. __write_register(device, CVP_CPU_CS_A2HSOFTINTCLR, 1);
  2126. }
  2127. static int iris_hfi_core_trigger_ssr(void *device,
  2128. enum hal_ssr_trigger_type type)
  2129. {
  2130. struct cvp_hfi_cmd_sys_test_ssr_packet pkt;
  2131. int rc = 0;
  2132. struct iris_hfi_device *dev;
  2133. cvp_free_va_md_list();
  2134. if (!device) {
  2135. dprintk(CVP_ERR, "invalid device\n");
  2136. return -ENODEV;
  2137. }
  2138. dev = device;
  2139. if (mutex_trylock(&dev->lock)) {
  2140. rc = call_hfi_pkt_op(dev, ssr_cmd, type, &pkt);
  2141. if (rc) {
  2142. dprintk(CVP_ERR, "%s: failed to create packet\n",
  2143. __func__);
  2144. goto err_create_pkt;
  2145. }
  2146. if (__iface_cmdq_write(dev, &pkt))
  2147. rc = -ENOTEMPTY;
  2148. } else {
  2149. return -EAGAIN;
  2150. }
  2151. err_create_pkt:
  2152. mutex_unlock(&dev->lock);
  2153. return rc;
  2154. }
  2155. static void __set_default_sys_properties(struct iris_hfi_device *device)
  2156. {
  2157. if (__sys_set_debug(device, msm_cvp_fw_debug))
  2158. dprintk(CVP_WARN, "Setting fw_debug msg ON failed\n");
  2159. if (__sys_set_power_control(device, msm_cvp_fw_low_power_mode))
  2160. dprintk(CVP_WARN, "Setting h/w power collapse ON failed\n");
  2161. }
  2162. static void __session_clean(struct cvp_hal_session *session)
  2163. {
  2164. struct cvp_hal_session *temp, *next;
  2165. struct iris_hfi_device *device;
  2166. if (!session || !session->device) {
  2167. dprintk(CVP_WARN, "%s: invalid params\n", __func__);
  2168. return;
  2169. }
  2170. device = session->device;
  2171. dprintk(CVP_SESS, "deleted the session: %pK\n", session);
  2172. /*
  2173. * session might have been removed from the device list in
  2174. * core_release, so check and remove if it is in the list
  2175. */
  2176. list_for_each_entry_safe(temp, next, &device->sess_head, list) {
  2177. if (session == temp) {
  2178. list_del(&session->list);
  2179. break;
  2180. }
  2181. }
  2182. /* Poison the session handle with zeros */
  2183. *session = (struct cvp_hal_session){ {0} };
  2184. kfree(session);
  2185. }
  2186. static int iris_hfi_session_clean(void *session)
  2187. {
  2188. struct cvp_hal_session *sess_close;
  2189. struct iris_hfi_device *device;
  2190. if (!session) {
  2191. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2192. return -EINVAL;
  2193. }
  2194. sess_close = session;
  2195. device = sess_close->device;
  2196. if (!device) {
  2197. dprintk(CVP_ERR, "Invalid device handle %s\n", __func__);
  2198. return -EINVAL;
  2199. }
  2200. mutex_lock(&device->lock);
  2201. __session_clean(sess_close);
  2202. mutex_unlock(&device->lock);
  2203. return 0;
  2204. }
  2205. static int iris_debug_hook(void *device)
  2206. {
  2207. struct iris_hfi_device *dev = device;
  2208. u32 val;
  2209. if (!device) {
  2210. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  2211. return -ENODEV;
  2212. }
  2213. //__write_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0x11);
  2214. //__write_register(dev, CVP_WRAPPER_TZ_CPU_CLOCK_CONFIG, 0x1);
  2215. dprintk(CVP_ERR, "Halt Tensilica and core and axi\n");
  2216. return 0;
  2217. /******* FDU & MPU *****/
  2218. #define CVP0_CVP_SS_FDU_SECURE_ENABLE 0x90
  2219. #define CVP0_CVP_SS_MPU_SECURE_ENABLE 0x94
  2220. #define CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE 0xA0
  2221. #define CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE 0xA4
  2222. #define CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE 0xA8
  2223. #define CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE 0xAC
  2224. val = __read_register(dev, CVP0_CVP_SS_FDU_SECURE_ENABLE);
  2225. dprintk(CVP_ERR, "FDU_SECURE_ENABLE %#x\n", val);
  2226. val = __read_register(dev, CVP0_CVP_SS_MPU_SECURE_ENABLE);
  2227. dprintk(CVP_ERR, "MPU_SECURE_ENABLE %#x\n", val);
  2228. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE);
  2229. dprintk(CVP_ERR, "ARP_THREAD_0_SECURE_ENABLE %#x\n", val);
  2230. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE);
  2231. dprintk(CVP_ERR, "ARP_THREAD_1_SECURE_ENABLE %#x\n", val);
  2232. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE);
  2233. dprintk(CVP_ERR, "ARP_THREAD_2_SECURE_ENABLE %#x\n", val);
  2234. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE);
  2235. dprintk(CVP_ERR, "ARP_THREAD_3_SECURE_ENABLE %#x\n", val);
  2236. if (true)
  2237. return 0;
  2238. /***** GCE *******
  2239. * Bit 0 of below register is CDM secure enable for GCE
  2240. * CDM buffer will be in CB4 if set
  2241. */
  2242. #define CVP_GCE_GCE_SS_CP_CTL 0x51100
  2243. /* STATUS bit0 && CFG bit 4 of below register set,
  2244. * expect pixel buffers in CB3,
  2245. * otherwise in CB0
  2246. * CFG bit 9:8 b01 -> LMC input in CB3
  2247. * CFG bit 9:8 b10 -> LMC input in CB4
  2248. */
  2249. #define CVP_GCE0_CP_STATUS 0x51080
  2250. #define CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG 0x52020
  2251. val = __read_register(dev, CVP_GCE_GCE_SS_CP_CTL);
  2252. dprintk(CVP_ERR, "CVP_GCE_GCE_SS_CP_CTL %#x\n", val);
  2253. val = __read_register(dev, CVP_GCE0_CP_STATUS);
  2254. dprintk(CVP_ERR, "CVP_GCE0_CP_STATUS %#x\n", val);
  2255. val = __read_register(dev, CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG);
  2256. dprintk(CVP_ERR, "CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2257. /***** RGE *****
  2258. * Bit 0 of below regiser is CDM secure enable for RGE
  2259. * CDM buffer to be in CB4 i fset
  2260. */
  2261. #define CVP_RGE0_TOPRGE_CP_CTL 0x31010
  2262. /* CFG bit 4 && IN bit 0:
  2263. * if both are set, expect CB3 or CB4 depending on IN 6:4 field
  2264. * either is clear, expect CB0
  2265. */
  2266. #define CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG 0x32020
  2267. #define CVP_RGE0_TOPSPARE_IN 0x311F4
  2268. val = __read_register(dev, CVP_RGE0_TOPRGE_CP_CTL);
  2269. dprintk(CVP_ERR, "CVP_RGE0_TOPRGE_CP_CTL %#x\n", val);
  2270. val = __read_register(dev, CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2271. dprintk(CVP_ERR, "CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2272. val = __read_register(dev, CVP_RGE0_TOPSPARE_IN);
  2273. dprintk(CVP_ERR, "CVP_RGE0_TOPSPARE_IN %#x\n", val);
  2274. /****** VADL ******
  2275. * Bit 0 of below register is CDM secure enable for VADL
  2276. * CDM buffer will bei in CB4 if set
  2277. */
  2278. #define CVP_VADL0_VADL_SS_CP_CTL 0x21010
  2279. /* Below registers are used the same way as RGE */
  2280. #define CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG 0x22020
  2281. #define CVP_VADL0_SPARE_IN 0x211F4
  2282. val = __read_register(dev, CVP_VADL0_VADL_SS_CP_CTL);
  2283. dprintk(CVP_ERR, "CVP_VADL0_VADL_SS_CP_CTL %#x\n", val);
  2284. val = __read_register(dev, CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2285. dprintk(CVP_ERR, "CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2286. val = __read_register(dev, CVP_VADL0_SPARE_IN);
  2287. dprintk(CVP_ERR, "CVP_VADL0_SPARE_IN %#x\n", val);
  2288. /****** ITOF *****
  2289. * Below registers are used the same way as RGE
  2290. */
  2291. #define CVP_ITOF0_TOF_SS_CP_CTL 0x41010
  2292. #define CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG 0x42020
  2293. #define CVP_ITOF0_TOF_SS_SPARE_IN 0x411F4
  2294. val = __read_register(dev, CVP_ITOF0_TOF_SS_CP_CTL);
  2295. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_CP_CTL %#x\n", val);
  2296. val = __read_register(dev, CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2297. dprintk(CVP_ERR, "CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2298. val = __read_register(dev, CVP_ITOF0_TOF_SS_SPARE_IN);
  2299. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_SPARE_IN %#x\n", val);
  2300. return 0;
  2301. }
  2302. static int iris_hfi_session_init(void *device, void *session_id,
  2303. void **new_session)
  2304. {
  2305. struct cvp_hfi_cmd_sys_session_init_packet pkt;
  2306. struct iris_hfi_device *dev;
  2307. struct cvp_hal_session *s;
  2308. if (!device || !new_session) {
  2309. dprintk(CVP_ERR, "%s - invalid input\n", __func__);
  2310. return -EINVAL;
  2311. }
  2312. dev = device;
  2313. mutex_lock(&dev->lock);
  2314. s = kzalloc(sizeof(*s), GFP_KERNEL);
  2315. if (!s) {
  2316. dprintk(CVP_ERR, "new session fail: Out of memory\n");
  2317. goto err_session_init_fail;
  2318. }
  2319. s->session_id = session_id;
  2320. s->device = dev;
  2321. dprintk(CVP_SESS,
  2322. "%s: inst %pK, session %pK\n", __func__, session_id, s);
  2323. list_add_tail(&s->list, &dev->sess_head);
  2324. __set_default_sys_properties(device);
  2325. if (call_hfi_pkt_op(dev, session_init, &pkt, s)) {
  2326. dprintk(CVP_ERR, "session_init: failed to create packet\n");
  2327. goto err_session_init_fail;
  2328. }
  2329. *new_session = s;
  2330. if (__iface_cmdq_write(dev, &pkt))
  2331. goto err_session_init_fail;
  2332. mutex_unlock(&dev->lock);
  2333. return 0;
  2334. err_session_init_fail:
  2335. if (s)
  2336. __session_clean(s);
  2337. *new_session = NULL;
  2338. mutex_unlock(&dev->lock);
  2339. return -EINVAL;
  2340. }
  2341. static int __send_session_cmd(struct cvp_hal_session *session, int pkt_type)
  2342. {
  2343. struct cvp_hal_session_cmd_pkt pkt;
  2344. int rc = 0;
  2345. struct iris_hfi_device *device = session->device;
  2346. if (!__is_session_valid(device, session, __func__))
  2347. return -ECONNRESET;
  2348. rc = call_hfi_pkt_op(device, session_cmd,
  2349. &pkt, pkt_type, session);
  2350. if (rc == -EPERM)
  2351. return 0;
  2352. if (rc) {
  2353. dprintk(CVP_ERR, "send session cmd: create pkt failed\n");
  2354. goto err_create_pkt;
  2355. }
  2356. if (__iface_cmdq_write(session->device, &pkt))
  2357. rc = -ENOTEMPTY;
  2358. err_create_pkt:
  2359. return rc;
  2360. }
  2361. static int iris_hfi_session_end(void *session)
  2362. {
  2363. struct cvp_hal_session *sess;
  2364. struct iris_hfi_device *device;
  2365. int rc = 0;
  2366. if (!session) {
  2367. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2368. return -EINVAL;
  2369. }
  2370. sess = session;
  2371. device = sess->device;
  2372. if (!device) {
  2373. dprintk(CVP_ERR, "Invalid session %s\n", __func__);
  2374. return -EINVAL;
  2375. }
  2376. mutex_lock(&device->lock);
  2377. if (msm_cvp_fw_coverage) {
  2378. if (__sys_set_coverage(sess->device, msm_cvp_fw_coverage))
  2379. dprintk(CVP_WARN, "Fw_coverage msg ON failed\n");
  2380. }
  2381. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_END);
  2382. mutex_unlock(&device->lock);
  2383. return rc;
  2384. }
  2385. static int iris_hfi_session_abort(void *sess)
  2386. {
  2387. struct cvp_hal_session *session = sess;
  2388. struct iris_hfi_device *device;
  2389. int rc = 0;
  2390. if (!session || !session->device) {
  2391. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2392. return -EINVAL;
  2393. }
  2394. device = session->device;
  2395. mutex_lock(&device->lock);
  2396. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_ABORT);
  2397. mutex_unlock(&device->lock);
  2398. return rc;
  2399. }
  2400. static int iris_hfi_session_set_buffers(void *sess, u32 iova, u32 size)
  2401. {
  2402. struct cvp_hfi_cmd_session_set_buffers_packet pkt;
  2403. int rc = 0;
  2404. struct cvp_hal_session *session = sess;
  2405. struct iris_hfi_device *device;
  2406. if (!session || !session->device || !iova || !size) {
  2407. dprintk(CVP_ERR, "Invalid Params\n");
  2408. return -EINVAL;
  2409. }
  2410. device = session->device;
  2411. mutex_lock(&device->lock);
  2412. if (!__is_session_valid(device, session, __func__)) {
  2413. rc = -ECONNRESET;
  2414. goto err_create_pkt;
  2415. }
  2416. rc = call_hfi_pkt_op(device, session_set_buffers,
  2417. &pkt, session, iova, size);
  2418. if (rc) {
  2419. dprintk(CVP_ERR, "set buffers: failed to create packet\n");
  2420. goto err_create_pkt;
  2421. }
  2422. if (__iface_cmdq_write(session->device, &pkt))
  2423. rc = -ENOTEMPTY;
  2424. err_create_pkt:
  2425. mutex_unlock(&device->lock);
  2426. return rc;
  2427. }
  2428. static int iris_hfi_session_release_buffers(void *sess)
  2429. {
  2430. struct cvp_session_release_buffers_packet pkt;
  2431. int rc = 0;
  2432. struct cvp_hal_session *session = sess;
  2433. struct iris_hfi_device *device;
  2434. if (!session || !session->device) {
  2435. dprintk(CVP_ERR, "Invalid Params\n");
  2436. return -EINVAL;
  2437. }
  2438. device = session->device;
  2439. mutex_lock(&device->lock);
  2440. if (!__is_session_valid(device, session, __func__)) {
  2441. rc = -ECONNRESET;
  2442. goto err_create_pkt;
  2443. }
  2444. rc = call_hfi_pkt_op(device, session_release_buffers, &pkt, session);
  2445. if (rc) {
  2446. dprintk(CVP_ERR, "release buffers: failed to create packet\n");
  2447. goto err_create_pkt;
  2448. }
  2449. if (__iface_cmdq_write(session->device, &pkt))
  2450. rc = -ENOTEMPTY;
  2451. err_create_pkt:
  2452. mutex_unlock(&device->lock);
  2453. return rc;
  2454. }
  2455. static int iris_hfi_session_send(void *sess,
  2456. struct eva_kmd_hfi_packet *in_pkt)
  2457. {
  2458. int rc = 0;
  2459. struct eva_kmd_hfi_packet pkt;
  2460. struct cvp_hal_session *session = sess;
  2461. struct iris_hfi_device *device;
  2462. if (!session || !session->device) {
  2463. dprintk(CVP_ERR, "invalid session");
  2464. return -ENODEV;
  2465. }
  2466. device = session->device;
  2467. mutex_lock(&device->lock);
  2468. if (!__is_session_valid(device, session, __func__)) {
  2469. rc = -ECONNRESET;
  2470. goto err_send_pkt;
  2471. }
  2472. rc = call_hfi_pkt_op(device, session_send,
  2473. &pkt, session, in_pkt);
  2474. if (rc) {
  2475. dprintk(CVP_ERR,
  2476. "failed to create pkt\n");
  2477. goto err_send_pkt;
  2478. }
  2479. if (__iface_cmdq_write(session->device, &pkt))
  2480. rc = -ENOTEMPTY;
  2481. err_send_pkt:
  2482. mutex_unlock(&device->lock);
  2483. return rc;
  2484. return rc;
  2485. }
  2486. static int iris_hfi_session_flush(void *sess)
  2487. {
  2488. struct cvp_hal_session *session = sess;
  2489. struct iris_hfi_device *device;
  2490. int rc = 0;
  2491. if (!session || !session->device) {
  2492. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2493. return -EINVAL;
  2494. }
  2495. device = session->device;
  2496. mutex_lock(&device->lock);
  2497. rc = __send_session_cmd(session, HFI_CMD_SESSION_CVP_FLUSH);
  2498. mutex_unlock(&device->lock);
  2499. return rc;
  2500. }
  2501. static int iris_hfi_session_start(void *sess)
  2502. {
  2503. struct cvp_hal_session *session = sess;
  2504. struct iris_hfi_device *device;
  2505. int rc = 0;
  2506. if (!session || !session->device) {
  2507. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2508. return -EINVAL;
  2509. }
  2510. device = session->device;
  2511. mutex_lock(&device->lock);
  2512. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_START);
  2513. mutex_unlock(&device->lock);
  2514. return rc;
  2515. }
  2516. static int iris_hfi_session_stop(void *sess)
  2517. {
  2518. struct cvp_hal_session *session = sess;
  2519. struct iris_hfi_device *device;
  2520. int rc = 0;
  2521. if (!session || !session->device) {
  2522. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2523. return -EINVAL;
  2524. }
  2525. device = session->device;
  2526. mutex_lock(&device->lock);
  2527. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_STOP);
  2528. mutex_unlock(&device->lock);
  2529. return rc;
  2530. }
  2531. static void __process_fatal_error(
  2532. struct iris_hfi_device *device)
  2533. {
  2534. struct msm_cvp_cb_cmd_done cmd_done = {0};
  2535. device->callback(HAL_SYS_ERROR, &cmd_done);
  2536. }
  2537. static int __prepare_pc(struct iris_hfi_device *device)
  2538. {
  2539. int rc = 0;
  2540. struct cvp_hfi_cmd_sys_pc_prep_packet pkt;
  2541. rc = call_hfi_pkt_op(device, sys_pc_prep, &pkt);
  2542. if (rc) {
  2543. dprintk(CVP_ERR, "Failed to create sys pc prep pkt\n");
  2544. goto err_pc_prep;
  2545. }
  2546. if (__iface_cmdq_write(device, &pkt))
  2547. rc = -ENOTEMPTY;
  2548. if (rc)
  2549. dprintk(CVP_ERR, "Failed to prepare iris for power off");
  2550. err_pc_prep:
  2551. return rc;
  2552. }
  2553. static void iris_hfi_pm_handler(struct work_struct *work)
  2554. {
  2555. int rc = 0;
  2556. struct msm_cvp_core *core;
  2557. struct iris_hfi_device *device;
  2558. core = cvp_driver->cvp_core;
  2559. if (core)
  2560. device = core->dev_ops->hfi_device_data;
  2561. else
  2562. return;
  2563. if (!device) {
  2564. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2565. return;
  2566. }
  2567. dprintk(CVP_PWR,
  2568. "Entering %s\n", __func__);
  2569. /*
  2570. * It is ok to check this variable outside the lock since
  2571. * it is being updated in this context only
  2572. */
  2573. if (device->skip_pc_count >= CVP_MAX_PC_SKIP_COUNT) {
  2574. dprintk(CVP_WARN, "Failed to PC for %d times\n",
  2575. device->skip_pc_count);
  2576. device->skip_pc_count = 0;
  2577. __process_fatal_error(device);
  2578. return;
  2579. }
  2580. mutex_lock(&device->lock);
  2581. if (gfa_cv.state == DSP_SUSPEND)
  2582. rc = __power_collapse(device, true);
  2583. else
  2584. rc = __power_collapse(device, false);
  2585. mutex_unlock(&device->lock);
  2586. switch (rc) {
  2587. case 0:
  2588. device->skip_pc_count = 0;
  2589. /* Cancel pending delayed works if any */
  2590. cancel_delayed_work(&iris_hfi_pm_work);
  2591. dprintk(CVP_PWR, "%s: power collapse successful!\n",
  2592. __func__);
  2593. break;
  2594. case -EBUSY:
  2595. device->skip_pc_count = 0;
  2596. dprintk(CVP_PWR, "%s: retry PC as cvp is busy\n", __func__);
  2597. queue_delayed_work(device->iris_pm_workq,
  2598. &iris_hfi_pm_work, msecs_to_jiffies(
  2599. device->res->msm_cvp_pwr_collapse_delay));
  2600. break;
  2601. case -EAGAIN:
  2602. device->skip_pc_count++;
  2603. dprintk(CVP_WARN, "%s: retry power collapse (count %d)\n",
  2604. __func__, device->skip_pc_count);
  2605. queue_delayed_work(device->iris_pm_workq,
  2606. &iris_hfi_pm_work, msecs_to_jiffies(
  2607. device->res->msm_cvp_pwr_collapse_delay));
  2608. break;
  2609. default:
  2610. dprintk(CVP_ERR, "%s: power collapse failed\n", __func__);
  2611. break;
  2612. }
  2613. }
  2614. static int __power_collapse(struct iris_hfi_device *device, bool force)
  2615. {
  2616. int rc = 0;
  2617. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  2618. int count = 0;
  2619. const int max_tries = 150;
  2620. if (!device) {
  2621. dprintk(CVP_ERR, "%s: invalid params\n", __func__);
  2622. return -EINVAL;
  2623. }
  2624. if (!device->power_enabled) {
  2625. dprintk(CVP_PWR, "%s: Power already disabled\n",
  2626. __func__);
  2627. goto exit;
  2628. }
  2629. rc = __core_in_valid_state(device);
  2630. if (!rc) {
  2631. dprintk(CVP_WARN,
  2632. "Core is in bad state, Skipping power collapse\n");
  2633. return -EINVAL;
  2634. }
  2635. rc = __dsp_suspend(device, force);
  2636. if (rc == -EBUSY)
  2637. goto exit;
  2638. else if (rc)
  2639. goto skip_power_off;
  2640. __flush_debug_queue(device, device->raw_packet);
  2641. pc_ready = __read_register(device, CVP_CTRL_STATUS) &
  2642. CVP_CTRL_STATUS_PC_READY;
  2643. if (!pc_ready) {
  2644. wfi_status = __read_register(device,
  2645. CVP_WRAPPER_CPU_STATUS);
  2646. idle_status = __read_register(device,
  2647. CVP_CTRL_STATUS);
  2648. if (!(wfi_status & BIT(0))) {
  2649. dprintk(CVP_WARN,
  2650. "Skipping PC as wfi_status (%#x) bit not set\n",
  2651. wfi_status);
  2652. goto skip_power_off;
  2653. }
  2654. if (!(idle_status & BIT(30))) {
  2655. dprintk(CVP_WARN,
  2656. "Skipping PC as idle_status (%#x) bit not set\n",
  2657. idle_status);
  2658. goto skip_power_off;
  2659. }
  2660. rc = __prepare_pc(device);
  2661. if (rc) {
  2662. dprintk(CVP_WARN, "Failed PC %d\n", rc);
  2663. goto skip_power_off;
  2664. }
  2665. while (count < max_tries) {
  2666. wfi_status = __read_register(device,
  2667. CVP_WRAPPER_CPU_STATUS);
  2668. pc_ready = __read_register(device,
  2669. CVP_CTRL_STATUS);
  2670. if ((wfi_status & BIT(0)) && (pc_ready &
  2671. CVP_CTRL_STATUS_PC_READY))
  2672. break;
  2673. usleep_range(150, 250);
  2674. count++;
  2675. }
  2676. if (count == max_tries) {
  2677. dprintk(CVP_ERR,
  2678. "Skip PC. Core is not ready (%#x, %#x)\n",
  2679. wfi_status, pc_ready);
  2680. goto skip_power_off;
  2681. }
  2682. } else {
  2683. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  2684. if (!(wfi_status & BIT(0))) {
  2685. dprintk(CVP_WARN,
  2686. "Skip PC as wfi_status (%#x) bit not set\n",
  2687. wfi_status);
  2688. goto skip_power_off;
  2689. }
  2690. }
  2691. rc = __suspend(device);
  2692. if (rc)
  2693. dprintk(CVP_ERR, "Failed __suspend\n");
  2694. exit:
  2695. return rc;
  2696. skip_power_off:
  2697. dprintk(CVP_PWR, "Skip PC(%#x, %#x, %#x)\n",
  2698. wfi_status, idle_status, pc_ready);
  2699. __flush_debug_queue(device, device->raw_packet);
  2700. return -EAGAIN;
  2701. }
  2702. static void __process_sys_error(struct iris_hfi_device *device)
  2703. {
  2704. struct cvp_hfi_sfr_struct *vsfr = NULL;
  2705. vsfr = (struct cvp_hfi_sfr_struct *)device->sfr.align_virtual_addr;
  2706. if (vsfr) {
  2707. void *p = memchr(vsfr->rg_data, '\0', vsfr->bufSize);
  2708. /*
  2709. * SFR isn't guaranteed to be NULL terminated
  2710. * since SYS_ERROR indicates that Iris is in the
  2711. * process of crashing.
  2712. */
  2713. if (p == NULL)
  2714. vsfr->rg_data[vsfr->bufSize - 1] = '\0';
  2715. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2716. vsfr->rg_data);
  2717. }
  2718. }
  2719. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet)
  2720. {
  2721. bool local_packet = false;
  2722. enum cvp_msg_prio log_level = CVP_FW;
  2723. if (!device) {
  2724. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  2725. return;
  2726. }
  2727. if (!packet) {
  2728. packet = kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  2729. if (!packet) {
  2730. dprintk(CVP_ERR, "In %s() Fail to allocate mem\n",
  2731. __func__);
  2732. return;
  2733. }
  2734. local_packet = true;
  2735. /*
  2736. * Local packek is used when something FATAL occurred.
  2737. * It is good to print these logs by default.
  2738. */
  2739. log_level = CVP_ERR;
  2740. }
  2741. #define SKIP_INVALID_PKT(pkt_size, payload_size, pkt_hdr_size) ({ \
  2742. if (pkt_size < pkt_hdr_size || \
  2743. payload_size < MIN_PAYLOAD_SIZE || \
  2744. payload_size > \
  2745. (pkt_size - pkt_hdr_size + sizeof(u8))) { \
  2746. dprintk(CVP_ERR, \
  2747. "%s: invalid msg size - %d\n", \
  2748. __func__, pkt->msg_size); \
  2749. continue; \
  2750. } \
  2751. })
  2752. while (!__iface_dbgq_read(device, packet)) {
  2753. struct cvp_hfi_packet_header *pkt =
  2754. (struct cvp_hfi_packet_header *) packet;
  2755. if (pkt->size < sizeof(struct cvp_hfi_packet_header)) {
  2756. dprintk(CVP_ERR, "Invalid pkt size - %s\n",
  2757. __func__);
  2758. continue;
  2759. }
  2760. if (pkt->packet_type == HFI_MSG_SYS_DEBUG) {
  2761. struct cvp_hfi_msg_sys_debug_packet *pkt =
  2762. (struct cvp_hfi_msg_sys_debug_packet *) packet;
  2763. SKIP_INVALID_PKT(pkt->size,
  2764. pkt->msg_size, sizeof(*pkt));
  2765. /*
  2766. * All fw messages starts with new line character. This
  2767. * causes dprintk to print this message in two lines
  2768. * in the kernel log. Ignoring the first character
  2769. * from the message fixes this to print it in a single
  2770. * line.
  2771. */
  2772. pkt->rg_msg_data[pkt->msg_size-1] = '\0';
  2773. dprintk(log_level, "%s", &pkt->rg_msg_data[1]);
  2774. }
  2775. }
  2776. #undef SKIP_INVALID_PKT
  2777. if (local_packet)
  2778. kfree(packet);
  2779. }
  2780. static bool __is_session_valid(struct iris_hfi_device *device,
  2781. struct cvp_hal_session *session, const char *func)
  2782. {
  2783. struct cvp_hal_session *temp = NULL;
  2784. if (!device || !session)
  2785. goto invalid;
  2786. list_for_each_entry(temp, &device->sess_head, list)
  2787. if (session == temp)
  2788. return true;
  2789. invalid:
  2790. dprintk(CVP_WARN, "%s: device %pK, invalid session %pK\n",
  2791. func, device, session);
  2792. return false;
  2793. }
  2794. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  2795. u32 session_id)
  2796. {
  2797. struct cvp_hal_session *temp = NULL;
  2798. list_for_each_entry(temp, &device->sess_head, list) {
  2799. if (session_id == hash32_ptr(temp))
  2800. return temp;
  2801. }
  2802. return NULL;
  2803. }
  2804. #define _INVALID_MSG_ "Unrecognized MSG (%#x) session (%pK), discarding\n"
  2805. #define _INVALID_STATE_ "Ignore responses from %d to %d invalid state\n"
  2806. #define _DEVFREQ_FAIL_ "Failed to add devfreq device bus %s governor %s: %d\n"
  2807. static void process_system_msg(struct msm_cvp_cb_info *info,
  2808. struct iris_hfi_device *device,
  2809. void *raw_packet)
  2810. {
  2811. struct cvp_hal_sys_init_done sys_init_done = {0};
  2812. switch (info->response_type) {
  2813. case HAL_SYS_ERROR:
  2814. __process_sys_error(device);
  2815. break;
  2816. case HAL_SYS_RELEASE_RESOURCE_DONE:
  2817. dprintk(CVP_CORE, "Received SYS_RELEASE_RESOURCE\n");
  2818. break;
  2819. case HAL_SYS_INIT_DONE:
  2820. dprintk(CVP_CORE, "Received SYS_INIT_DONE\n");
  2821. sys_init_done.capabilities =
  2822. device->sys_init_capabilities;
  2823. cvp_hfi_process_sys_init_done_prop_read(
  2824. (struct cvp_hfi_msg_sys_init_done_packet *)
  2825. raw_packet, &sys_init_done);
  2826. info->response.cmd.data.sys_init_done = sys_init_done;
  2827. break;
  2828. default:
  2829. break;
  2830. }
  2831. }
  2832. static void **get_session_id(struct msm_cvp_cb_info *info)
  2833. {
  2834. void **session_id = NULL;
  2835. /* For session-related packets, validate session */
  2836. switch (info->response_type) {
  2837. case HAL_SESSION_INIT_DONE:
  2838. case HAL_SESSION_END_DONE:
  2839. case HAL_SESSION_ABORT_DONE:
  2840. case HAL_SESSION_START_DONE:
  2841. case HAL_SESSION_STOP_DONE:
  2842. case HAL_SESSION_FLUSH_DONE:
  2843. case HAL_SESSION_SET_BUFFER_DONE:
  2844. case HAL_SESSION_SUSPEND_DONE:
  2845. case HAL_SESSION_RESUME_DONE:
  2846. case HAL_SESSION_SET_PROP_DONE:
  2847. case HAL_SESSION_GET_PROP_DONE:
  2848. case HAL_SESSION_RELEASE_BUFFER_DONE:
  2849. case HAL_SESSION_REGISTER_BUFFER_DONE:
  2850. case HAL_SESSION_UNREGISTER_BUFFER_DONE:
  2851. case HAL_SESSION_PROPERTY_INFO:
  2852. case HAL_SESSION_EVENT_CHANGE:
  2853. case HAL_SESSION_DUMP_NOTIFY:
  2854. case HAL_SESSION_ERROR:
  2855. session_id = &info->response.cmd.session_id;
  2856. break;
  2857. case HAL_RESPONSE_UNUSED:
  2858. default:
  2859. session_id = NULL;
  2860. break;
  2861. }
  2862. return session_id;
  2863. }
  2864. static void print_msg_hdr(void *hdr)
  2865. {
  2866. struct cvp_hfi_msg_session_hdr *new_hdr =
  2867. (struct cvp_hfi_msg_session_hdr *)hdr;
  2868. dprintk(CVP_HFI, "HFI MSG received: %x %x %x %x %x %x %x %#llx\n",
  2869. new_hdr->size, new_hdr->packet_type,
  2870. new_hdr->session_id,
  2871. new_hdr->client_data.transaction_id,
  2872. new_hdr->client_data.data1,
  2873. new_hdr->client_data.data2,
  2874. new_hdr->error_type,
  2875. new_hdr->client_data.kdata);
  2876. }
  2877. static int __response_handler(struct iris_hfi_device *device)
  2878. {
  2879. struct msm_cvp_cb_info *packets;
  2880. int packet_count = 0;
  2881. u8 *raw_packet = NULL;
  2882. bool requeue_pm_work = true;
  2883. if (!device || device->state != IRIS_STATE_INIT)
  2884. return 0;
  2885. packets = device->response_pkt;
  2886. raw_packet = device->raw_packet;
  2887. if (!raw_packet || !packets) {
  2888. dprintk(CVP_ERR,
  2889. "%s: Invalid args : Res pkt = %pK, Raw pkt = %pK\n",
  2890. __func__, packets, raw_packet);
  2891. return 0;
  2892. }
  2893. if (device->intr_status & CVP_FATAL_INTR_BMSK) {
  2894. struct cvp_hfi_sfr_struct *vsfr = (struct cvp_hfi_sfr_struct *)
  2895. device->sfr.align_virtual_addr;
  2896. struct msm_cvp_cb_info info = {
  2897. .response_type = HAL_SYS_WATCHDOG_TIMEOUT,
  2898. .response.cmd = {
  2899. .device_id = 0,
  2900. }
  2901. };
  2902. if (vsfr)
  2903. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2904. vsfr->rg_data);
  2905. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CPU_NOC_BMSK)
  2906. dprintk(CVP_ERR, "Received Xtensa NOC error\n");
  2907. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CORE_NOC_BMSK)
  2908. dprintk(CVP_ERR, "Received CVP core NOC error\n");
  2909. if (device->intr_status & CVP_WRAPPER_INTR_MASK_A2HWD_BMSK)
  2910. dprintk(CVP_ERR, "Received CVP watchdog timeout\n");
  2911. packets[packet_count++] = info;
  2912. goto exit;
  2913. }
  2914. /* Bleed the msg queue dry of packets */
  2915. while (!__iface_msgq_read(device, raw_packet)) {
  2916. void **session_id = NULL;
  2917. struct msm_cvp_cb_info *info = &packets[packet_count++];
  2918. struct cvp_hfi_msg_session_hdr *hdr =
  2919. (struct cvp_hfi_msg_session_hdr *)raw_packet;
  2920. int rc = 0;
  2921. print_msg_hdr(hdr);
  2922. rc = cvp_hfi_process_msg_packet(0, raw_packet, info);
  2923. if (rc) {
  2924. dprintk(CVP_WARN,
  2925. "Corrupt/unknown packet found, discarding\n");
  2926. --packet_count;
  2927. continue;
  2928. } else if (info->response_type == HAL_NO_RESP) {
  2929. --packet_count;
  2930. continue;
  2931. }
  2932. /* Process the packet types that we're interested in */
  2933. process_system_msg(info, device, raw_packet);
  2934. session_id = get_session_id(info);
  2935. /*
  2936. * hfi_process_msg_packet provides a session_id that's a hashed
  2937. * value of struct cvp_hal_session, we need to coerce the hashed
  2938. * value back to pointer that we can use. Ideally, hfi_process\
  2939. * _msg_packet should take care of this, but it doesn't have
  2940. * required information for it
  2941. */
  2942. if (session_id) {
  2943. struct cvp_hal_session *session = NULL;
  2944. if (upper_32_bits((uintptr_t)*session_id) != 0) {
  2945. dprintk(CVP_ERR,
  2946. "Upper 32-bits != 0 for sess_id=%pK\n",
  2947. *session_id);
  2948. }
  2949. session = __get_session(device,
  2950. (u32)(uintptr_t)*session_id);
  2951. if (!session) {
  2952. dprintk(CVP_ERR, _INVALID_MSG_,
  2953. info->response_type,
  2954. *session_id);
  2955. --packet_count;
  2956. continue;
  2957. }
  2958. *session_id = session->session_id;
  2959. }
  2960. if (packet_count >= cvp_max_packets) {
  2961. dprintk(CVP_WARN,
  2962. "Too many packets in message queue!\n");
  2963. break;
  2964. }
  2965. /* do not read packets after sys error packet */
  2966. if (info->response_type == HAL_SYS_ERROR)
  2967. break;
  2968. }
  2969. if (requeue_pm_work && device->res->sw_power_collapsible) {
  2970. cancel_delayed_work(&iris_hfi_pm_work);
  2971. if (!queue_delayed_work(device->iris_pm_workq,
  2972. &iris_hfi_pm_work,
  2973. msecs_to_jiffies(
  2974. device->res->msm_cvp_pwr_collapse_delay))) {
  2975. dprintk(CVP_ERR, "PM work already scheduled\n");
  2976. }
  2977. }
  2978. exit:
  2979. __flush_debug_queue(device, raw_packet);
  2980. return packet_count;
  2981. }
  2982. irqreturn_t iris_hfi_core_work_handler(int irq, void *data)
  2983. {
  2984. struct msm_cvp_core *core;
  2985. struct iris_hfi_device *device;
  2986. int num_responses = 0, i = 0;
  2987. u32 intr_status;
  2988. static bool warning_on = true;
  2989. core = cvp_driver->cvp_core;
  2990. if (core)
  2991. device = core->dev_ops->hfi_device_data;
  2992. else
  2993. return IRQ_HANDLED;
  2994. mutex_lock(&device->lock);
  2995. if (!__core_in_valid_state(device)) {
  2996. if (warning_on) {
  2997. dprintk(CVP_WARN, "%s Core not in init state\n",
  2998. __func__);
  2999. warning_on = false;
  3000. }
  3001. goto err_no_work;
  3002. }
  3003. warning_on = true;
  3004. if (!device->callback) {
  3005. dprintk(CVP_ERR, "No interrupt callback function: %pK\n",
  3006. device);
  3007. goto err_no_work;
  3008. }
  3009. if (__resume(device)) {
  3010. dprintk(CVP_ERR, "%s: Power enable failed\n", __func__);
  3011. goto err_no_work;
  3012. }
  3013. __core_clear_interrupt(device);
  3014. num_responses = __response_handler(device);
  3015. dprintk(CVP_HFI, "%s:: cvp_driver_debug num_responses = %d ",
  3016. __func__, num_responses);
  3017. err_no_work:
  3018. /* Keep the interrupt status before releasing device lock */
  3019. intr_status = device->intr_status;
  3020. mutex_unlock(&device->lock);
  3021. /*
  3022. * Issue the callbacks outside of the locked contex to preserve
  3023. * re-entrancy.
  3024. */
  3025. for (i = 0; !IS_ERR_OR_NULL(device->response_pkt) &&
  3026. i < num_responses; ++i) {
  3027. struct msm_cvp_cb_info *r = &device->response_pkt[i];
  3028. void *rsp = (void *)&r->response;
  3029. if (!__core_in_valid_state(device)) {
  3030. dprintk(CVP_ERR,
  3031. _INVALID_STATE_, (i + 1), num_responses);
  3032. break;
  3033. }
  3034. dprintk(CVP_HFI, "Processing response %d of %d, type %d\n",
  3035. (i + 1), num_responses, r->response_type);
  3036. /* callback = void cvp_handle_cmd_response() */
  3037. device->callback(r->response_type, rsp);
  3038. }
  3039. /* We need re-enable the irq which was disabled in ISR handler */
  3040. if (!(intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  3041. enable_irq(device->cvp_hal_data->irq);
  3042. return IRQ_HANDLED;
  3043. }
  3044. irqreturn_t cvp_hfi_isr(int irq, void *dev)
  3045. {
  3046. disable_irq_nosync(irq);
  3047. return IRQ_WAKE_THREAD;
  3048. }
  3049. static void iris_hfi_wd_work_handler(struct work_struct *work)
  3050. {
  3051. struct msm_cvp_core *core;
  3052. struct iris_hfi_device *device;
  3053. struct msm_cvp_cb_cmd_done response = {0};
  3054. enum hal_command_response cmd = HAL_SYS_WATCHDOG_TIMEOUT;
  3055. core = cvp_driver->cvp_core;
  3056. if (core)
  3057. device = core->dev_ops->hfi_device_data;
  3058. else
  3059. return;
  3060. if (msm_cvp_hw_wd_recovery) {
  3061. dprintk(CVP_ERR, "Cleaning up as HW WD recovery is enable %d\n",
  3062. msm_cvp_hw_wd_recovery);
  3063. __print_sidebandmanager_regs(device);
  3064. response.device_id = 0;
  3065. handle_sys_error(cmd, (void *) &response);
  3066. enable_irq(device->cvp_hal_data->irq_wd);
  3067. }
  3068. else {
  3069. dprintk(CVP_ERR, "Crashing the device as HW WD recovery is disable %d\n",
  3070. msm_cvp_hw_wd_recovery);
  3071. BUG_ON(1);
  3072. }
  3073. }
  3074. static DECLARE_WORK(iris_hfi_wd_work, iris_hfi_wd_work_handler);
  3075. irqreturn_t iris_hfi_isr_wd(int irq, void *dev)
  3076. {
  3077. struct iris_hfi_device *device = dev;
  3078. dprintk(CVP_ERR, "Got HW WDOG IRQ at %llu! \n", get_aon_time());
  3079. disable_irq_nosync(irq);
  3080. queue_work(device->cvp_workq, &iris_hfi_wd_work);
  3081. return IRQ_HANDLED;
  3082. }
  3083. static int __init_reset_clk(struct msm_cvp_platform_resources *res,
  3084. int reset_index)
  3085. {
  3086. int rc = 0;
  3087. struct reset_control *rst;
  3088. struct reset_info *rst_info;
  3089. struct reset_set *rst_set = &res->reset_set;
  3090. if (!rst_set->reset_tbl)
  3091. return 0;
  3092. rst_info = &rst_set->reset_tbl[reset_index];
  3093. rst = rst_info->rst;
  3094. dprintk(CVP_PWR, "reset_clk: name %s rst %pK required_stage=%d\n",
  3095. rst_set->reset_tbl[reset_index].name, rst, rst_info->required_stage);
  3096. if (rst)
  3097. goto skip_reset_init;
  3098. if (rst_info->required_stage == CVP_ON_USE) {
  3099. rst = reset_control_get_exclusive_released(&res->pdev->dev,
  3100. rst_set->reset_tbl[reset_index].name);
  3101. if (IS_ERR(rst)) {
  3102. rc = PTR_ERR(rst);
  3103. dprintk(CVP_ERR, "reset get exclusive fail %d\n", rc);
  3104. return rc;
  3105. }
  3106. dprintk(CVP_PWR, "reset_clk: name %s get exclusive rst %llx\n",
  3107. rst_set->reset_tbl[reset_index].name, rst);
  3108. } else if (rst_info->required_stage == CVP_ON_INIT) {
  3109. rst = devm_reset_control_get(&res->pdev->dev,
  3110. rst_set->reset_tbl[reset_index].name);
  3111. if (IS_ERR(rst)) {
  3112. rc = PTR_ERR(rst);
  3113. dprintk(CVP_ERR, "reset get fail %d\n", rc);
  3114. return rc;
  3115. }
  3116. dprintk(CVP_PWR, "reset_clk: name %s get rst %llx\n",
  3117. rst_set->reset_tbl[reset_index].name, rst);
  3118. } else {
  3119. dprintk(CVP_ERR, "Invalid reset stage\n");
  3120. return -EINVAL;
  3121. }
  3122. rst_set->reset_tbl[reset_index].rst = rst;
  3123. rst_info->state = RESET_INIT;
  3124. return 0;
  3125. skip_reset_init:
  3126. return rc;
  3127. }
  3128. static int __reset_control_assert_name(struct iris_hfi_device *device,
  3129. const char *name)
  3130. {
  3131. struct reset_info *rcinfo = NULL;
  3132. int rc = 0;
  3133. bool found = false;
  3134. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3135. if (strcmp(rcinfo->name, name))
  3136. continue;
  3137. found = true;
  3138. rc = reset_control_assert(rcinfo->rst);
  3139. if (rc)
  3140. dprintk(CVP_ERR,
  3141. "%s: failed to assert reset control (%s), rc = %d\n",
  3142. __func__, rcinfo->name, rc);
  3143. else
  3144. dprintk(CVP_PWR, "%s: assert reset control (%s)\n",
  3145. __func__, rcinfo->name);
  3146. break;
  3147. }
  3148. if (!found) {
  3149. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3150. __func__, name);
  3151. rc = -EINVAL;
  3152. }
  3153. return rc;
  3154. }
  3155. static int __reset_control_deassert_name(struct iris_hfi_device *device,
  3156. const char *name)
  3157. {
  3158. struct reset_info *rcinfo = NULL;
  3159. int rc = 0;
  3160. bool found = false;
  3161. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3162. if (strcmp(rcinfo->name, name))
  3163. continue;
  3164. found = true;
  3165. rc = reset_control_deassert(rcinfo->rst);
  3166. if (rc)
  3167. dprintk(CVP_ERR,
  3168. "%s: deassert reset control for (%s) failed, rc %d\n",
  3169. __func__, rcinfo->name, rc);
  3170. else
  3171. dprintk(CVP_PWR, "%s: deassert reset control (%s)\n",
  3172. __func__, rcinfo->name);
  3173. break;
  3174. }
  3175. if (!found) {
  3176. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3177. __func__, name);
  3178. rc = -EINVAL;
  3179. }
  3180. return rc;
  3181. }
  3182. static int __reset_control_acquire(struct iris_hfi_device *device,
  3183. const char *name)
  3184. {
  3185. struct reset_info *rcinfo = NULL;
  3186. int rc = 0;
  3187. bool found = false;
  3188. int max_retries = 10;
  3189. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3190. if (strcmp(rcinfo->name, name))
  3191. continue;
  3192. found = true;
  3193. if (rcinfo->state == RESET_ACQUIRED)
  3194. return rc;
  3195. acquire_again:
  3196. rc = reset_control_acquire(rcinfo->rst);
  3197. if (rc) {
  3198. if (rc == -EBUSY) {
  3199. usleep_range(500, 1000);
  3200. max_retries--;
  3201. if (max_retries) {
  3202. goto acquire_again;
  3203. } else {
  3204. dprintk(CVP_ERR,
  3205. "%s acquire %s -EBUSY\n",
  3206. __func__, rcinfo->name);
  3207. rc = -EINVAL;
  3208. }
  3209. } else {
  3210. dprintk(CVP_ERR,
  3211. "%s: acquire failed (%s) rc %d\n",
  3212. __func__, rcinfo->name, rc);
  3213. rc = -EINVAL;
  3214. }
  3215. } else {
  3216. dprintk(CVP_PWR, "%s: reset acquire succeed (%s)\n",
  3217. __func__, rcinfo->name);
  3218. rcinfo->state = RESET_ACQUIRED;
  3219. }
  3220. break;
  3221. }
  3222. if (!found) {
  3223. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3224. __func__, name);
  3225. rc = -EINVAL;
  3226. }
  3227. return rc;
  3228. }
  3229. static int __reset_control_release(struct iris_hfi_device *device,
  3230. const char *name)
  3231. {
  3232. struct reset_info *rcinfo = NULL;
  3233. int rc = 0;
  3234. bool found = false;
  3235. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3236. if (strcmp(rcinfo->name, name))
  3237. continue;
  3238. found = true;
  3239. if (rcinfo->state != RESET_ACQUIRED) {
  3240. dprintk(CVP_WARN, "Double releasing reset clk?\n");
  3241. return -EINVAL;
  3242. }
  3243. reset_control_release(rcinfo->rst);
  3244. dprintk(CVP_PWR, "%s: reset release succeed (%s)\n",
  3245. __func__, rcinfo->name);
  3246. rcinfo->state = RESET_RELEASED;
  3247. break;
  3248. }
  3249. if (!found) {
  3250. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3251. __func__, name);
  3252. rc = -EINVAL;
  3253. }
  3254. return rc;
  3255. }
  3256. static void __deinit_bus(struct iris_hfi_device *device)
  3257. {
  3258. struct bus_info *bus = NULL;
  3259. if (!device)
  3260. return;
  3261. kfree(device->bus_vote.data);
  3262. device->bus_vote = CVP_DEFAULT_BUS_VOTE;
  3263. iris_hfi_for_each_bus_reverse(device, bus) {
  3264. dev_set_drvdata(bus->dev, NULL);
  3265. icc_put(bus->client);
  3266. bus->client = NULL;
  3267. }
  3268. }
  3269. static int __init_bus(struct iris_hfi_device *device)
  3270. {
  3271. struct bus_info *bus = NULL;
  3272. int rc = 0;
  3273. if (!device)
  3274. return -EINVAL;
  3275. iris_hfi_for_each_bus(device, bus) {
  3276. /*
  3277. * This is stupid, but there's no other easy way to ahold
  3278. * of struct bus_info in iris_hfi_devfreq_*()
  3279. */
  3280. WARN(dev_get_drvdata(bus->dev), "%s's drvdata already set\n",
  3281. dev_name(bus->dev));
  3282. dev_set_drvdata(bus->dev, device);
  3283. bus->client = icc_get(&device->res->pdev->dev,
  3284. bus->master, bus->slave);
  3285. if (IS_ERR_OR_NULL(bus->client)) {
  3286. rc = PTR_ERR(bus->client) ?: -EBADHANDLE;
  3287. dprintk(CVP_ERR, "Failed to register bus %s: %d\n",
  3288. bus->name, rc);
  3289. bus->client = NULL;
  3290. goto err_add_dev;
  3291. }
  3292. }
  3293. return 0;
  3294. err_add_dev:
  3295. __deinit_bus(device);
  3296. return rc;
  3297. }
  3298. static void __deinit_regulators(struct iris_hfi_device *device)
  3299. {
  3300. struct regulator_info *rinfo = NULL;
  3301. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3302. if (rinfo->regulator) {
  3303. regulator_put(rinfo->regulator);
  3304. rinfo->regulator = NULL;
  3305. }
  3306. }
  3307. }
  3308. static int __init_regulators(struct iris_hfi_device *device)
  3309. {
  3310. int rc = 0;
  3311. struct regulator_info *rinfo = NULL;
  3312. iris_hfi_for_each_regulator(device, rinfo) {
  3313. rinfo->regulator = regulator_get(&device->res->pdev->dev,
  3314. rinfo->name);
  3315. if (IS_ERR_OR_NULL(rinfo->regulator)) {
  3316. rc = PTR_ERR(rinfo->regulator) ?: -EBADHANDLE;
  3317. dprintk(CVP_ERR, "Failed to get regulator: %s\n",
  3318. rinfo->name);
  3319. rinfo->regulator = NULL;
  3320. goto err_reg_get;
  3321. }
  3322. }
  3323. return 0;
  3324. err_reg_get:
  3325. __deinit_regulators(device);
  3326. return rc;
  3327. }
  3328. static void __deinit_subcaches(struct iris_hfi_device *device)
  3329. {
  3330. struct subcache_info *sinfo = NULL;
  3331. if (!device) {
  3332. dprintk(CVP_ERR, "deinit_subcaches: invalid device %pK\n",
  3333. device);
  3334. goto exit;
  3335. }
  3336. if (!is_sys_cache_present(device))
  3337. goto exit;
  3338. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3339. if (sinfo->subcache) {
  3340. dprintk(CVP_CORE, "deinit_subcaches: %s\n",
  3341. sinfo->name);
  3342. llcc_slice_putd(sinfo->subcache);
  3343. sinfo->subcache = NULL;
  3344. }
  3345. }
  3346. exit:
  3347. return;
  3348. }
  3349. static int __init_subcaches(struct iris_hfi_device *device)
  3350. {
  3351. int rc = 0;
  3352. struct subcache_info *sinfo = NULL;
  3353. if (!device) {
  3354. dprintk(CVP_ERR, "init_subcaches: invalid device %pK\n",
  3355. device);
  3356. return -EINVAL;
  3357. }
  3358. if (!is_sys_cache_present(device))
  3359. return 0;
  3360. iris_hfi_for_each_subcache(device, sinfo) {
  3361. if (!strcmp("cvp", sinfo->name)) {
  3362. sinfo->subcache = llcc_slice_getd(LLCC_CVP);
  3363. } else if (!strcmp("cvpfw", sinfo->name)) {
  3364. sinfo->subcache = llcc_slice_getd(LLCC_CVPFW);
  3365. } else {
  3366. dprintk(CVP_ERR, "Invalid subcache name %s\n",
  3367. sinfo->name);
  3368. }
  3369. if (IS_ERR_OR_NULL(sinfo->subcache)) {
  3370. rc = PTR_ERR(sinfo->subcache) ?
  3371. PTR_ERR(sinfo->subcache) : -EBADHANDLE;
  3372. dprintk(CVP_ERR,
  3373. "init_subcaches: invalid subcache: %s rc %d\n",
  3374. sinfo->name, rc);
  3375. sinfo->subcache = NULL;
  3376. goto err_subcache_get;
  3377. }
  3378. dprintk(CVP_CORE, "init_subcaches: %s\n",
  3379. sinfo->name);
  3380. }
  3381. return 0;
  3382. err_subcache_get:
  3383. __deinit_subcaches(device);
  3384. return rc;
  3385. }
  3386. static int __init_resources(struct iris_hfi_device *device,
  3387. struct msm_cvp_platform_resources *res)
  3388. {
  3389. int i, rc = 0;
  3390. rc = __init_regulators(device);
  3391. if (rc) {
  3392. dprintk(CVP_ERR, "Failed to get all regulators\n");
  3393. return -ENODEV;
  3394. }
  3395. rc = msm_cvp_init_clocks(device);
  3396. if (rc) {
  3397. dprintk(CVP_ERR, "Failed to init clocks\n");
  3398. rc = -ENODEV;
  3399. goto err_init_clocks;
  3400. }
  3401. for (i = 0; i < device->res->reset_set.count; i++) {
  3402. rc = __init_reset_clk(res, i);
  3403. if (rc) {
  3404. dprintk(CVP_ERR, "Failed to init reset clocks\n");
  3405. rc = -ENODEV;
  3406. goto err_init_reset_clk;
  3407. }
  3408. }
  3409. rc = __init_bus(device);
  3410. if (rc) {
  3411. dprintk(CVP_ERR, "Failed to init bus: %d\n", rc);
  3412. goto err_init_bus;
  3413. }
  3414. rc = __init_subcaches(device);
  3415. if (rc)
  3416. dprintk(CVP_WARN, "Failed to init subcaches: %d\n", rc);
  3417. device->sys_init_capabilities =
  3418. kzalloc(sizeof(struct msm_cvp_capability)
  3419. * CVP_MAX_SESSIONS, GFP_KERNEL);
  3420. return rc;
  3421. err_init_reset_clk:
  3422. err_init_bus:
  3423. msm_cvp_deinit_clocks(device);
  3424. err_init_clocks:
  3425. __deinit_regulators(device);
  3426. return rc;
  3427. }
  3428. static void __deinit_resources(struct iris_hfi_device *device)
  3429. {
  3430. __deinit_subcaches(device);
  3431. __deinit_bus(device);
  3432. msm_cvp_deinit_clocks(device);
  3433. __deinit_regulators(device);
  3434. kfree(device->sys_init_capabilities);
  3435. device->sys_init_capabilities = NULL;
  3436. }
  3437. static int __disable_regulator_impl(struct regulator_info *rinfo,
  3438. struct iris_hfi_device *device)
  3439. {
  3440. int rc = 0;
  3441. dprintk(CVP_PWR, "Disabling regulator %s\n", rinfo->name);
  3442. /*
  3443. * This call is needed. Driver needs to acquire the control back
  3444. * from HW in order to disable the regualtor. Else the behavior
  3445. * is unknown.
  3446. */
  3447. rc = __acquire_regulator(rinfo, device);
  3448. if (rc) {
  3449. /*
  3450. * This is somewhat fatal, but nothing we can do
  3451. * about it. We can't disable the regulator w/o
  3452. * getting it back under s/w control
  3453. */
  3454. dprintk(CVP_WARN,
  3455. "Failed to acquire control on %s\n",
  3456. rinfo->name);
  3457. goto disable_regulator_failed;
  3458. }
  3459. rc = regulator_disable(rinfo->regulator);
  3460. if (rc) {
  3461. dprintk(CVP_WARN,
  3462. "Failed to disable %s: %d\n",
  3463. rinfo->name, rc);
  3464. goto disable_regulator_failed;
  3465. }
  3466. return 0;
  3467. disable_regulator_failed:
  3468. /* Bring attention to this issue */
  3469. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3470. return rc;
  3471. }
  3472. static int __disable_hw_power_collapse(struct iris_hfi_device *device)
  3473. {
  3474. int rc = 0;
  3475. if (!msm_cvp_fw_low_power_mode) {
  3476. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3477. return 0;
  3478. }
  3479. rc = __take_back_regulators(device);
  3480. if (rc)
  3481. dprintk(CVP_WARN,
  3482. "%s : Failed to disable HW power collapse %d\n",
  3483. __func__, rc);
  3484. return rc;
  3485. }
  3486. static int __enable_hw_power_collapse(struct iris_hfi_device *device)
  3487. {
  3488. int rc = 0;
  3489. if (!msm_cvp_fw_low_power_mode) {
  3490. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3491. return 0;
  3492. }
  3493. rc = __hand_off_regulators(device);
  3494. if (rc)
  3495. dprintk(CVP_WARN,
  3496. "%s : Failed to enable HW power collapse %d\n",
  3497. __func__, rc);
  3498. return rc;
  3499. }
  3500. static int __enable_regulator(struct iris_hfi_device *device,
  3501. const char *name)
  3502. {
  3503. int rc = 0;
  3504. struct regulator_info *rinfo;
  3505. iris_hfi_for_each_regulator(device, rinfo) {
  3506. if (strcmp(rinfo->name, name))
  3507. continue;
  3508. rc = regulator_enable(rinfo->regulator);
  3509. if (rc) {
  3510. dprintk(CVP_ERR, "Failed to enable %s: %d\n",
  3511. rinfo->name, rc);
  3512. return rc;
  3513. }
  3514. if (!regulator_is_enabled(rinfo->regulator)) {
  3515. dprintk(CVP_ERR,"%s: regulator %s not enabled\n",
  3516. __func__, rinfo->name);
  3517. regulator_disable(rinfo->regulator);
  3518. return -EINVAL;
  3519. }
  3520. dprintk(CVP_PWR, "Enabled regulator %s\n", rinfo->name);
  3521. return 0;
  3522. }
  3523. dprintk(CVP_ERR, "regulator %s not found\n", name);
  3524. return -EINVAL;
  3525. }
  3526. static int __disable_regulator(struct iris_hfi_device *device,
  3527. const char *name)
  3528. {
  3529. struct regulator_info *rinfo;
  3530. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3531. if (strcmp(rinfo->name, name))
  3532. continue;
  3533. __disable_regulator_impl(rinfo, device);
  3534. dprintk(CVP_PWR, "%s Disabled regulator %s\n", __func__, name);
  3535. return 0;
  3536. }
  3537. dprintk(CVP_ERR, "%s regulator %s not found\n", __func__, name);
  3538. return -EINVAL;
  3539. }
  3540. static int __enable_subcaches(struct iris_hfi_device *device)
  3541. {
  3542. int rc = 0;
  3543. u32 c = 0;
  3544. struct subcache_info *sinfo;
  3545. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3546. return 0;
  3547. /* Activate subcaches */
  3548. iris_hfi_for_each_subcache(device, sinfo) {
  3549. rc = llcc_slice_activate(sinfo->subcache);
  3550. if (rc) {
  3551. dprintk(CVP_WARN, "Failed to activate %s: %d\n",
  3552. sinfo->name, rc);
  3553. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3554. goto err_activate_fail;
  3555. }
  3556. sinfo->isactive = true;
  3557. dprintk(CVP_CORE, "Activated subcache %s\n", sinfo->name);
  3558. c++;
  3559. }
  3560. dprintk(CVP_CORE, "Activated %d Subcaches to CVP\n", c);
  3561. return 0;
  3562. err_activate_fail:
  3563. __release_subcaches(device);
  3564. __disable_subcaches(device);
  3565. return 0;
  3566. }
  3567. static int __set_subcaches(struct iris_hfi_device *device)
  3568. {
  3569. int rc = 0;
  3570. u32 c = 0;
  3571. struct subcache_info *sinfo;
  3572. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3573. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3574. struct cvp_hfi_resource_subcache_type *sc_res;
  3575. struct cvp_resource_hdr rhdr;
  3576. if (device->res->sys_cache_res_set || msm_cvp_syscache_disable) {
  3577. dprintk(CVP_CORE, "Subcaches already set or disabled\n");
  3578. return 0;
  3579. }
  3580. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3581. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3582. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3583. iris_hfi_for_each_subcache(device, sinfo) {
  3584. if (sinfo->isactive) {
  3585. sc_res[c].size = sinfo->subcache->slice_size;
  3586. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3587. c++;
  3588. }
  3589. }
  3590. /* Set resource to CVP for activated subcaches */
  3591. if (c) {
  3592. dprintk(CVP_CORE, "Setting %d Subcaches\n", c);
  3593. rhdr.resource_handle = sc_res_info; /* cookie */
  3594. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3595. sc_res_info->num_entries = c;
  3596. rc = __core_set_resource(device, &rhdr, (void *)sc_res_info);
  3597. if (rc) {
  3598. dprintk(CVP_WARN, "Failed to set subcaches %d\n", rc);
  3599. goto err_fail_set_subacaches;
  3600. }
  3601. iris_hfi_for_each_subcache(device, sinfo) {
  3602. if (sinfo->isactive)
  3603. sinfo->isset = true;
  3604. }
  3605. dprintk(CVP_CORE, "Set Subcaches done to CVP\n");
  3606. device->res->sys_cache_res_set = true;
  3607. }
  3608. return 0;
  3609. err_fail_set_subacaches:
  3610. __disable_subcaches(device);
  3611. return 0;
  3612. }
  3613. static int __release_subcaches(struct iris_hfi_device *device)
  3614. {
  3615. struct subcache_info *sinfo;
  3616. int rc = 0;
  3617. u32 c = 0;
  3618. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3619. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3620. struct cvp_hfi_resource_subcache_type *sc_res;
  3621. struct cvp_resource_hdr rhdr;
  3622. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3623. return 0;
  3624. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3625. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3626. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3627. /* Release resource command to Iris */
  3628. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3629. if (sinfo->isset) {
  3630. /* Update the entry */
  3631. sc_res[c].size = sinfo->subcache->slice_size;
  3632. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3633. c++;
  3634. sinfo->isset = false;
  3635. }
  3636. }
  3637. if (c > 0) {
  3638. dprintk(CVP_CORE, "Releasing %d subcaches\n", c);
  3639. rhdr.resource_handle = sc_res_info; /* cookie */
  3640. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3641. rc = __core_release_resource(device, &rhdr);
  3642. if (rc)
  3643. dprintk(CVP_WARN,
  3644. "Failed to release %d subcaches\n", c);
  3645. }
  3646. device->res->sys_cache_res_set = false;
  3647. return 0;
  3648. }
  3649. static int __disable_subcaches(struct iris_hfi_device *device)
  3650. {
  3651. struct subcache_info *sinfo;
  3652. int rc = 0;
  3653. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3654. return 0;
  3655. /* De-activate subcaches */
  3656. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3657. if (sinfo->isactive) {
  3658. dprintk(CVP_CORE, "De-activate subcache %s\n",
  3659. sinfo->name);
  3660. rc = llcc_slice_deactivate(sinfo->subcache);
  3661. if (rc) {
  3662. dprintk(CVP_WARN,
  3663. "Failed to de-activate %s: %d\n",
  3664. sinfo->name, rc);
  3665. }
  3666. sinfo->isactive = false;
  3667. }
  3668. }
  3669. return 0;
  3670. }
  3671. static void interrupt_init_iris2(struct iris_hfi_device *device)
  3672. {
  3673. u32 mask_val = 0;
  3674. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  3675. mask_val = __read_register(device, CVP_WRAPPER_INTR_MASK);
  3676. /* Write 0 to unmask CPU and WD interrupts */
  3677. mask_val &= ~(CVP_FATAL_INTR_BMSK | CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK);
  3678. __write_register(device, CVP_WRAPPER_INTR_MASK, mask_val);
  3679. dprintk(CVP_REG, "Init irq: reg: %x, mask value %x\n",
  3680. CVP_WRAPPER_INTR_MASK, mask_val);
  3681. mask_val = 0;
  3682. mask_val = __read_register(device, CVP_SS_IRQ_MASK);
  3683. mask_val &= ~(CVP_SS_INTR_BMASK);
  3684. __write_register(device, CVP_SS_IRQ_MASK, mask_val);
  3685. dprintk(CVP_REG, "Init irq_wd: reg: %x, mask value %x\n",
  3686. CVP_SS_IRQ_MASK, mask_val);
  3687. }
  3688. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device)
  3689. {
  3690. /* initialize DSP QTBL & UCREGION with CPU queues */
  3691. __write_register(device, HFI_DSP_QTBL_ADDR,
  3692. (u32)device->dsp_iface_q_table.align_device_addr);
  3693. __write_register(device, HFI_DSP_UC_REGION_ADDR,
  3694. (u32)device->dsp_iface_q_table.align_device_addr);
  3695. __write_register(device, HFI_DSP_UC_REGION_SIZE,
  3696. device->dsp_iface_q_table.mem_data.size);
  3697. }
  3698. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device)
  3699. {
  3700. __write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);
  3701. }
  3702. static int __set_ubwc_config(struct iris_hfi_device *device)
  3703. {
  3704. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  3705. int rc = 0;
  3706. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  3707. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  3708. if (!device->res->ubwc_config)
  3709. return 0;
  3710. rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,
  3711. device->res->ubwc_config);
  3712. if (rc) {
  3713. dprintk(CVP_WARN,
  3714. "ubwc config setting to FW failed\n");
  3715. rc = -ENOTEMPTY;
  3716. goto fail_to_set_ubwc_config;
  3717. }
  3718. if (__iface_cmdq_write(device, pkt)) {
  3719. rc = -ENOTEMPTY;
  3720. goto fail_to_set_ubwc_config;
  3721. }
  3722. fail_to_set_ubwc_config:
  3723. return rc;
  3724. }
  3725. static int __power_on_controller(struct iris_hfi_device *device)
  3726. {
  3727. int rc = 0;
  3728. rc = __enable_regulator(device, "cvp");
  3729. if (rc) {
  3730. dprintk(CVP_ERR, "Failed to enable ctrler: %d\n", rc);
  3731. return rc;
  3732. }
  3733. rc = msm_cvp_prepare_enable_clk(device, "sleep_clk");
  3734. if (rc) {
  3735. dprintk(CVP_ERR, "Failed to enable sleep clk: %d\n", rc);
  3736. goto fail_reset_clks;
  3737. }
  3738. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  3739. if (rc)
  3740. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  3741. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  3742. if (rc)
  3743. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  3744. /* wait for deassert */
  3745. usleep_range(300, 400);
  3746. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  3747. if (rc)
  3748. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  3749. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  3750. if (rc)
  3751. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  3752. rc = msm_cvp_prepare_enable_clk(device, "gcc_video_axi1");
  3753. if (rc) {
  3754. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  3755. goto fail_reset_clks;
  3756. }
  3757. rc = msm_cvp_prepare_enable_clk(device, "cvp_clk");
  3758. if (rc) {
  3759. dprintk(CVP_ERR, "Failed to enable cvp_clk: %d\n", rc);
  3760. goto fail_enable_clk;
  3761. }
  3762. dprintk(CVP_PWR, "EVA controller powered on\n");
  3763. return 0;
  3764. fail_enable_clk:
  3765. msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  3766. fail_reset_clks:
  3767. __disable_regulator(device, "cvp");
  3768. return rc;
  3769. }
  3770. static int __power_on_core(struct iris_hfi_device *device)
  3771. {
  3772. int rc = 0;
  3773. rc = __enable_regulator(device, "cvp-core");
  3774. if (rc) {
  3775. dprintk(CVP_ERR, "Failed to enable core: %d\n", rc);
  3776. return rc;
  3777. }
  3778. rc = msm_cvp_prepare_enable_clk(device, "video_cc_mvs1_clk_src");
  3779. if (rc) {
  3780. dprintk(CVP_ERR, "Failed to enable video_cc_mvs1_clk_src:%d\n",
  3781. rc);
  3782. __disable_regulator(device, "cvp-core");
  3783. return rc;
  3784. }
  3785. rc = msm_cvp_prepare_enable_clk(device, "core_clk");
  3786. if (rc) {
  3787. dprintk(CVP_ERR, "Failed to enable core_clk: %d\n", rc);
  3788. __disable_regulator(device, "cvp-core");
  3789. return rc;
  3790. }
  3791. /*#ifdef CONFIG_EVA_PINEAPPLE
  3792. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_ARCG_CONTROL, 0);
  3793. __write_register(device, CVP_NOC_RCGCONTROLLER_HYSTERESIS_LOW, 0x2f);
  3794. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 1);
  3795. __write_register(device, CVP_NOC_RCGCONTROLLER_MAINCTL_LOW, 1);
  3796. usleep_range(50, 100);
  3797. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 0);
  3798. #endif*/
  3799. dprintk(CVP_PWR, "EVA core powered on\n");
  3800. return 0;
  3801. }
  3802. static int __iris_power_on(struct iris_hfi_device *device)
  3803. {
  3804. int rc = 0;
  3805. u32 reg_gdsc, reg_cbcr, spare_val;
  3806. if (device->power_enabled)
  3807. return 0;
  3808. /* Vote for all hardware resources */
  3809. rc = __vote_buses(device, device->bus_vote.data,
  3810. device->bus_vote.data_count);
  3811. if (rc) {
  3812. dprintk(CVP_ERR, "Failed to vote buses, err: %d\n", rc);
  3813. goto fail_vote_buses;
  3814. }
  3815. rc = __power_on_controller(device);
  3816. if (rc)
  3817. goto fail_enable_controller;
  3818. rc = __power_on_core(device);
  3819. if (rc)
  3820. goto fail_enable_core;
  3821. rc = msm_cvp_scale_clocks(device);
  3822. if (rc) {
  3823. dprintk(CVP_WARN,
  3824. "Failed to scale clocks, perf may regress\n");
  3825. rc = 0;
  3826. } else {
  3827. dprintk(CVP_PWR, "Done with scaling\n");
  3828. }
  3829. /*Do not access registers before this point!*/
  3830. device->power_enabled = true;
  3831. /* Thomas input to debug CPU NoC hang */
  3832. __write_register(device, CVP_NOC_SBM_FAULTINEN0_LOW, 0x1);
  3833. __write_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS, 0x3);
  3834. /*
  3835. * Re-program all of the registers that get reset as a result of
  3836. * regulator_disable() and _enable()
  3837. * calling below function requires CORE powered on
  3838. */
  3839. rc = __set_registers(device);
  3840. if (rc)
  3841. goto fail_enable_core;
  3842. dprintk(CVP_CORE, "Done with register set\n");
  3843. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  3844. reg_cbcr = __read_register(device, CVP_CC_MVS1_CBCR);
  3845. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3846. rc = -EINVAL;
  3847. dprintk(CVP_ERR, "CORE power on failed gdsc %x cbcr %x\n",
  3848. reg_gdsc, reg_cbcr);
  3849. goto fail_enable_core;
  3850. }
  3851. reg_gdsc = __read_register(device, CVP_CC_MVS1C_GDSCR);
  3852. reg_cbcr = __read_register(device, CVP_CC_MVS1C_CBCR);
  3853. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3854. rc = -EINVAL;
  3855. dprintk(CVP_ERR, "CTRL power on failed gdsc %x cbcr %x\n",
  3856. reg_gdsc, reg_cbcr);
  3857. goto fail_enable_core;
  3858. }
  3859. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3860. if ((spare_val & 0x2) != 0) {
  3861. usleep_range(2000, 3000);
  3862. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3863. if ((spare_val & 0x2) != 0) {
  3864. dprintk(CVP_ERR, "WRAPPER_SPARE non-zero %#x\n", spare_val);
  3865. rc = -EINVAL;
  3866. goto fail_enable_core;
  3867. }
  3868. }
  3869. call_iris_op(device, interrupt_init, device);
  3870. dprintk(CVP_CORE, "Done with interrupt enabling\n");
  3871. device->intr_status = 0;
  3872. enable_irq(device->cvp_hal_data->irq);
  3873. __write_register(device,
  3874. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
  3875. pr_info_ratelimited(CVP_DBG_TAG "cvp (eva) powered on\n", "pwr");
  3876. return 0;
  3877. fail_enable_core:
  3878. __power_off_controller(device);
  3879. fail_enable_controller:
  3880. __unvote_buses(device);
  3881. fail_vote_buses:
  3882. device->power_enabled = false;
  3883. return rc;
  3884. }
  3885. static inline int __suspend(struct iris_hfi_device *device)
  3886. {
  3887. int rc = 0;
  3888. if (!device) {
  3889. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3890. return -EINVAL;
  3891. } else if (!device->power_enabled) {
  3892. dprintk(CVP_PWR, "Power already disabled\n");
  3893. return 0;
  3894. }
  3895. dprintk(CVP_PWR, "Entering suspend\n");
  3896. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3897. if (rc) {
  3898. dprintk(CVP_WARN, "Failed to suspend cvp core %d\n", rc);
  3899. goto err_tzbsp_suspend;
  3900. }
  3901. __disable_subcaches(device);
  3902. call_iris_op(device, power_off, device);
  3903. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  3904. cvp_pm_qos_update(device, false);
  3905. return rc;
  3906. err_tzbsp_suspend:
  3907. return rc;
  3908. }
  3909. static void __print_sidebandmanager_regs(struct iris_hfi_device *device)
  3910. {
  3911. u32 sbm_ln0_low, axi_cbcr, val;
  3912. u32 main_sbm_ln0_low = 0xdeadbeef, main_sbm_ln0_high = 0xdeadbeef;
  3913. u32 main_sbm_ln1_high = 0xdeadbeef, cpu_cs_x2rpmh;
  3914. int rc;
  3915. sbm_ln0_low =
  3916. __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3917. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3918. __write_register(device, CVP_CPU_CS_X2RPMh,
  3919. (cpu_cs_x2rpmh | CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK));
  3920. usleep_range(500, 1000);
  3921. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3922. if (!(cpu_cs_x2rpmh & CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK)) {
  3923. dprintk(CVP_WARN,
  3924. "failed set CVP_CPU_CS_X2RPMH mask %x\n",
  3925. cpu_cs_x2rpmh);
  3926. goto exit;
  3927. }
  3928. axi_cbcr = __read_gcc_register(device, CVP_GCC_VIDEO_AXI1_CBCR);
  3929. if (axi_cbcr & 0x80000000) {
  3930. dprintk(CVP_WARN, "failed to turn on AXI clock %x\n",
  3931. axi_cbcr);
  3932. goto exit;
  3933. }
  3934. /* Added by Thomas to debug CPU NoC hang */
  3935. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  3936. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRVLD_LOW %#x\n", val);
  3937. val = __read_register(device, CVP_NOC_SBM_FAULTINSTATUS0_LOW);
  3938. dprintk(CVP_ERR, "CVP_NOC_SBM_FAULTINSTATUS0_LOW %#x\n", val);
  3939. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  3940. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_LOW %#x\n", val);
  3941. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  3942. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH %#x\n", val);
  3943. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  3944. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_LOW %#x\n", val);
  3945. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  3946. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH %#x\n", val);
  3947. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  3948. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_LOW %#x\n", val);
  3949. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  3950. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH %#x\n", val);
  3951. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  3952. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_LOW %#x\n", val);
  3953. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  3954. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH %#x\n", val);
  3955. /* end of addition */
  3956. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3957. if (rc) {
  3958. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  3959. goto exit;
  3960. }
  3961. main_sbm_ln0_low = __read_register(device,
  3962. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW +
  3963. device->res->noc_main_sidebandmanager_offset);
  3964. main_sbm_ln0_high = __read_register(device,
  3965. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_HIGH +
  3966. device->res->noc_main_sidebandmanager_offset);
  3967. main_sbm_ln1_high = __read_register(device,
  3968. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH +
  3969. device->res->noc_main_sidebandmanager_offset);
  3970. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3971. exit:
  3972. cpu_cs_x2rpmh = cpu_cs_x2rpmh & (~CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK);
  3973. __write_register(device, CVP_CPU_CS_X2RPMh, cpu_cs_x2rpmh);
  3974. dprintk(CVP_WARN, "Sidebandmanager regs %x %x %x %x %x\n",
  3975. sbm_ln0_low, main_sbm_ln0_low,
  3976. main_sbm_ln0_high, main_sbm_ln1_high,
  3977. cpu_cs_x2rpmh);
  3978. }
  3979. static void __enter_cpu_noc_lpi(struct iris_hfi_device *device)
  3980. {
  3981. u32 lpi_status, count = 0, max_count = 2000;
  3982. /* New addition to put CPU/Tensilica to low power */
  3983. count = 0;
  3984. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  3985. while (count < max_count) {
  3986. lpi_status = __read_register(device, CVP_WRAPPER_CPU_NOC_LPI_STATUS);
  3987. if ((lpi_status & BIT(1)) || ((lpi_status & BIT(2)) && (!(lpi_status & BIT(0))))) {
  3988. /*
  3989. * If QDENY == true, or
  3990. * If QACTIVE == true && QACCEPT == false
  3991. * Try again
  3992. */
  3993. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x0);
  3994. usleep_range(10, 20);
  3995. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  3996. usleep_range(1000, 1200);
  3997. count++;
  3998. } else {
  3999. break;
  4000. }
  4001. }
  4002. dprintk(CVP_PWR,
  4003. "%s, CPU Noc: lpi_status %x (count %d)\n", __func__, lpi_status, count);
  4004. if (count == max_count) {
  4005. u32 pc_ready, wfi_status;
  4006. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4007. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4008. dprintk(CVP_WARN,
  4009. "%s, CPU NOC not in qaccept status %x %x %x\n",
  4010. __func__, lpi_status, wfi_status, pc_ready);
  4011. __print_sidebandmanager_regs(device);
  4012. }
  4013. }
  4014. static int __power_off_controller(struct iris_hfi_device *device)
  4015. {
  4016. u32 lpi_status, count = 0, max_count = 1000;
  4017. int rc;
  4018. u32 spare_val, spare_status;
  4019. /* HPG 6.2.2 Step 1 */
  4020. __write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
  4021. /* HPG 6.2.2 Step 2, noc to low power */
  4022. __enter_cpu_noc_lpi(device);
  4023. /* HPG 6.2.2 Step 3, debug bridge to low power BYPASSED */
  4024. /* HPG 6.2.2 Step 4, debug bridge to lpi release */
  4025. __write_register(device,
  4026. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x0);
  4027. lpi_status = 0x1;
  4028. count = 0;
  4029. while (lpi_status && count < max_count) {
  4030. lpi_status = __read_register(device,
  4031. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  4032. usleep_range(50, 100);
  4033. count++;
  4034. }
  4035. dprintk(CVP_PWR,
  4036. "DBLP Release: lpi_status %d(count %d)\n",
  4037. lpi_status, count);
  4038. if (count == max_count) {
  4039. dprintk(CVP_WARN,
  4040. "DBLP Release: lpi_status %x\n", lpi_status);
  4041. }
  4042. /* PDXFIFO reset: addition for Kailua / Lanai */
  4043. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x3);
  4044. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x1);
  4045. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x0);
  4046. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x0);
  4047. /* HPG 6.2.2 Step 5 */
  4048. msm_cvp_disable_unprepare_clk(device, "cvp_clk");
  4049. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  4050. if (rc)
  4051. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  4052. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  4053. if (rc)
  4054. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  4055. /* wait for deassert */
  4056. usleep_range(1000, 1050);
  4057. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  4058. if (rc)
  4059. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  4060. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  4061. if (rc)
  4062. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  4063. /* disable EVA NoC clock */
  4064. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x1);
  4065. /* enable EVA NoC reset */
  4066. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x1);
  4067. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4068. if (rc) {
  4069. dprintk(CVP_ERR, "FATAL ERROR, HPG step 17 to 20 will be bypassed\n");
  4070. goto skip_xo_reset;
  4071. }
  4072. spare_status = 0x1;
  4073. while (spare_status != 0x0) {
  4074. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  4075. spare_status = spare_val & 0x2;
  4076. usleep_range(50, 100);
  4077. }
  4078. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x1);
  4079. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_xo_reset");
  4080. if (rc)
  4081. dprintk(CVP_ERR, "%s: assert cvp_xo_reset failed\n", __func__);
  4082. /* de-assert EVA_NoC reset */
  4083. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x0);
  4084. /* de-assert EVA video_cc XO reset and enable video_cc XO clock after 80us */
  4085. usleep_range(80, 100);
  4086. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_xo_reset");
  4087. if (rc)
  4088. dprintk(CVP_ERR, "%s: de-assert cvp_xo_reset failed\n", __func__);
  4089. /* clear XO mask bit - this step was missing in previous sequence */
  4090. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x0);
  4091. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4092. skip_xo_reset:
  4093. /* enable EVA NoC clock */
  4094. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x0);
  4095. /* De-assert EVA_CTL Force Sleep Retention */
  4096. usleep_range(400, 500);
  4097. /* HPG 6.2.2 Step 6 */
  4098. __disable_regulator(device, "cvp");
  4099. /* HPG 6.2.2 Step 7 */
  4100. rc = msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  4101. if (rc) {
  4102. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  4103. }
  4104. rc = msm_cvp_disable_unprepare_clk(device, "sleep_clk");
  4105. if (rc) {
  4106. dprintk(CVP_ERR, "Failed to disable sleep clk: %d\n", rc);
  4107. }
  4108. return 0;
  4109. }
  4110. static int __power_off_core(struct iris_hfi_device *device)
  4111. {
  4112. u32 reg_status = 0, lpi_status, config, value = 0, count = 0;
  4113. u32 warn_flag = 0, max_count = 10;
  4114. value = __read_register(device, CVP_CC_MVS1_GDSCR);
  4115. if (!(value & 0x80000000)) {
  4116. /*
  4117. * Core has been powered off by f/w.
  4118. * Check NOC reset registers to ensure
  4119. * NO outstanding NoC transactions
  4120. */
  4121. value = __read_register(device, CVP_NOC_RESET_ACK);
  4122. if (value) {
  4123. dprintk(CVP_WARN,
  4124. "Core off with NOC RESET ACK non-zero %x\n",
  4125. value);
  4126. __print_sidebandmanager_regs(device);
  4127. }
  4128. __disable_regulator(device, "cvp-core");
  4129. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4130. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4131. return 0;
  4132. } else if (!(value & 0x2)) {
  4133. /*
  4134. * HW_CONTROL PC disabled, then core is powered on for
  4135. * CVP NoC access
  4136. */
  4137. __disable_regulator(device, "cvp-core");
  4138. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4139. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4140. return 0;
  4141. }
  4142. dprintk(CVP_PWR, "Driver controls Core power off now\n");
  4143. /*
  4144. * check to make sure core clock branch enabled else
  4145. * we cannot read core idle register
  4146. */
  4147. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4148. if (config) {
  4149. dprintk(CVP_PWR,
  4150. "core clock config not enabled, enable it to access core\n");
  4151. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4152. }
  4153. /*
  4154. * add MNoC idle check before collapsing MVS1 per HPG update
  4155. * poll for NoC DMA idle -> HPG 6.2.1
  4156. *
  4157. */
  4158. do {
  4159. value = __read_register(device, CVP_SS_IDLE_STATUS);
  4160. if (value & 0x400000)
  4161. break;
  4162. else
  4163. usleep_range(1000, 2000);
  4164. count++;
  4165. } while (count < max_count);
  4166. if (count == max_count) {
  4167. dprintk(CVP_WARN, "Core fail to go idle %x\n", value);
  4168. warn_flag = 1;
  4169. }
  4170. count = 0;
  4171. max_count = 1000;
  4172. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x1);
  4173. while (!reg_status && count < max_count) {
  4174. lpi_status =
  4175. __read_register(device,
  4176. CVP_AON_WRAPPER_CVP_NOC_LPI_STATUS);
  4177. reg_status = lpi_status & BIT(0);
  4178. /* Wait for Core noc lpi status to be set */
  4179. usleep_range(50, 100);
  4180. count++;
  4181. }
  4182. dprintk(CVP_PWR,
  4183. "Core Noc: lpi_status %x noc_status %x (count %d)\n",
  4184. lpi_status, reg_status, count);
  4185. if (count == max_count) {
  4186. u32 pc_ready, wfi_status;
  4187. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4188. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4189. dprintk(CVP_WARN,
  4190. "Core NOC not in qaccept status %x %x %x %x\n",
  4191. reg_status, lpi_status, wfi_status, pc_ready);
  4192. __print_sidebandmanager_regs(device);
  4193. }
  4194. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x0);
  4195. if (warn_flag)
  4196. __print_sidebandmanager_regs(device);
  4197. /* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ) */
  4198. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x3);
  4199. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x2);
  4200. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x0);
  4201. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4202. __disable_hw_power_collapse(device);
  4203. usleep_range(100, 200);
  4204. __disable_regulator(device, "cvp-core");
  4205. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4206. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4207. return 0;
  4208. }
  4209. static void power_off_iris2(struct iris_hfi_device *device)
  4210. {
  4211. if (!device->power_enabled || !device->res->sw_power_collapsible)
  4212. return;
  4213. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  4214. disable_irq_nosync(device->cvp_hal_data->irq);
  4215. device->intr_status = 0;
  4216. __power_off_core(device);
  4217. __power_off_controller(device);
  4218. if (__unvote_buses(device))
  4219. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  4220. /*Do not access registers after this point!*/
  4221. device->power_enabled = false;
  4222. pr_info(CVP_DBG_TAG "cvp (eva) power collapsed\n", "pwr");
  4223. }
  4224. static inline int __resume(struct iris_hfi_device *device)
  4225. {
  4226. int rc = 0;
  4227. struct msm_cvp_core *core;
  4228. if (!device) {
  4229. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  4230. return -EINVAL;
  4231. } else if (device->power_enabled) {
  4232. goto exit;
  4233. } else if (!__core_in_valid_state(device)) {
  4234. dprintk(CVP_PWR, "iris_hfi_device in deinit state.");
  4235. return -EINVAL;
  4236. }
  4237. core = cvp_driver->cvp_core;
  4238. dprintk(CVP_PWR, "Resuming from power collapse\n");
  4239. rc = __iris_power_on(device);
  4240. if (rc) {
  4241. dprintk(CVP_ERR, "Failed to power on cvp\n");
  4242. goto err_iris_power_on;
  4243. }
  4244. __setup_ucregion_memory_map(device);
  4245. /* RUMI: set CVP_CTRL_INIT register to disable synx in FW */
  4246. /* Reboot the firmware */
  4247. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESUME);
  4248. if (rc) {
  4249. dprintk(CVP_ERR, "Failed to resume cvp core %d\n", rc);
  4250. goto err_set_cvp_state;
  4251. }
  4252. /* Wait for boot completion */
  4253. rc = __boot_firmware(device);
  4254. if (rc) {
  4255. dprintk(CVP_ERR, "Failed to reset cvp core\n");
  4256. goto err_reset_core;
  4257. }
  4258. /*
  4259. * Work around for H/W bug, need to reprogram these registers once
  4260. * firmware is out reset
  4261. */
  4262. __set_threshold_registers(device);
  4263. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  4264. cvp_pm_qos_update(device, true);
  4265. __sys_set_debug(device, msm_cvp_fw_debug);
  4266. __enable_subcaches(device);
  4267. __set_subcaches(device);
  4268. __dsp_resume(device);
  4269. dprintk(CVP_PWR, "Resumed from power collapse\n");
  4270. exit:
  4271. /* Don't reset skip_pc_count for SYS_PC_PREP cmd */
  4272. if (device->last_packet_type != HFI_CMD_SYS_PC_PREP)
  4273. device->skip_pc_count = 0;
  4274. return rc;
  4275. err_reset_core:
  4276. __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  4277. err_set_cvp_state:
  4278. call_iris_op(device, power_off, device);
  4279. err_iris_power_on:
  4280. dprintk(CVP_ERR, "Failed to resume from power collapse\n");
  4281. return rc;
  4282. }
  4283. static int __power_on_init(struct iris_hfi_device *device)
  4284. {
  4285. int rc = 0;
  4286. /* Initialize resources */
  4287. rc = __init_resources(device, device->res);
  4288. if (rc) {
  4289. dprintk(CVP_ERR, "Failed to init resources: %d\n", rc);
  4290. return rc;
  4291. }
  4292. rc = __initialize_packetization(device);
  4293. if (rc) {
  4294. dprintk(CVP_ERR, "Failed to initialize packetization\n");
  4295. goto fail_iris_init;
  4296. }
  4297. rc = __iris_power_on(device);
  4298. if (rc) {
  4299. dprintk(CVP_ERR, "Failed to power on iris in in load_fw\n");
  4300. goto fail_iris_init;
  4301. }
  4302. return rc;
  4303. fail_iris_init:
  4304. __deinit_resources(device);
  4305. return rc;
  4306. }
  4307. static int __load_fw(struct iris_hfi_device *device)
  4308. {
  4309. int rc = 0;
  4310. if ((!device->res->use_non_secure_pil && !device->res->firmware_base)
  4311. || device->res->use_non_secure_pil) {
  4312. rc = load_cvp_fw_impl(device);
  4313. if (rc)
  4314. goto fail_load_fw;
  4315. }
  4316. return rc;
  4317. fail_load_fw:
  4318. call_iris_op(device, power_off, device);
  4319. return rc;
  4320. }
  4321. static void __unload_fw(struct iris_hfi_device *device)
  4322. {
  4323. if (!device->resources.fw.cookie)
  4324. return;
  4325. cancel_delayed_work(&iris_hfi_pm_work);
  4326. if (device->state != IRIS_STATE_DEINIT)
  4327. flush_workqueue(device->iris_pm_workq);
  4328. /* New addition to put CPU/Tensilica to low power */
  4329. __enter_cpu_noc_lpi(device);
  4330. unload_cvp_fw_impl(device);
  4331. __interface_queues_release(device);
  4332. call_iris_op(device, power_off, device);
  4333. __deinit_resources(device);
  4334. dprintk(CVP_WARN, "Firmware unloaded\n");
  4335. }
  4336. static int iris_hfi_get_fw_info(void *dev, struct cvp_hal_fw_info *fw_info)
  4337. {
  4338. int i = 0;
  4339. struct iris_hfi_device *device = dev;
  4340. if (!device || !fw_info) {
  4341. dprintk(CVP_ERR,
  4342. "%s Invalid parameter: device = %pK fw_info = %pK\n",
  4343. __func__, device, fw_info);
  4344. return -EINVAL;
  4345. }
  4346. mutex_lock(&device->lock);
  4347. while (cvp_driver->fw_version[i++] != 'V' && i < CVP_VERSION_LENGTH)
  4348. ;
  4349. if (i == CVP_VERSION_LENGTH - 1) {
  4350. dprintk(CVP_WARN, "Iris version string is not proper\n");
  4351. fw_info->version[0] = '\0';
  4352. goto fail_version_string;
  4353. }
  4354. memcpy(&fw_info->version[0], &cvp_driver->fw_version[0],
  4355. CVP_VERSION_LENGTH);
  4356. fw_info->version[CVP_VERSION_LENGTH - 1] = '\0';
  4357. fail_version_string:
  4358. dprintk(CVP_CORE, "F/W version retrieved : %s\n", fw_info->version);
  4359. fw_info->base_addr = device->cvp_hal_data->firmware_base;
  4360. fw_info->register_base = device->res->register_base;
  4361. fw_info->register_size = device->cvp_hal_data->register_size;
  4362. fw_info->irq = device->cvp_hal_data->irq;
  4363. mutex_unlock(&device->lock);
  4364. return 0;
  4365. }
  4366. static int iris_hfi_get_core_capabilities(void *dev)
  4367. {
  4368. dprintk(CVP_CORE, "%s not supported yet!\n", __func__);
  4369. return 0;
  4370. }
  4371. static const char * const mid_names[16] = {
  4372. "CVP_FW",
  4373. "ARP_DATA",
  4374. "CVP_MPU_PIXEL",
  4375. "CVP_MPU_NON_PIXEL",
  4376. "CVP_FDU_PIXEL",
  4377. "CVP_FDU_NON_PIXEL",
  4378. "CVP_GCE_PIXEL",
  4379. "CVP_GCE_NON_PIXEL",
  4380. "CVP_TOF_PIXEL",
  4381. "CVP_TOF_NON_PIXEL",
  4382. "CVP_VADL_PIXEL",
  4383. "CVP_VADL_NON_PIXEL",
  4384. "CVP_RGE_NON_PIXEL",
  4385. "CVP_CDM",
  4386. "Invalid",
  4387. "Invalid"
  4388. };
  4389. static void __print_reg_details(u32 val)
  4390. {
  4391. u32 mid, sid;
  4392. mid = (val >> 5) & 0xF;
  4393. sid = (val >> 2) & 0x7;
  4394. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  4395. dprintk(CVP_ERR, "Sub-client:%s, SID: %d\n", mid_names[mid], sid);
  4396. }
  4397. static void __err_log(bool logging, u32 *data, const char *name, u32 val)
  4398. {
  4399. if (logging)
  4400. *data = val;
  4401. dprintk(CVP_ERR, "%s: %#x\n", name, val);
  4402. }
  4403. static void __noc_error_info_iris2(struct iris_hfi_device *device)
  4404. {
  4405. struct msm_cvp_core *core;
  4406. struct cvp_noc_log *noc_log;
  4407. u32 val = 0, regi, regii, regiii;
  4408. bool log_required = false;
  4409. int rc;
  4410. core = cvp_driver->cvp_core;
  4411. if (!core->ssr_count && core->resources.max_ssr_allowed > 1)
  4412. log_required = true;
  4413. noc_log = &core->log.noc_log;
  4414. if (noc_log->used) {
  4415. dprintk(CVP_WARN, "Data already in NoC log, skip logging\n");
  4416. return;
  4417. }
  4418. noc_log->used = 1;
  4419. __disable_hw_power_collapse(device);
  4420. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4421. regi = __read_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL);
  4422. regii = __read_register(device, CVP_CC_MVS1_CBCR);
  4423. regiii = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4424. dprintk(CVP_ERR, "noc reg check: %#x %#x %#x %#x\n",
  4425. val, regi, regii, regiii);
  4426. val = __read_register(device, CVP_NOC_ERR_SWID_LOW_OFFS);
  4427. __err_log(log_required, &noc_log->err_ctrl_swid_low,
  4428. "CVP_NOC_ERL_MAIN_SWID_LOW", val);
  4429. val = __read_register(device, CVP_NOC_ERR_SWID_HIGH_OFFS);
  4430. __err_log(log_required, &noc_log->err_ctrl_swid_high,
  4431. "CVP_NOC_ERL_MAIN_SWID_HIGH", val);
  4432. val = __read_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS);
  4433. __err_log(log_required, &noc_log->err_ctrl_mainctl_low,
  4434. "CVP_NOC_ERL_MAIN_MAINCTL_LOW", val);
  4435. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  4436. __err_log(log_required, &noc_log->err_ctrl_errvld_low,
  4437. "CVP_NOC_ERL_MAIN_ERRVLD_LOW", val);
  4438. val = __read_register(device, CVP_NOC_ERR_ERRCLR_LOW_OFFS);
  4439. __err_log(log_required, &noc_log->err_ctrl_errclr_low,
  4440. "CVP_NOC_ERL_MAIN_ERRCLR_LOW", val);
  4441. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  4442. __err_log(log_required, &noc_log->err_ctrl_errlog0_low,
  4443. "CVP_NOC_ERL_MAIN_ERRLOG0_LOW", val);
  4444. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  4445. __err_log(log_required, &noc_log->err_ctrl_errlog0_high,
  4446. "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH", val);
  4447. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  4448. __err_log(log_required, &noc_log->err_ctrl_errlog1_low,
  4449. "CVP_NOC_ERL_MAIN_ERRLOG1_LOW", val);
  4450. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  4451. __err_log(log_required, &noc_log->err_ctrl_errlog1_high,
  4452. "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH", val);
  4453. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  4454. __err_log(log_required, &noc_log->err_ctrl_errlog2_low,
  4455. "CVP_NOC_ERL_MAIN_ERRLOG2_LOW", val);
  4456. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  4457. __err_log(log_required, &noc_log->err_ctrl_errlog2_high,
  4458. "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH", val);
  4459. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  4460. __err_log(log_required, &noc_log->err_ctrl_errlog3_low,
  4461. "CVP_NOC_ERL_MAIN_ERRLOG3_LOW", val);
  4462. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  4463. __err_log(log_required, &noc_log->err_ctrl_errlog3_high,
  4464. "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH", val);
  4465. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4466. if (rc) {
  4467. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4468. return;
  4469. }
  4470. val = __read_register(device,
  4471. CVP_NOC_CORE_ERR_SWID_LOW_OFFS + device->res->noc_core_err_offset);
  4472. __err_log(log_required, &noc_log->err_core_swid_low,
  4473. "CVP_NOC__CORE_ERL_MAIN_SWID_LOW", val);
  4474. val = __read_register(device,
  4475. CVP_NOC_CORE_ERR_SWID_HIGH_OFFS + device->res->noc_core_err_offset);
  4476. __err_log(log_required, &noc_log->err_core_swid_high,
  4477. "CVP_NOC_CORE_ERL_MAIN_SWID_HIGH", val);
  4478. val = __read_register(device,
  4479. CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS + device->res->noc_core_err_offset);
  4480. __err_log(log_required, &noc_log->err_core_mainctl_low,
  4481. "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW", val);
  4482. val = __read_register(device,
  4483. CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS + device->res->noc_core_err_offset);
  4484. __err_log(log_required, &noc_log->err_core_errvld_low,
  4485. "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW", val);
  4486. val = __read_register(device,
  4487. CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS + device->res->noc_core_err_offset);
  4488. __err_log(log_required, &noc_log->err_core_errclr_low,
  4489. "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW", val);
  4490. val = __read_register(device,
  4491. CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS + device->res->noc_core_err_offset);
  4492. __err_log(log_required, &noc_log->err_core_errlog0_low,
  4493. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW", val);
  4494. val = __read_register(device,
  4495. CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS + device->res->noc_core_err_offset);
  4496. __err_log(log_required, &noc_log->err_core_errlog0_high,
  4497. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH", val);
  4498. val = __read_register(device,
  4499. CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS + device->res->noc_core_err_offset);
  4500. __err_log(log_required, &noc_log->err_core_errlog1_low,
  4501. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW", val);
  4502. val = __read_register(device,
  4503. CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS + device->res->noc_core_err_offset);
  4504. __err_log(log_required, &noc_log->err_core_errlog1_high,
  4505. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH", val);
  4506. val = __read_register(device,
  4507. CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS + device->res->noc_core_err_offset);
  4508. __err_log(log_required, &noc_log->err_core_errlog2_low,
  4509. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW", val);
  4510. val = __read_register(device,
  4511. CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS + device->res->noc_core_err_offset);
  4512. __err_log(log_required, &noc_log->err_core_errlog2_high,
  4513. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH", val);
  4514. val = __read_register(device,
  4515. CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS + device->res->noc_core_err_offset);
  4516. __err_log(log_required, &noc_log->err_core_errlog3_low,
  4517. "CORE ERRLOG3_LOW, below details", val);
  4518. __print_reg_details(val);
  4519. val = __read_register(device,
  4520. CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS + device->res->noc_core_err_offset);
  4521. __err_log(log_required, &noc_log->err_core_errlog3_high,
  4522. "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH", val);
  4523. __write_register(device,
  4524. CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS + device->res->noc_core_err_offset, 0x1);
  4525. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4526. #define CVP_SS_CLK_HALT 0x8
  4527. #define CVP_SS_CLK_EN 0xC
  4528. #define CVP_SS_ARP_TEST_BUS_CONTROL 0x700
  4529. #define CVP_SS_ARP_TEST_BUS_REGISTER 0x704
  4530. #define CVP_DMA_TEST_BUS_CONTROL 0x66A0
  4531. #define CVP_DMA_TEST_BUS_REGISTER 0x66A4
  4532. #define CVP_VPU_WRAPPER_CORE_CONFIG 0xB0088
  4533. __write_register(device, CVP_SS_CLK_HALT, 0);
  4534. __write_register(device, CVP_SS_CLK_EN, 0x3f);
  4535. __write_register(device, CVP_VPU_WRAPPER_CORE_CONFIG, 0);
  4536. }
  4537. static int iris_hfi_noc_error_info(void *dev)
  4538. {
  4539. struct iris_hfi_device *device;
  4540. if (!dev) {
  4541. dprintk(CVP_ERR, "%s: null device\n", __func__);
  4542. return -EINVAL;
  4543. }
  4544. device = dev;
  4545. mutex_lock(&device->lock);
  4546. dprintk(CVP_ERR, "%s: non error information\n", __func__);
  4547. call_iris_op(device, noc_error_info, device);
  4548. mutex_unlock(&device->lock);
  4549. return 0;
  4550. }
  4551. static int __initialize_packetization(struct iris_hfi_device *device)
  4552. {
  4553. int rc = 0;
  4554. if (!device || !device->res) {
  4555. dprintk(CVP_ERR, "%s - invalid param\n", __func__);
  4556. return -EINVAL;
  4557. }
  4558. device->packetization_type = HFI_PACKETIZATION_4XX;
  4559. device->pkt_ops = cvp_hfi_get_pkt_ops_handle(
  4560. device->packetization_type);
  4561. if (!device->pkt_ops) {
  4562. rc = -EINVAL;
  4563. dprintk(CVP_ERR, "Failed to get pkt_ops handle\n");
  4564. }
  4565. return rc;
  4566. }
  4567. void __init_cvp_ops(struct iris_hfi_device *device)
  4568. {
  4569. device->hal_ops = &hal_ops;
  4570. }
  4571. static struct iris_hfi_device *__add_device(struct msm_cvp_platform_resources *res,
  4572. hfi_cmd_response_callback callback)
  4573. {
  4574. struct iris_hfi_device *hdevice = NULL;
  4575. int rc = 0;
  4576. if (!res || !callback) {
  4577. dprintk(CVP_ERR, "Invalid Parameters\n");
  4578. return NULL;
  4579. }
  4580. hdevice = kzalloc(sizeof(*hdevice), GFP_KERNEL);
  4581. if (!hdevice) {
  4582. dprintk(CVP_ERR, "failed to allocate new device\n");
  4583. goto exit;
  4584. }
  4585. hdevice->response_pkt = kmalloc_array(cvp_max_packets,
  4586. sizeof(*hdevice->response_pkt), GFP_KERNEL);
  4587. if (!hdevice->response_pkt) {
  4588. dprintk(CVP_ERR, "failed to allocate response_pkt\n");
  4589. goto err_cleanup;
  4590. }
  4591. hdevice->raw_packet =
  4592. kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  4593. if (!hdevice->raw_packet) {
  4594. dprintk(CVP_ERR, "failed to allocate raw packet\n");
  4595. goto err_cleanup;
  4596. }
  4597. rc = vm_manager.vm_ops->vm_init_reg_and_irq(hdevice, res);
  4598. if (rc)
  4599. goto err_cleanup;
  4600. hdevice->res = res;
  4601. hdevice->callback = callback;
  4602. __init_cvp_ops(hdevice);
  4603. hdevice->cvp_workq = create_singlethread_workqueue(
  4604. "msm_cvp_workerq_iris");
  4605. if (!hdevice->cvp_workq) {
  4606. dprintk(CVP_ERR, ": create cvp workq failed\n");
  4607. goto err_cleanup;
  4608. }
  4609. hdevice->iris_pm_workq = create_singlethread_workqueue(
  4610. "pm_workerq_iris");
  4611. if (!hdevice->iris_pm_workq) {
  4612. dprintk(CVP_ERR, ": create pm workq failed\n");
  4613. goto err_cleanup;
  4614. }
  4615. mutex_init(&hdevice->lock);
  4616. INIT_LIST_HEAD(&hdevice->sess_head);
  4617. return hdevice;
  4618. err_cleanup:
  4619. if (hdevice->iris_pm_workq)
  4620. destroy_workqueue(hdevice->iris_pm_workq);
  4621. if (hdevice->cvp_workq)
  4622. destroy_workqueue(hdevice->cvp_workq);
  4623. kfree(hdevice->response_pkt);
  4624. kfree(hdevice->raw_packet);
  4625. kfree(hdevice);
  4626. exit:
  4627. return NULL;
  4628. }
  4629. static struct iris_hfi_device *__get_device(struct msm_cvp_platform_resources *res,
  4630. hfi_cmd_response_callback callback)
  4631. {
  4632. if (!res || !callback) {
  4633. dprintk(CVP_ERR, "Invalid params: %pK %pK\n", res, callback);
  4634. return NULL;
  4635. }
  4636. return __add_device(res, callback);
  4637. }
  4638. void cvp_iris_hfi_delete_device(void *device)
  4639. {
  4640. struct msm_cvp_core *core;
  4641. struct iris_hfi_device *dev = NULL;
  4642. if (!device)
  4643. return;
  4644. core = cvp_driver->cvp_core;
  4645. if (core)
  4646. dev = core->dev_ops->hfi_device_data;
  4647. if (!dev)
  4648. return;
  4649. mutex_destroy(&dev->lock);
  4650. destroy_workqueue(dev->cvp_workq);
  4651. destroy_workqueue(dev->iris_pm_workq);
  4652. free_irq(dev->cvp_hal_data->irq, dev);
  4653. iounmap(dev->cvp_hal_data->register_base);
  4654. iounmap(dev->cvp_hal_data->gcc_reg_base);
  4655. kfree(dev->cvp_hal_data);
  4656. kfree(dev->response_pkt);
  4657. kfree(dev->raw_packet);
  4658. kfree(dev);
  4659. }
  4660. static int iris_hfi_validate_session(void *sess, const char *func)
  4661. {
  4662. struct cvp_hal_session *session = sess;
  4663. int rc = 0;
  4664. struct iris_hfi_device *device;
  4665. if (!session || !session->device) {
  4666. dprintk(CVP_ERR, " %s Invalid Params %pK\n", __func__, session);
  4667. return -EINVAL;
  4668. }
  4669. device = session->device;
  4670. mutex_lock(&device->lock);
  4671. if (!__is_session_valid(device, session, func))
  4672. rc = -ECONNRESET;
  4673. mutex_unlock(&device->lock);
  4674. return rc;
  4675. }
  4676. static void iris_init_hfi_callbacks(struct cvp_hfi_ops *ops_tbl)
  4677. {
  4678. ops_tbl->core_init = iris_hfi_core_init;
  4679. ops_tbl->core_release = iris_hfi_core_release;
  4680. ops_tbl->core_trigger_ssr = iris_hfi_core_trigger_ssr;
  4681. ops_tbl->session_init = iris_hfi_session_init;
  4682. ops_tbl->session_end = iris_hfi_session_end;
  4683. ops_tbl->session_start = iris_hfi_session_start;
  4684. ops_tbl->session_stop = iris_hfi_session_stop;
  4685. ops_tbl->session_abort = iris_hfi_session_abort;
  4686. ops_tbl->session_clean = iris_hfi_session_clean;
  4687. ops_tbl->session_set_buffers = iris_hfi_session_set_buffers;
  4688. ops_tbl->session_release_buffers = iris_hfi_session_release_buffers;
  4689. ops_tbl->session_send = iris_hfi_session_send;
  4690. ops_tbl->session_flush = iris_hfi_session_flush;
  4691. ops_tbl->scale_clocks = iris_hfi_scale_clocks;
  4692. ops_tbl->vote_bus = iris_hfi_vote_buses;
  4693. ops_tbl->get_fw_info = iris_hfi_get_fw_info;
  4694. ops_tbl->get_core_capabilities = iris_hfi_get_core_capabilities;
  4695. ops_tbl->suspend = iris_hfi_suspend;
  4696. ops_tbl->resume = iris_hfi_resume;
  4697. ops_tbl->flush_debug_queue = iris_hfi_flush_debug_queue;
  4698. ops_tbl->noc_error_info = iris_hfi_noc_error_info;
  4699. ops_tbl->validate_session = iris_hfi_validate_session;
  4700. ops_tbl->pm_qos_update = iris_pm_qos_update;
  4701. ops_tbl->debug_hook = iris_debug_hook;
  4702. }
  4703. int cvp_iris_hfi_initialize(struct cvp_hfi_ops *ops_tbl,
  4704. struct msm_cvp_platform_resources *res,
  4705. hfi_cmd_response_callback callback)
  4706. {
  4707. int rc = 0;
  4708. if (!ops_tbl || !res || !callback) {
  4709. dprintk(CVP_ERR, "Invalid params: %pK %pK %pK\n",
  4710. ops_tbl, res, callback);
  4711. rc = -EINVAL;
  4712. goto err_iris_hfi_init;
  4713. }
  4714. ops_tbl->hfi_device_data = __get_device(res, callback);
  4715. if (IS_ERR_OR_NULL(ops_tbl->hfi_device_data)) {
  4716. rc = PTR_ERR(ops_tbl->hfi_device_data) ?: -EINVAL;
  4717. goto err_iris_hfi_init;
  4718. }
  4719. iris_init_hfi_callbacks(ops_tbl);
  4720. err_iris_hfi_init:
  4721. return rc;
  4722. }
  4723. static void dump_noc_reg(struct iris_hfi_device *device)
  4724. {
  4725. u32 val = 0, config;
  4726. int i;
  4727. struct regulator_info *rinfo;
  4728. int rc = 0;
  4729. if (msm_cvp_fw_low_power_mode) {
  4730. iris_hfi_for_each_regulator(device, rinfo) {
  4731. if (strcmp(rinfo->name, "cvp-core"))
  4732. continue;
  4733. rc = __acquire_regulator(rinfo, device);
  4734. if (rc)
  4735. dprintk(CVP_WARN,
  4736. "%s, Failed to acquire regulator control: %s\n",
  4737. __func__, rinfo->name);
  4738. }
  4739. }
  4740. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4741. dprintk(CVP_ERR, "%s, CVP_CC_MVS1_GDSCR: 0x%x", __func__, val);
  4742. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4743. dprintk(CVP_ERR, "%s, CVP_WRAPPER_CORE_CLOCK_CONFIG: 0x%x", __func__, config);
  4744. if (config) {
  4745. dprintk(CVP_PWR,
  4746. "core clock config not enabled, enable it to access core\n");
  4747. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4748. }
  4749. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4750. if (i) {
  4751. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4752. return;
  4753. }
  4754. val = __read_register(device, CVP_NOC_RGE_NIU_DECCTL_LOW);
  4755. dprintk(CVP_ERR, "CVP_NOC_RGE_NIU_DECCTL_LOW: 0x%x", val);
  4756. val = __read_register(device, CVP_NOC_RGE_NIU_ENCCTL_LOW);
  4757. dprintk(CVP_ERR, "CVP_NOC_RGE_NIU_ENCCTL_LOW: 0x%x", val);
  4758. val = __read_register(device, CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW);
  4759. dprintk(CVP_ERR, "CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW: 0x%x", val);
  4760. val = __read_register(device, CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW);
  4761. dprintk(CVP_ERR, "CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW: 0x%x", val);
  4762. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS);
  4763. dprintk(CVP_ERR, "CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS: 0x%x", val);
  4764. val = __read_register(device, CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW);
  4765. dprintk(CVP_ERR, "CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW: 0x%x", val);
  4766. dprintk(CVP_ERR, "Dumping Core NoC registers\n");
  4767. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_LOW_OFFS);
  4768. dprintk(CVP_ERR, "CVP_NOC__CORE_ERL_MAIN_SWID_LOW: 0x%x", val);
  4769. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_HIGH_OFFS);
  4770. dprintk(CVP_ERR, "CVVP_NOC_CORE_ERL_MAIN_SWID_HIGH 0x%x", val);
  4771. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS);
  4772. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW 0x%x", val);
  4773. val = __read_register(device, CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS);
  4774. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW 0x%x", val);
  4775. val = __read_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS);
  4776. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW 0x%x", val);
  4777. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS);
  4778. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW 0x%x", val);
  4779. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS);
  4780. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH 0x%x", val);
  4781. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS);
  4782. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW 0x%x", val);
  4783. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS);
  4784. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH 0x%x", val);
  4785. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS);
  4786. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW 0x%x", val);
  4787. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS);
  4788. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH 0x%x", val);
  4789. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS);
  4790. dprintk(CVP_ERR, "CORE ERRLOG3_LOW 0x%x, below details", val);
  4791. __print_reg_details(val);
  4792. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS);
  4793. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH 0x%x", val);
  4794. __write_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS, 0x1);
  4795. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4796. if (msm_cvp_fw_low_power_mode) {
  4797. iris_hfi_for_each_regulator(device, rinfo) {
  4798. if (strcmp(rinfo->name, "cvp-core"))
  4799. continue;
  4800. rc = __hand_off_regulator(rinfo);
  4801. }
  4802. }
  4803. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4804. }