sde_rm.c 74 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  7. #include "sde_kms.h"
  8. #include "sde_hw_lm.h"
  9. #include "sde_hw_ctl.h"
  10. #include "sde_hw_cdm.h"
  11. #include "sde_hw_dspp.h"
  12. #include "sde_hw_ds.h"
  13. #include "sde_hw_pingpong.h"
  14. #include "sde_hw_intf.h"
  15. #include "sde_hw_wb.h"
  16. #include "sde_encoder.h"
  17. #include "sde_connector.h"
  18. #include "sde_hw_dsc.h"
  19. #include "sde_hw_vdc.h"
  20. #include "sde_crtc.h"
  21. #include "sde_hw_qdss.h"
  22. #include "sde_vbif.h"
  23. #include "sde_hw_dnsc_blur.h"
  24. #define RESERVED_BY_OTHER(h, r) \
  25. (((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
  26. ((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
  27. #define RESERVED_BY_CURRENT(h, r) \
  28. (((h)->rsvp && ((h)->rsvp->enc_id == (r)->enc_id)))
  29. #define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
  30. #define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
  31. #define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
  32. #define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))
  33. #define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))
  34. #define RM_RQ_DCWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DCWB))
  35. #define RM_RQ_DNSC_BLUR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DNSC_BLUR))
  36. #define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
  37. (t).num_comp_enc == (r).num_enc && \
  38. (t).num_intf == (r).num_intf && \
  39. (t).comp_type == (r).comp_type)
  40. #define IS_COMPATIBLE_PP_DSC(p, d) (p % 2 == d % 2)
  41. /* ~one vsync poll time for rsvp_nxt to cleared by modeset from commit thread */
  42. #define RM_NXT_CLEAR_POLL_TIMEOUT_US 33000
  43. /**
  44. * toplogy information to be used when ctl path version does not
  45. * support driving more than one interface per ctl_path
  46. */
  47. static const struct sde_rm_topology_def g_top_table[SDE_RM_TOPOLOGY_MAX] = {
  48. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  49. MSM_DISPLAY_COMPRESSION_NONE },
  50. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  51. MSM_DISPLAY_COMPRESSION_NONE },
  52. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  53. MSM_DISPLAY_COMPRESSION_DSC },
  54. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true,
  55. MSM_DISPLAY_COMPRESSION_NONE },
  56. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 2, true,
  57. MSM_DISPLAY_COMPRESSION_DSC },
  58. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  59. MSM_DISPLAY_COMPRESSION_NONE },
  60. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  61. MSM_DISPLAY_COMPRESSION_DSC },
  62. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  63. MSM_DISPLAY_COMPRESSION_DSC },
  64. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true,
  65. MSM_DISPLAY_COMPRESSION_NONE },
  66. };
  67. /**
  68. * topology information to be used when the ctl path version
  69. * is SDE_CTL_CFG_VERSION_1_0_0
  70. */
  71. static const struct sde_rm_topology_def g_top_table_v1[SDE_RM_TOPOLOGY_MAX] = {
  72. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  73. MSM_DISPLAY_COMPRESSION_NONE },
  74. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  75. MSM_DISPLAY_COMPRESSION_NONE },
  76. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  77. MSM_DISPLAY_COMPRESSION_DSC },
  78. { SDE_RM_TOPOLOGY_SINGLEPIPE_VDC, 1, 1, 1, 1, false,
  79. MSM_DISPLAY_COMPRESSION_VDC },
  80. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 1, false,
  81. MSM_DISPLAY_COMPRESSION_NONE },
  82. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 1, false,
  83. MSM_DISPLAY_COMPRESSION_DSC },
  84. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  85. MSM_DISPLAY_COMPRESSION_NONE },
  86. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  87. MSM_DISPLAY_COMPRESSION_DSC },
  88. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC, 2, 1, 1, 1, false,
  89. MSM_DISPLAY_COMPRESSION_VDC },
  90. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  91. MSM_DISPLAY_COMPRESSION_DSC },
  92. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, false,
  93. MSM_DISPLAY_COMPRESSION_NONE },
  94. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE, 4, 0, 2, 1, false,
  95. MSM_DISPLAY_COMPRESSION_NONE },
  96. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE_DSC, 4, 3, 2, 1, false,
  97. MSM_DISPLAY_COMPRESSION_DSC },
  98. { SDE_RM_TOPOLOGY_QUADPIPE_DSCMERGE, 4, 4, 2, 1, false,
  99. MSM_DISPLAY_COMPRESSION_DSC },
  100. { SDE_RM_TOPOLOGY_QUADPIPE_DSC4HSMERGE, 4, 4, 1, 1, false,
  101. MSM_DISPLAY_COMPRESSION_DSC },
  102. };
  103. char sde_hw_blk_str[SDE_HW_BLK_MAX][SDE_HW_BLK_NAME_LEN] = {
  104. "top",
  105. "sspp",
  106. "lm",
  107. "dspp",
  108. "ds",
  109. "ctl",
  110. "cdm",
  111. "pingpong",
  112. "intf",
  113. "wb",
  114. "dsc",
  115. "vdc",
  116. "merge_3d",
  117. "qdss",
  118. "dnsc_blur"
  119. };
  120. /**
  121. * struct sde_rm_requirements - Reservation requirements parameter bundle
  122. * @top_ctrl: topology control preference from kernel client
  123. * @top: selected topology for the display
  124. * @hw_res: Hardware resources required as reported by the encoders
  125. * @conn_lm_mask: preferred LM mask of cwb requested display
  126. */
  127. struct sde_rm_requirements {
  128. uint64_t top_ctrl;
  129. const struct sde_rm_topology_def *topology;
  130. struct sde_encoder_hw_resources hw_res;
  131. u32 conn_lm_mask;
  132. };
  133. /**
  134. * struct sde_rm_rsvp - Use Case Reservation tagging structure
  135. * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
  136. * By using as a tag, rather than lists of pointers to HW blocks used
  137. * we can avoid some list management since we don't know how many blocks
  138. * of each type a given use case may require.
  139. * @list: List head for list of all reservations
  140. * @seq: Global RSVP sequence number for debugging, especially for
  141. * differentiating differenct allocations for same encoder.
  142. * @enc_id: Reservations are tracked by Encoder DRM object ID.
  143. * CRTCs may be connected to multiple Encoders.
  144. * An encoder or connector id identifies the display path.
  145. * @topology: DRM<->HW topology use case
  146. * @pending: True for pending rsvp-nxt, cleared when the rsvp is committed
  147. */
  148. struct sde_rm_rsvp {
  149. struct list_head list;
  150. uint32_t seq;
  151. uint32_t enc_id;
  152. enum sde_rm_topology_name topology;
  153. bool pending;
  154. };
  155. /**
  156. * struct sde_rm_hw_blk - hardware block tracking list member
  157. * @list: List head for list of all hardware blocks tracking items
  158. * @rsvp: Pointer to use case reservation if reserved by a client
  159. * @rsvp_nxt: Temporary pointer used during reservation to the incoming
  160. * request. Will be swapped into rsvp if proposal is accepted
  161. * @type: Type of hardware block this structure tracks
  162. * @id: Hardware ID number, within it's own space, ie. LM_X
  163. * @catalog: Pointer to the hardware catalog entry for this block
  164. * @hw: Pointer to the hardware register access object for this block
  165. */
  166. struct sde_rm_hw_blk {
  167. struct list_head list;
  168. struct sde_rm_rsvp *rsvp;
  169. struct sde_rm_rsvp *rsvp_nxt;
  170. enum sde_hw_blk_type type;
  171. uint32_t id;
  172. struct sde_hw_blk_reg_map *hw;
  173. };
  174. /**
  175. * sde_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
  176. */
  177. enum sde_rm_dbg_rsvp_stage {
  178. SDE_RM_STAGE_BEGIN,
  179. SDE_RM_STAGE_AFTER_CLEAR,
  180. SDE_RM_STAGE_AFTER_RSVPNEXT,
  181. SDE_RM_STAGE_FINAL
  182. };
  183. static void _sde_rm_inc_resource_info_lm(struct sde_rm *rm,
  184. struct msm_resource_caps_info *avail_res,
  185. struct sde_rm_hw_blk *blk)
  186. {
  187. struct sde_rm_hw_blk *blk2;
  188. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  189. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  190. /* Do not track & expose dummy mixers */
  191. if (lm_cfg->dummy_mixer)
  192. return;
  193. avail_res->num_lm++;
  194. /* Check for 3d muxes by comparing paired lms */
  195. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  196. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  197. /*
  198. * If lm2 is free, or
  199. * lm1 & lm2 reserved by same enc, check mask
  200. */
  201. if ((!blk2->rsvp || (blk->rsvp &&
  202. blk2->rsvp->enc_id == blk->rsvp->enc_id
  203. && lm_cfg->id > lm_cfg2->id)) &&
  204. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  205. avail_res->num_3dmux++;
  206. }
  207. }
  208. static void _sde_rm_dec_resource_info_lm(struct sde_rm *rm,
  209. struct msm_resource_caps_info *avail_res,
  210. struct sde_rm_hw_blk *blk)
  211. {
  212. struct sde_rm_hw_blk *blk2;
  213. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  214. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  215. /* Do not track & expose dummy mixers */
  216. if (lm_cfg->dummy_mixer)
  217. return;
  218. avail_res->num_lm--;
  219. /* Check for 3d muxes by comparing paired lms */
  220. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  221. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  222. /* If lm2 is free and lm1 is now being reserved */
  223. if (!blk2->rsvp &&
  224. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  225. avail_res->num_3dmux--;
  226. }
  227. }
  228. static void _sde_rm_inc_resource_info(struct sde_rm *rm,
  229. struct msm_resource_caps_info *avail_res,
  230. struct sde_rm_hw_blk *blk)
  231. {
  232. enum sde_hw_blk_type type = blk->type;
  233. if (type == SDE_HW_BLK_LM)
  234. _sde_rm_inc_resource_info_lm(rm, avail_res, blk);
  235. else if (type == SDE_HW_BLK_CTL)
  236. avail_res->num_ctl++;
  237. else if (type == SDE_HW_BLK_DSC)
  238. avail_res->num_dsc++;
  239. else if (type == SDE_HW_BLK_VDC)
  240. avail_res->num_vdc++;
  241. }
  242. static void _sde_rm_dec_resource_info(struct sde_rm *rm,
  243. struct msm_resource_caps_info *avail_res,
  244. struct sde_rm_hw_blk *blk)
  245. {
  246. enum sde_hw_blk_type type = blk->type;
  247. if (type == SDE_HW_BLK_LM)
  248. _sde_rm_dec_resource_info_lm(rm, avail_res, blk);
  249. else if (type == SDE_HW_BLK_CTL)
  250. avail_res->num_ctl--;
  251. else if (type == SDE_HW_BLK_DSC)
  252. avail_res->num_dsc--;
  253. else if (type == SDE_HW_BLK_VDC)
  254. avail_res->num_vdc--;
  255. }
  256. void sde_rm_get_resource_info(struct sde_rm *rm,
  257. struct drm_encoder *drm_enc,
  258. struct msm_resource_caps_info *avail_res)
  259. {
  260. struct sde_rm_hw_blk *blk;
  261. enum sde_hw_blk_type type;
  262. const struct sde_lm_cfg *lm_cfg;
  263. bool is_built_in, is_pref;
  264. u32 lm_pref = (BIT(SDE_DISP_PRIMARY_PREF) | BIT(SDE_DISP_SECONDARY_PREF));
  265. mutex_lock(&rm->rm_lock);
  266. /* Get all currently available resources */
  267. memcpy(avail_res, &rm->avail_res,
  268. sizeof(rm->avail_res));
  269. /**
  270. * When the encoder is null, assume display is external in order to return the count of
  271. * availalbe non-preferred LMs
  272. */
  273. if (!drm_enc)
  274. is_built_in = false;
  275. else
  276. is_built_in = sde_encoder_is_built_in_display(drm_enc);
  277. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  278. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  279. /* Add back resources allocated to the given encoder */
  280. if (blk->rsvp && drm_enc && blk->rsvp->enc_id == drm_enc->base.id) {
  281. _sde_rm_inc_resource_info(rm, avail_res, blk);
  282. if (type == SDE_HW_BLK_LM)
  283. avail_res->num_lm_in_use++;
  284. }
  285. /**
  286. * Remove unallocated preferred lms that cannot reserved
  287. * by non built-in displays.
  288. */
  289. if (type == SDE_HW_BLK_LM) {
  290. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  291. is_pref = lm_cfg->features & lm_pref;
  292. if (!blk->rsvp && !blk->rsvp_nxt && !is_built_in && is_pref)
  293. _sde_rm_dec_resource_info(rm, avail_res, blk);
  294. }
  295. }
  296. }
  297. mutex_unlock(&rm->rm_lock);
  298. }
  299. static void _sde_rm_print_rsvps(
  300. struct sde_rm *rm,
  301. enum sde_rm_dbg_rsvp_stage stage)
  302. {
  303. struct sde_rm_rsvp *rsvp;
  304. struct sde_rm_hw_blk *blk;
  305. enum sde_hw_blk_type type;
  306. SDE_DEBUG("%d\n", stage);
  307. list_for_each_entry(rsvp, &rm->rsvps, list) {
  308. SDE_DEBUG("%d rsvp%s[s%ue%u] topology %d\n", stage, rsvp->pending ? "_nxt" : "",
  309. rsvp->seq, rsvp->enc_id, rsvp->topology);
  310. SDE_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology, rsvp->pending);
  311. }
  312. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  313. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  314. if (!blk->rsvp && !blk->rsvp_nxt)
  315. continue;
  316. SDE_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
  317. (blk->rsvp) ? blk->rsvp->seq : 0,
  318. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  319. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  320. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  321. blk->type, blk->id);
  322. SDE_EVT32(stage,
  323. (blk->rsvp) ? blk->rsvp->seq : 0,
  324. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  325. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  326. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  327. blk->type, blk->id);
  328. }
  329. }
  330. }
  331. static void _sde_rm_print_rsvps_by_type(
  332. struct sde_rm *rm,
  333. enum sde_hw_blk_type type)
  334. {
  335. struct sde_rm_hw_blk *blk;
  336. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  337. if (!blk->rsvp && !blk->rsvp_nxt)
  338. continue;
  339. SDE_ERROR("rsvp[s%ue%u->s%ue%u] %d %d\n",
  340. (blk->rsvp) ? blk->rsvp->seq : 0,
  341. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  342. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  343. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  344. blk->type, blk->id);
  345. SDE_EVT32((blk->rsvp) ? blk->rsvp->seq : 0,
  346. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  347. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  348. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  349. blk->type, blk->id);
  350. }
  351. }
  352. struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm)
  353. {
  354. return rm->hw_mdp;
  355. }
  356. void sde_rm_init_hw_iter(
  357. struct sde_rm_hw_iter *iter,
  358. uint32_t enc_id,
  359. enum sde_hw_blk_type type)
  360. {
  361. memset(iter, 0, sizeof(*iter));
  362. iter->enc_id = enc_id;
  363. iter->type = type;
  364. }
  365. enum sde_rm_topology_name sde_rm_get_topology_name(struct sde_rm *rm,
  366. struct msm_display_topology topology)
  367. {
  368. int i;
  369. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  370. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  371. topology))
  372. return rm->topology_tbl[i].top_name;
  373. return SDE_RM_TOPOLOGY_NONE;
  374. }
  375. static bool _sde_rm_get_hw_locked(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  376. {
  377. struct list_head *blk_list;
  378. if (!rm || !i || i->type >= SDE_HW_BLK_MAX) {
  379. SDE_ERROR("invalid rm\n");
  380. return false;
  381. }
  382. i->hw = NULL;
  383. blk_list = &rm->hw_blks[i->type];
  384. if (i->blk && (&i->blk->list == blk_list)) {
  385. SDE_DEBUG("attempt resume iteration past last\n");
  386. return false;
  387. }
  388. i->blk = list_prepare_entry(i->blk, blk_list, list);
  389. list_for_each_entry_continue(i->blk, blk_list, list) {
  390. struct sde_rm_rsvp *rsvp = i->blk->rsvp;
  391. if (i->blk->type != i->type) {
  392. SDE_ERROR("found incorrect block type %d on %d list\n",
  393. i->blk->type, i->type);
  394. return false;
  395. }
  396. if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
  397. i->hw = i->blk->hw;
  398. SDE_DEBUG("found type %d id %d for enc %d\n",
  399. i->type, i->blk->id, i->enc_id);
  400. return true;
  401. }
  402. }
  403. SDE_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
  404. return false;
  405. }
  406. static bool _sde_rm_request_hw_blk_locked(struct sde_rm *rm,
  407. struct sde_rm_hw_request *hw_blk_info)
  408. {
  409. struct list_head *blk_list;
  410. struct sde_rm_hw_blk *blk = NULL;
  411. if (!rm || !hw_blk_info || hw_blk_info->type >= SDE_HW_BLK_MAX) {
  412. SDE_ERROR("invalid rm\n");
  413. return false;
  414. }
  415. hw_blk_info->hw = NULL;
  416. blk_list = &rm->hw_blks[hw_blk_info->type];
  417. blk = list_prepare_entry(blk, blk_list, list);
  418. list_for_each_entry_continue(blk, blk_list, list) {
  419. if (blk->type != hw_blk_info->type) {
  420. SDE_ERROR("found incorrect block type %d on %d list\n",
  421. blk->type, hw_blk_info->type);
  422. return false;
  423. }
  424. if (blk->id == hw_blk_info->id) {
  425. hw_blk_info->hw = blk->hw;
  426. SDE_DEBUG("found type %d id %d\n",
  427. blk->type, blk->id);
  428. return true;
  429. }
  430. }
  431. SDE_DEBUG("no match, type %d id %d\n", hw_blk_info->type,
  432. hw_blk_info->id);
  433. return false;
  434. }
  435. bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  436. {
  437. bool ret;
  438. mutex_lock(&rm->rm_lock);
  439. ret = _sde_rm_get_hw_locked(rm, i);
  440. mutex_unlock(&rm->rm_lock);
  441. return ret;
  442. }
  443. bool sde_rm_request_hw_blk(struct sde_rm *rm, struct sde_rm_hw_request *hw)
  444. {
  445. bool ret;
  446. mutex_lock(&rm->rm_lock);
  447. ret = _sde_rm_request_hw_blk_locked(rm, hw);
  448. mutex_unlock(&rm->rm_lock);
  449. return ret;
  450. }
  451. static void _sde_rm_hw_destroy(enum sde_hw_blk_type type, struct sde_hw_blk_reg_map *hw)
  452. {
  453. switch (type) {
  454. case SDE_HW_BLK_LM:
  455. sde_hw_lm_destroy(hw);
  456. break;
  457. case SDE_HW_BLK_DSPP:
  458. sde_hw_dspp_destroy(hw);
  459. break;
  460. case SDE_HW_BLK_DS:
  461. sde_hw_ds_destroy(hw);
  462. break;
  463. case SDE_HW_BLK_CTL:
  464. sde_hw_ctl_destroy(hw);
  465. break;
  466. case SDE_HW_BLK_CDM:
  467. sde_hw_cdm_destroy(hw);
  468. break;
  469. case SDE_HW_BLK_PINGPONG:
  470. sde_hw_pingpong_destroy(hw);
  471. break;
  472. case SDE_HW_BLK_INTF:
  473. sde_hw_intf_destroy(hw);
  474. break;
  475. case SDE_HW_BLK_WB:
  476. sde_hw_wb_destroy(hw);
  477. break;
  478. case SDE_HW_BLK_DSC:
  479. sde_hw_dsc_destroy(hw);
  480. break;
  481. case SDE_HW_BLK_VDC:
  482. sde_hw_vdc_destroy(hw);
  483. break;
  484. case SDE_HW_BLK_QDSS:
  485. sde_hw_qdss_destroy(hw);
  486. break;
  487. case SDE_HW_BLK_DNSC_BLUR:
  488. sde_hw_dnsc_blur_destroy(hw);
  489. break;
  490. case SDE_HW_BLK_SSPP:
  491. /* SSPPs are not managed by the resource manager */
  492. case SDE_HW_BLK_TOP:
  493. /* Top is a singleton, not managed in hw_blks list */
  494. case SDE_HW_BLK_MAX:
  495. default:
  496. SDE_ERROR("unsupported block type %d\n", type);
  497. break;
  498. }
  499. }
  500. static void _deinit_hw_fences(struct sde_rm *rm)
  501. {
  502. struct sde_rm_hw_iter iter;
  503. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  504. while (_sde_rm_get_hw_locked(rm, &iter)) {
  505. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  506. sde_hw_fence_deinit(ctl);
  507. }
  508. }
  509. int sde_rm_destroy(struct sde_rm *rm)
  510. {
  511. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  512. struct sde_rm_hw_blk *hw_cur, *hw_nxt;
  513. enum sde_hw_blk_type type;
  514. if (!rm) {
  515. SDE_ERROR("invalid rm\n");
  516. return -EINVAL;
  517. }
  518. _deinit_hw_fences(rm);
  519. list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
  520. list_del(&rsvp_cur->list);
  521. kfree(rsvp_cur);
  522. }
  523. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  524. list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
  525. list) {
  526. list_del(&hw_cur->list);
  527. _sde_rm_hw_destroy(hw_cur->type, hw_cur->hw);
  528. kfree(hw_cur);
  529. }
  530. }
  531. sde_hw_mdp_destroy(rm->hw_mdp);
  532. rm->hw_mdp = NULL;
  533. mutex_destroy(&rm->rm_lock);
  534. return 0;
  535. }
  536. static int _sde_rm_hw_blk_create(
  537. struct sde_rm *rm,
  538. struct sde_mdss_cfg *cat,
  539. void __iomem *mmio,
  540. enum sde_hw_blk_type type,
  541. uint32_t id,
  542. void *hw_catalog_info)
  543. {
  544. int rc;
  545. struct sde_rm_hw_blk *blk;
  546. struct sde_hw_mdp *hw_mdp;
  547. struct sde_hw_blk_reg_map *hw;
  548. struct sde_kms *sde_kms = to_sde_kms(ddev_to_msm_kms(rm->dev));
  549. struct sde_vbif_clk_client clk_client = {0};
  550. hw_mdp = rm->hw_mdp;
  551. switch (type) {
  552. case SDE_HW_BLK_LM:
  553. hw = sde_hw_lm_init(id, mmio, cat);
  554. break;
  555. case SDE_HW_BLK_DSPP:
  556. hw = sde_hw_dspp_init(id, mmio, cat);
  557. break;
  558. case SDE_HW_BLK_DS:
  559. hw = sde_hw_ds_init(id, mmio, cat);
  560. break;
  561. case SDE_HW_BLK_CTL:
  562. hw = sde_hw_ctl_init(id, mmio, cat);
  563. break;
  564. case SDE_HW_BLK_CDM:
  565. hw = sde_hw_cdm_init(id, mmio, cat, hw_mdp);
  566. break;
  567. case SDE_HW_BLK_PINGPONG:
  568. hw = sde_hw_pingpong_init(id, mmio, cat);
  569. break;
  570. case SDE_HW_BLK_INTF:
  571. hw = sde_hw_intf_init(id, mmio, cat);
  572. break;
  573. case SDE_HW_BLK_WB:
  574. hw = sde_hw_wb_init(id, mmio, cat, hw_mdp, &clk_client);
  575. break;
  576. case SDE_HW_BLK_DSC:
  577. hw = sde_hw_dsc_init(id, mmio, cat);
  578. break;
  579. case SDE_HW_BLK_VDC:
  580. hw = sde_hw_vdc_init(id, mmio, cat);
  581. break;
  582. case SDE_HW_BLK_QDSS:
  583. hw = sde_hw_qdss_init(id, mmio, cat);
  584. break;
  585. case SDE_HW_BLK_DNSC_BLUR:
  586. hw = sde_hw_dnsc_blur_init(id, mmio, cat);
  587. break;
  588. case SDE_HW_BLK_SSPP:
  589. /* SSPPs are not managed by the resource manager */
  590. case SDE_HW_BLK_TOP:
  591. /* Top is a singleton, not managed in hw_blks list */
  592. case SDE_HW_BLK_MAX:
  593. default:
  594. SDE_ERROR("unsupported block type %d\n", type);
  595. return -EINVAL;
  596. }
  597. if (IS_ERR_OR_NULL(hw)) {
  598. SDE_ERROR("failed hw object creation: type %d, err %ld\n",
  599. type, PTR_ERR(hw));
  600. return -EFAULT;
  601. }
  602. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  603. if (!blk) {
  604. _sde_rm_hw_destroy(type, hw);
  605. return -ENOMEM;
  606. }
  607. blk->type = type;
  608. blk->id = id;
  609. blk->hw = hw;
  610. list_add_tail(&blk->list, &rm->hw_blks[type]);
  611. _sde_rm_inc_resource_info(rm, &rm->avail_res, blk);
  612. if (sde_kms && sde_kms->catalog &&
  613. test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, sde_kms->catalog->features) &&
  614. SDE_CLK_CTRL_VALID(clk_client.clk_ctrl)) {
  615. rc = sde_vbif_clk_register(sde_kms, &clk_client);
  616. if (rc) {
  617. SDE_ERROR("failed to register vbif client %d\n", clk_client.clk_ctrl);
  618. return -EFAULT;
  619. }
  620. }
  621. return 0;
  622. }
  623. static int _init_hw_fences(struct sde_rm *rm, bool use_ipcc)
  624. {
  625. struct sde_rm_hw_iter iter;
  626. int ret = 0;
  627. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  628. while (_sde_rm_get_hw_locked(rm, &iter)) {
  629. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  630. if (sde_hw_fence_init(ctl, use_ipcc)) {
  631. pr_err("failed to init hw_fence idx:%d\n", ctl->idx);
  632. ret = -EINVAL;
  633. break;
  634. }
  635. SDE_DEBUG("init hw-fence for ctl %d", iter.blk->id);
  636. }
  637. if (ret)
  638. _deinit_hw_fences(rm);
  639. return ret;
  640. }
  641. static int _sde_rm_hw_blk_create_new(struct sde_rm *rm,
  642. struct sde_mdss_cfg *cat,
  643. void __iomem *mmio)
  644. {
  645. int i, rc = 0;
  646. for (i = 0; i < cat->dspp_count; i++) {
  647. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSPP,
  648. cat->dspp[i].id, &cat->dspp[i]);
  649. if (rc) {
  650. SDE_ERROR("failed: dspp hw not available\n");
  651. goto fail;
  652. }
  653. }
  654. if (cat->mdp[0].has_dest_scaler) {
  655. for (i = 0; i < cat->ds_count; i++) {
  656. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DS,
  657. cat->ds[i].id, &cat->ds[i]);
  658. if (rc) {
  659. SDE_ERROR("failed: ds hw not available\n");
  660. goto fail;
  661. }
  662. }
  663. }
  664. for (i = 0; i < cat->pingpong_count; i++) {
  665. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_PINGPONG,
  666. cat->pingpong[i].id, &cat->pingpong[i]);
  667. if (rc) {
  668. SDE_ERROR("failed: pp hw not available\n");
  669. goto fail;
  670. }
  671. }
  672. for (i = 0; i < cat->dsc_count; i++) {
  673. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSC,
  674. cat->dsc[i].id, &cat->dsc[i]);
  675. if (rc) {
  676. SDE_ERROR("failed: dsc hw not available\n");
  677. goto fail;
  678. }
  679. }
  680. for (i = 0; i < cat->vdc_count; i++) {
  681. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_VDC,
  682. cat->vdc[i].id, &cat->vdc[i]);
  683. if (rc) {
  684. SDE_ERROR("failed: vdc hw not available\n");
  685. goto fail;
  686. }
  687. }
  688. for (i = 0; i < cat->intf_count; i++) {
  689. if (cat->intf[i].type == INTF_NONE) {
  690. SDE_DEBUG("skip intf %d with type none\n", i);
  691. continue;
  692. }
  693. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_INTF,
  694. cat->intf[i].id, &cat->intf[i]);
  695. if (rc) {
  696. SDE_ERROR("failed: intf hw not available\n");
  697. goto fail;
  698. }
  699. }
  700. for (i = 0; i < cat->wb_count; i++) {
  701. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_WB,
  702. cat->wb[i].id, &cat->wb[i]);
  703. if (rc) {
  704. SDE_ERROR("failed: wb hw not available\n");
  705. goto fail;
  706. }
  707. }
  708. for (i = 0; i < cat->ctl_count; i++) {
  709. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CTL,
  710. cat->ctl[i].id, &cat->ctl[i]);
  711. if (rc) {
  712. SDE_ERROR("failed: ctl hw not available\n");
  713. goto fail;
  714. }
  715. }
  716. if (cat->hw_fence_rev) {
  717. if (_init_hw_fences(rm, test_bit(SDE_FEATURE_HW_FENCE_IPCC, cat->features))) {
  718. SDE_INFO("failed to init hw-fences, disabling hw-fences\n");
  719. cat->hw_fence_rev = 0;
  720. }
  721. }
  722. for (i = 0; i < cat->cdm_count; i++) {
  723. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CDM,
  724. cat->cdm[i].id, &cat->cdm[i]);
  725. if (rc) {
  726. SDE_ERROR("failed: cdm hw not available\n");
  727. goto fail;
  728. }
  729. }
  730. for (i = 0; i < cat->dnsc_blur_count; i++) {
  731. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DNSC_BLUR,
  732. cat->dnsc_blur[i].id, &cat->dnsc_blur[i]);
  733. if (rc) {
  734. SDE_ERROR("failed: dnsc_blur hw not available\n");
  735. goto fail;
  736. }
  737. }
  738. for (i = 0; i < cat->qdss_count; i++) {
  739. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_QDSS,
  740. cat->qdss[i].id, &cat->qdss[i]);
  741. if (rc) {
  742. SDE_ERROR("failed: qdss hw not available\n");
  743. goto fail;
  744. }
  745. }
  746. fail:
  747. return rc;
  748. }
  749. #if IS_ENABLED(CONFIG_DEBUG_FS)
  750. static int _sde_rm_status_show(struct seq_file *s, void *data)
  751. {
  752. struct sde_rm *rm;
  753. struct sde_rm_hw_blk *blk;
  754. u32 type, allocated, unallocated;
  755. if (!s || !s->private)
  756. return -EINVAL;
  757. rm = s->private;
  758. for (type = SDE_HW_BLK_LM; type < SDE_HW_BLK_MAX; type++) {
  759. allocated = 0;
  760. unallocated = 0;
  761. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  762. if (!blk->rsvp && !blk->rsvp_nxt)
  763. unallocated++;
  764. else
  765. allocated++;
  766. }
  767. seq_printf(s, "type:%d blk:%s allocated:%d unallocated:%d\n",
  768. type, sde_hw_blk_str[type], allocated, unallocated);
  769. }
  770. return 0;
  771. }
  772. static int _sde_rm_debugfs_status_open(struct inode *inode,
  773. struct file *file)
  774. {
  775. return single_open(file, _sde_rm_status_show, inode->i_private);
  776. }
  777. void sde_rm_debugfs_init(struct sde_rm *sde_rm, struct dentry *parent)
  778. {
  779. static const struct file_operations debugfs_rm_status_fops = {
  780. .open = _sde_rm_debugfs_status_open,
  781. .read = seq_read,
  782. };
  783. debugfs_create_file("rm_status", 0400, parent, sde_rm, &debugfs_rm_status_fops);
  784. }
  785. #else
  786. void sde_rm_debugfs_init(struct sde_rm *rm, struct dentry *parent)
  787. {
  788. }
  789. #endif /* CONFIG_DEBUG_FS */
  790. int sde_rm_init(struct sde_rm *rm,
  791. struct sde_mdss_cfg *cat,
  792. void __iomem *mmio,
  793. struct drm_device *dev)
  794. {
  795. int i, rc = 0;
  796. enum sde_hw_blk_type type;
  797. if (!rm || !cat || !mmio || !dev) {
  798. SDE_ERROR("invalid input params\n");
  799. return -EINVAL;
  800. }
  801. /* Clear, setup lists */
  802. memset(rm, 0, sizeof(*rm));
  803. mutex_init(&rm->rm_lock);
  804. INIT_LIST_HEAD(&rm->rsvps);
  805. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  806. INIT_LIST_HEAD(&rm->hw_blks[type]);
  807. rm->dev = dev;
  808. if (IS_SDE_CTL_REV_100(cat->ctl_rev))
  809. rm->topology_tbl = g_top_table_v1;
  810. else
  811. rm->topology_tbl = g_top_table;
  812. /* Some of the sub-blocks require an mdptop to be created */
  813. rm->hw_mdp = sde_hw_mdptop_init(MDP_TOP, mmio, cat);
  814. if (IS_ERR_OR_NULL(rm->hw_mdp)) {
  815. rc = PTR_ERR(rm->hw_mdp);
  816. rm->hw_mdp = NULL;
  817. SDE_ERROR("failed: mdp hw not available\n");
  818. goto fail;
  819. }
  820. /* Interrogate HW catalog and create tracking items for hw blocks */
  821. for (i = 0; i < cat->mixer_count; i++) {
  822. struct sde_lm_cfg *lm = &cat->mixer[i];
  823. if (lm->pingpong == PINGPONG_MAX) {
  824. SDE_ERROR("mixer %d without pingpong\n", lm->id);
  825. goto fail;
  826. }
  827. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
  828. cat->mixer[i].id, &cat->mixer[i]);
  829. if (rc) {
  830. SDE_ERROR("failed: lm hw not available\n");
  831. goto fail;
  832. }
  833. if (!rm->lm_max_width) {
  834. rm->lm_max_width = lm->sblk->maxwidth;
  835. } else if (rm->lm_max_width != lm->sblk->maxwidth) {
  836. /*
  837. * Don't expect to have hw where lm max widths differ.
  838. * If found, take the min.
  839. */
  840. SDE_ERROR("unsupported: lm maxwidth differs\n");
  841. if (rm->lm_max_width > lm->sblk->maxwidth)
  842. rm->lm_max_width = lm->sblk->maxwidth;
  843. }
  844. }
  845. rc = _sde_rm_hw_blk_create_new(rm, cat, mmio);
  846. if (!rc)
  847. return 0;
  848. fail:
  849. sde_rm_destroy(rm);
  850. return rc;
  851. }
  852. static bool _sde_rm_check_lm(
  853. struct sde_rm *rm,
  854. struct sde_rm_rsvp *rsvp,
  855. struct sde_rm_requirements *reqs,
  856. const struct sde_lm_cfg *lm_cfg,
  857. struct sde_rm_hw_blk *lm,
  858. struct sde_rm_hw_blk **dspp,
  859. struct sde_rm_hw_blk **ds,
  860. struct sde_rm_hw_blk **pp)
  861. {
  862. bool is_valid_dspp, is_valid_ds, ret = true;
  863. is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
  864. is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
  865. /**
  866. * RM_RQ_X: specification of which LMs to choose
  867. * is_valid_X: indicates whether LM is tied with block X
  868. * ret: true if given LM matches the user requirement,
  869. * false otherwise
  870. */
  871. if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
  872. ret = (is_valid_dspp && is_valid_ds);
  873. else if (RM_RQ_DSPP(reqs))
  874. ret = is_valid_dspp;
  875. else if (RM_RQ_DS(reqs))
  876. ret = is_valid_ds;
  877. if (!ret) {
  878. SDE_DEBUG(
  879. "fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
  880. lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
  881. lm_cfg->dspp, (bool)(RM_RQ_DS(reqs)),
  882. lm_cfg->ds);
  883. return ret;
  884. }
  885. return true;
  886. }
  887. static bool _sde_rm_reserve_dspp(
  888. struct sde_rm *rm,
  889. struct sde_rm_rsvp *rsvp,
  890. const struct sde_lm_cfg *lm_cfg,
  891. struct sde_rm_hw_blk *lm,
  892. struct sde_rm_hw_blk **dspp)
  893. {
  894. struct sde_rm_hw_iter iter;
  895. if (lm_cfg->dspp != DSPP_MAX) {
  896. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DSPP);
  897. while (_sde_rm_get_hw_locked(rm, &iter)) {
  898. if (iter.blk->id == lm_cfg->dspp) {
  899. *dspp = iter.blk;
  900. break;
  901. }
  902. }
  903. if (!*dspp) {
  904. SDE_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
  905. lm_cfg->dspp);
  906. return false;
  907. }
  908. if (RESERVED_BY_OTHER(*dspp, rsvp)) {
  909. SDE_DEBUG("lm %d dspp %d already reserved\n",
  910. lm->id, (*dspp)->id);
  911. return false;
  912. }
  913. }
  914. return true;
  915. }
  916. static bool _sde_rm_reserve_ds(
  917. struct sde_rm *rm,
  918. struct sde_rm_rsvp *rsvp,
  919. const struct sde_lm_cfg *lm_cfg,
  920. struct sde_rm_hw_blk *lm,
  921. struct sde_rm_hw_blk **ds)
  922. {
  923. struct sde_rm_hw_iter iter;
  924. if (lm_cfg->ds != DS_MAX) {
  925. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DS);
  926. while (_sde_rm_get_hw_locked(rm, &iter)) {
  927. if (iter.blk->id == lm_cfg->ds) {
  928. *ds = iter.blk;
  929. break;
  930. }
  931. }
  932. if (!*ds) {
  933. SDE_DEBUG("lm %d failed to retrieve ds %d\n", lm->id,
  934. lm_cfg->ds);
  935. return false;
  936. }
  937. if (RESERVED_BY_OTHER(*ds, rsvp)) {
  938. SDE_DEBUG("lm %d ds %d already reserved\n",
  939. lm->id, (*ds)->id);
  940. return false;
  941. }
  942. }
  943. return true;
  944. }
  945. static bool _sde_rm_reserve_pp(
  946. struct sde_rm *rm,
  947. struct sde_rm_rsvp *rsvp,
  948. struct sde_rm_requirements *reqs,
  949. const struct sde_lm_cfg *lm_cfg,
  950. const struct sde_pingpong_cfg *pp_cfg,
  951. struct sde_rm_hw_blk *lm,
  952. struct sde_rm_hw_blk **dspp,
  953. struct sde_rm_hw_blk **ds,
  954. struct sde_rm_hw_blk **pp)
  955. {
  956. struct sde_rm_hw_iter iter;
  957. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_PINGPONG);
  958. while (_sde_rm_get_hw_locked(rm, &iter)) {
  959. if (iter.blk->id == lm_cfg->pingpong) {
  960. *pp = iter.blk;
  961. break;
  962. }
  963. }
  964. if (!*pp) {
  965. SDE_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
  966. return false;
  967. }
  968. if (RESERVED_BY_OTHER(*pp, rsvp)) {
  969. SDE_DEBUG("lm %d pp %d already reserved\n", lm->id,
  970. (*pp)->id);
  971. *dspp = NULL;
  972. *ds = NULL;
  973. return false;
  974. }
  975. pp_cfg = to_sde_hw_pingpong((*pp)->hw)->caps;
  976. if ((reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) &&
  977. !(test_bit(SDE_PINGPONG_SPLIT, &pp_cfg->features))) {
  978. SDE_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
  979. *dspp = NULL;
  980. *ds = NULL;
  981. return false;
  982. }
  983. return true;
  984. }
  985. /**
  986. * _sde_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
  987. * proposed use case requirements, incl. hardwired dependent blocks like
  988. * pingpong, and dspp.
  989. * @rm: sde resource manager handle
  990. * @rsvp: reservation currently being created
  991. * @reqs: proposed use case requirements
  992. * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  993. * blocks connected to the lm (pp, dspp) are available and appropriate
  994. * @dspp: output parameter, dspp block attached to the layer mixer.
  995. * NULL if dspp was not available, or not matching requirements.
  996. * @pp: output parameter, pingpong block attached to the layer mixer.
  997. * NULL if dspp was not available, or not matching requirements.
  998. * @primary_lm: if non-null, this function check if lm is compatible primary_lm
  999. * as well as satisfying all other requirements
  1000. * @Return: true if lm matches all requirements, false otherwise
  1001. */
  1002. static bool _sde_rm_check_lm_and_get_connected_blks(
  1003. struct sde_rm *rm,
  1004. struct sde_rm_rsvp *rsvp,
  1005. struct sde_rm_requirements *reqs,
  1006. struct sde_rm_hw_blk *lm,
  1007. struct sde_rm_hw_blk **dspp,
  1008. struct sde_rm_hw_blk **ds,
  1009. struct sde_rm_hw_blk **pp,
  1010. struct sde_rm_hw_blk *primary_lm,
  1011. u32 conn_lm_mask)
  1012. {
  1013. const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap;
  1014. const struct sde_pingpong_cfg *pp_cfg;
  1015. bool ret, is_conn_primary, is_conn_secondary;
  1016. u32 lm_primary_pref, lm_secondary_pref, cwb_pref, dcwb_pref;
  1017. *dspp = NULL;
  1018. *ds = NULL;
  1019. *pp = NULL;
  1020. lm_primary_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
  1021. lm_secondary_pref = lm_cfg->features & BIT(SDE_DISP_SECONDARY_PREF);
  1022. cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);
  1023. dcwb_pref = lm_cfg->features & BIT(SDE_DISP_DCWB_PREF);
  1024. is_conn_primary = (reqs->hw_res.display_type ==
  1025. SDE_CONNECTOR_PRIMARY) ? true : false;
  1026. is_conn_secondary = (reqs->hw_res.display_type ==
  1027. SDE_CONNECTOR_SECONDARY) ? true : false;
  1028. SDE_DEBUG("check lm %d: dspp %d ds %d pp %d features %ld disp type %d\n",
  1029. lm_cfg->id, lm_cfg->dspp, lm_cfg->ds, lm_cfg->pingpong,
  1030. lm_cfg->features, (int)reqs->hw_res.display_type);
  1031. /* Check if this layer mixer is a peer of the proposed primary LM */
  1032. if (primary_lm) {
  1033. const struct sde_lm_cfg *prim_lm_cfg =
  1034. to_sde_hw_mixer(primary_lm->hw)->cap;
  1035. if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
  1036. SDE_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
  1037. prim_lm_cfg->id);
  1038. return false;
  1039. }
  1040. }
  1041. /* bypass rest of the checks if LM for primary display is found */
  1042. if (!lm_primary_pref && !lm_secondary_pref) {
  1043. /* Check lm for valid requirements */
  1044. ret = _sde_rm_check_lm(rm, rsvp, reqs, lm_cfg, lm,
  1045. dspp, ds, pp);
  1046. if (!ret)
  1047. return ret;
  1048. /**
  1049. * If CWB is enabled and LM is not CWB supported
  1050. * then return false.
  1051. */
  1052. if ((RM_RQ_CWB(reqs) && !cwb_pref) ||
  1053. (RM_RQ_DCWB(reqs) && !dcwb_pref)) {
  1054. SDE_DEBUG("fail: cwb/dcwb supported lm not allocated\n");
  1055. return false;
  1056. } else if (!RM_RQ_DCWB(reqs) && dcwb_pref) {
  1057. SDE_DEBUG("fail: dcwb supported dummy lm incorrectly allocated\n");
  1058. return false;
  1059. } else if (RM_RQ_DCWB(reqs) && dcwb_pref && conn_lm_mask &&
  1060. ((ffs(conn_lm_mask) % 2) == ((lm_cfg->id + 1) % 2))) {
  1061. SDE_DEBUG("fail: dcwb:%d trying to match lm:%d\n",
  1062. lm_cfg->id, ffs(conn_lm_mask));
  1063. return false;
  1064. }
  1065. } else if ((!is_conn_primary && lm_primary_pref) ||
  1066. (!is_conn_secondary && lm_secondary_pref)) {
  1067. SDE_DEBUG(
  1068. "display preference is not met. display_type: %d lm_features: %lx\n",
  1069. (int)reqs->hw_res.display_type, lm_cfg->features);
  1070. return false;
  1071. }
  1072. /* Already reserved? */
  1073. if (RESERVED_BY_OTHER(lm, rsvp)) {
  1074. SDE_DEBUG("lm %d already reserved\n", lm_cfg->id);
  1075. return false;
  1076. }
  1077. /* Reserve dspp */
  1078. ret = _sde_rm_reserve_dspp(rm, rsvp, lm_cfg, lm, dspp);
  1079. if (!ret)
  1080. return ret;
  1081. /* Reserve ds */
  1082. ret = _sde_rm_reserve_ds(rm, rsvp, lm_cfg, lm, ds);
  1083. if (!ret)
  1084. return ret;
  1085. /* Reserve pp */
  1086. ret = _sde_rm_reserve_pp(rm, rsvp, reqs, lm_cfg, pp_cfg, lm,
  1087. dspp, ds, pp);
  1088. if (!ret)
  1089. return ret;
  1090. return true;
  1091. }
  1092. static int _sde_rm_reserve_lms(
  1093. struct sde_rm *rm,
  1094. struct sde_rm_rsvp *rsvp,
  1095. struct sde_rm_requirements *reqs,
  1096. u8 *_lm_ids)
  1097. {
  1098. struct sde_rm_hw_blk *lm[MAX_BLOCKS];
  1099. struct sde_rm_hw_blk *dspp[MAX_BLOCKS];
  1100. struct sde_rm_hw_blk *ds[MAX_BLOCKS];
  1101. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  1102. struct sde_rm_hw_iter iter_i, iter_j;
  1103. u32 lm_mask = 0, conn_lm_mask = 0;
  1104. int lm_count = 0;
  1105. int i, rc = 0;
  1106. if (!reqs->topology->num_lm) {
  1107. SDE_DEBUG("invalid number of lm: %d\n", reqs->topology->num_lm);
  1108. return 0;
  1109. }
  1110. if (RM_RQ_DCWB(reqs))
  1111. conn_lm_mask = reqs->conn_lm_mask;
  1112. /* Find a primary mixer */
  1113. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_LM);
  1114. while (lm_count != reqs->topology->num_lm &&
  1115. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1116. if (lm_mask & (1 << iter_i.blk->id))
  1117. continue;
  1118. lm[lm_count] = iter_i.blk;
  1119. dspp[lm_count] = NULL;
  1120. ds[lm_count] = NULL;
  1121. pp[lm_count] = NULL;
  1122. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  1123. iter_i.blk->id,
  1124. lm_count,
  1125. _lm_ids ? _lm_ids[lm_count] : -1);
  1126. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  1127. continue;
  1128. if (!_sde_rm_check_lm_and_get_connected_blks(
  1129. rm, rsvp, reqs, lm[lm_count],
  1130. &dspp[lm_count], &ds[lm_count],
  1131. &pp[lm_count], NULL, conn_lm_mask))
  1132. continue;
  1133. lm_mask |= (1 << iter_i.blk->id);
  1134. ++lm_count;
  1135. /* Return if peer is not needed */
  1136. if (lm_count == reqs->topology->num_lm)
  1137. break;
  1138. if (RM_RQ_DCWB(reqs))
  1139. conn_lm_mask = conn_lm_mask & ~BIT(ffs(conn_lm_mask) - 1);
  1140. /* Valid primary mixer found, find matching peers */
  1141. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_LM);
  1142. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1143. if (lm_mask & (1 << iter_j.blk->id))
  1144. continue;
  1145. lm[lm_count] = iter_j.blk;
  1146. dspp[lm_count] = NULL;
  1147. ds[lm_count] = NULL;
  1148. pp[lm_count] = NULL;
  1149. if (!_sde_rm_check_lm_and_get_connected_blks(
  1150. rm, rsvp, reqs, iter_j.blk,
  1151. &dspp[lm_count], &ds[lm_count],
  1152. &pp[lm_count], iter_i.blk,
  1153. conn_lm_mask))
  1154. continue;
  1155. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  1156. iter_j.blk->id,
  1157. lm_count,
  1158. _lm_ids ? _lm_ids[lm_count] : -1);
  1159. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  1160. continue;
  1161. lm_mask |= (1 << iter_j.blk->id);
  1162. ++lm_count;
  1163. if (RM_RQ_DCWB(reqs))
  1164. conn_lm_mask = conn_lm_mask & ~BIT(ffs(conn_lm_mask) - 1);
  1165. break;
  1166. }
  1167. /* Rollback primary LM if peer is not found */
  1168. if (!iter_j.hw) {
  1169. lm_mask &= ~(1 << iter_i.blk->id);
  1170. --lm_count;
  1171. }
  1172. }
  1173. if (lm_count != reqs->topology->num_lm) {
  1174. SDE_DEBUG("unable to find appropriate mixers\n");
  1175. return -ENAVAIL;
  1176. }
  1177. for (i = 0; i < lm_count; i++) {
  1178. lm[i]->rsvp_nxt = rsvp;
  1179. pp[i]->rsvp_nxt = rsvp;
  1180. if (dspp[i])
  1181. dspp[i]->rsvp_nxt = rsvp;
  1182. if (ds[i])
  1183. ds[i]->rsvp_nxt = rsvp;
  1184. SDE_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
  1185. dspp[i] ? dspp[i]->id : 0,
  1186. ds[i] ? ds[i]->id : 0);
  1187. }
  1188. if (reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
  1189. /* reserve a free PINGPONG_SLAVE block */
  1190. rc = -ENAVAIL;
  1191. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
  1192. while (_sde_rm_get_hw_locked(rm, &iter_i)) {
  1193. const struct sde_hw_pingpong *pp =
  1194. to_sde_hw_pingpong(iter_i.blk->hw);
  1195. const struct sde_pingpong_cfg *pp_cfg = pp->caps;
  1196. if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
  1197. continue;
  1198. if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
  1199. continue;
  1200. iter_i.blk->rsvp_nxt = rsvp;
  1201. rc = 0;
  1202. break;
  1203. }
  1204. }
  1205. return rc;
  1206. }
  1207. static int _sde_rm_reserve_ctls(
  1208. struct sde_rm *rm,
  1209. struct sde_rm_rsvp *rsvp,
  1210. struct sde_rm_requirements *reqs,
  1211. const struct sde_rm_topology_def *top,
  1212. u8 *_ctl_ids)
  1213. {
  1214. struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
  1215. struct sde_rm_hw_iter iter, curr;
  1216. int i = 0;
  1217. if (!top->num_ctl) {
  1218. SDE_DEBUG("invalid number of ctl: %d\n", top->num_ctl);
  1219. return 0;
  1220. }
  1221. memset(&ctls, 0, sizeof(ctls));
  1222. sde_rm_init_hw_iter(&curr, rsvp->enc_id, SDE_HW_BLK_CTL);
  1223. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  1224. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1225. const struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  1226. unsigned long features = ctl->caps->features;
  1227. bool has_split_display, has_ppsplit, primary_pref;
  1228. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1229. continue;
  1230. has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & features;
  1231. has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & features;
  1232. primary_pref = BIT(SDE_CTL_PRIMARY_PREF) & features;
  1233. SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
  1234. /*
  1235. * bypass rest feature checks on finding CTL preferred
  1236. * for primary displays.
  1237. */
  1238. if (!primary_pref && !_ctl_ids) {
  1239. if (top->needs_split_display != has_split_display)
  1240. continue;
  1241. if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT &&
  1242. !has_ppsplit)
  1243. continue;
  1244. } else if (!(reqs->hw_res.display_type ==
  1245. SDE_CONNECTOR_PRIMARY && primary_pref) && !_ctl_ids) {
  1246. SDE_DEBUG(
  1247. "display pref not met. display_type: %d primary_pref: %d\n",
  1248. reqs->hw_res.display_type, primary_pref);
  1249. continue;
  1250. }
  1251. if (_sde_rm_get_hw_locked(rm, &curr) && (curr.blk->id != iter.blk->id)) {
  1252. SDE_EVT32(curr.blk->id, iter.blk->id, SDE_EVTLOG_FUNC_CASE1);
  1253. SDE_DEBUG("ctl in use:%d avoiding new:%d\n", curr.blk->id, iter.blk->id);
  1254. continue;
  1255. }
  1256. ctls[i] = iter.blk;
  1257. SDE_DEBUG("blk id = %d, _ctl_ids[%d] = %d\n",
  1258. iter.blk->id, i,
  1259. _ctl_ids ? _ctl_ids[i] : -1);
  1260. if (_ctl_ids && (ctls[i]->id != _ctl_ids[i]))
  1261. continue;
  1262. SDE_DEBUG("ctl %d match\n", iter.blk->id);
  1263. if (++i == top->num_ctl)
  1264. break;
  1265. }
  1266. if (i != top->num_ctl)
  1267. return -ENAVAIL;
  1268. for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
  1269. ctls[i]->rsvp_nxt = rsvp;
  1270. SDE_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
  1271. }
  1272. return 0;
  1273. }
  1274. static bool _sde_rm_check_dsc(struct sde_rm *rm,
  1275. struct sde_rm_rsvp *rsvp,
  1276. struct sde_rm_hw_blk *dsc,
  1277. struct sde_rm_hw_blk *paired_dsc,
  1278. struct sde_rm_hw_blk *pp_blk)
  1279. {
  1280. const struct sde_dsc_cfg *dsc_cfg = to_sde_hw_dsc(dsc->hw)->caps;
  1281. /* Already reserved? */
  1282. if (RESERVED_BY_OTHER(dsc, rsvp)) {
  1283. SDE_DEBUG("dsc %d already reserved\n", dsc_cfg->id);
  1284. return false;
  1285. }
  1286. /**
  1287. * This check is required for routing even numbered DSC
  1288. * blks to any of the even numbered PP blks and odd numbered
  1289. * DSC blks to any of the odd numbered PP blks.
  1290. */
  1291. if (!pp_blk || !IS_COMPATIBLE_PP_DSC(pp_blk->id, dsc->id))
  1292. return false;
  1293. /* Check if this dsc is a peer of the proposed paired DSC */
  1294. if (paired_dsc) {
  1295. const struct sde_dsc_cfg *paired_dsc_cfg =
  1296. to_sde_hw_dsc(paired_dsc->hw)->caps;
  1297. if (!test_bit(dsc_cfg->id, paired_dsc_cfg->dsc_pair_mask)) {
  1298. SDE_DEBUG("dsc %d not peer of dsc %d\n", dsc_cfg->id,
  1299. paired_dsc_cfg->id);
  1300. return false;
  1301. }
  1302. }
  1303. return true;
  1304. }
  1305. static bool _sde_rm_check_vdc(struct sde_rm *rm,
  1306. struct sde_rm_rsvp *rsvp,
  1307. struct sde_rm_hw_blk *vdc)
  1308. {
  1309. const struct sde_vdc_cfg *vdc_cfg = to_sde_hw_vdc(vdc->hw)->caps;
  1310. /* Already reserved? */
  1311. if (RESERVED_BY_OTHER(vdc, rsvp)) {
  1312. SDE_DEBUG("vdc %d already reserved\n", vdc_cfg->id);
  1313. return false;
  1314. }
  1315. return true;
  1316. }
  1317. static void sde_rm_get_rsvp_nxt_hw_blks(
  1318. struct sde_rm *rm,
  1319. struct sde_rm_rsvp *rsvp,
  1320. int type,
  1321. struct sde_rm_hw_blk **blk_arr)
  1322. {
  1323. struct sde_rm_hw_blk *blk;
  1324. int i = 0;
  1325. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1326. if (blk->rsvp_nxt && blk->rsvp_nxt->seq ==
  1327. rsvp->seq)
  1328. blk_arr[i++] = blk;
  1329. }
  1330. }
  1331. static int _sde_rm_reserve_dsc(
  1332. struct sde_rm *rm,
  1333. struct sde_rm_rsvp *rsvp,
  1334. struct sde_rm_requirements *reqs,
  1335. u8 *_dsc_ids)
  1336. {
  1337. struct sde_rm_hw_iter iter_i, iter_j;
  1338. struct sde_rm_hw_blk *dsc[MAX_BLOCKS];
  1339. u32 reserve_mask = 0;
  1340. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  1341. int alloc_count = 0;
  1342. int num_dsc_enc;
  1343. struct msm_display_dsc_info *dsc_info;
  1344. int i;
  1345. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_DSC) {
  1346. SDE_DEBUG("compression blk dsc not required\n");
  1347. return 0;
  1348. }
  1349. num_dsc_enc = reqs->topology->num_comp_enc;
  1350. dsc_info = &reqs->hw_res.comp_info->dsc_info;
  1351. if ((!num_dsc_enc) || !dsc_info) {
  1352. SDE_DEBUG("invalid topoplogy params: %d, %d\n",
  1353. num_dsc_enc, !(dsc_info == NULL));
  1354. return 0;
  1355. }
  1356. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_DSC);
  1357. sde_rm_get_rsvp_nxt_hw_blks(rm, rsvp, SDE_HW_BLK_PINGPONG, pp);
  1358. /* Find a first DSC */
  1359. while (alloc_count != num_dsc_enc &&
  1360. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1361. const struct sde_hw_dsc *hw_dsc = to_sde_hw_dsc(
  1362. iter_i.blk->hw);
  1363. unsigned long features = hw_dsc->caps->features;
  1364. bool has_422_420_support =
  1365. BIT(SDE_DSC_NATIVE_422_EN) & features;
  1366. if (reserve_mask & (1 << iter_i.blk->id))
  1367. continue;
  1368. if (_dsc_ids && (iter_i.blk->id != _dsc_ids[alloc_count]))
  1369. continue;
  1370. /* if this hw block does not support required feature */
  1371. if (!_dsc_ids && (dsc_info->config.native_422 ||
  1372. dsc_info->config.native_420) && !has_422_420_support)
  1373. continue;
  1374. if (!_sde_rm_check_dsc(rm, rsvp, iter_i.blk, NULL,
  1375. pp[alloc_count]))
  1376. continue;
  1377. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1378. iter_i.blk->id,
  1379. alloc_count,
  1380. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1381. reserve_mask |= (1 << iter_i.blk->id);
  1382. dsc[alloc_count++] = iter_i.blk;
  1383. /* Return if peer is not needed */
  1384. if (alloc_count == num_dsc_enc)
  1385. break;
  1386. /* Valid first dsc found, find matching peers */
  1387. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_DSC);
  1388. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1389. if (reserve_mask & (1 << iter_j.blk->id))
  1390. continue;
  1391. if (_dsc_ids && (iter_j.blk->id !=
  1392. _dsc_ids[alloc_count]))
  1393. continue;
  1394. if (!_sde_rm_check_dsc(rm, rsvp, iter_j.blk,
  1395. iter_i.blk, pp[alloc_count]))
  1396. continue;
  1397. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1398. iter_j.blk->id,
  1399. alloc_count,
  1400. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1401. reserve_mask |= (1 << iter_j.blk->id);
  1402. dsc[alloc_count++] = iter_j.blk;
  1403. break;
  1404. }
  1405. /* Rollback primary DSC if peer is not found */
  1406. if (!iter_j.hw) {
  1407. reserve_mask &= ~(1 << iter_i.blk->id);
  1408. --alloc_count;
  1409. }
  1410. }
  1411. if (alloc_count != num_dsc_enc) {
  1412. SDE_ERROR("couldn't reserve %d dsc blocks for enc id %d\n",
  1413. num_dsc_enc, rsvp->enc_id);
  1414. return -EINVAL;
  1415. }
  1416. for (i = 0; i < alloc_count; i++) {
  1417. if (!dsc[i])
  1418. break;
  1419. dsc[i]->rsvp_nxt = rsvp;
  1420. SDE_EVT32(dsc[i]->type, rsvp->enc_id, dsc[i]->id);
  1421. }
  1422. return 0;
  1423. }
  1424. static int _sde_rm_reserve_vdc(
  1425. struct sde_rm *rm,
  1426. struct sde_rm_rsvp *rsvp,
  1427. struct sde_rm_requirements *reqs,
  1428. const struct sde_rm_topology_def *top,
  1429. u8 *_vdc_ids)
  1430. {
  1431. struct sde_rm_hw_iter iter_i;
  1432. struct sde_rm_hw_blk *vdc[MAX_BLOCKS];
  1433. int alloc_count = 0;
  1434. int num_vdc_enc = top->num_comp_enc;
  1435. int i;
  1436. if (!top->num_comp_enc)
  1437. return 0;
  1438. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_VDC)
  1439. return 0;
  1440. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_VDC);
  1441. /* Find a VDC */
  1442. while (alloc_count != num_vdc_enc &&
  1443. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1444. memset(&vdc, 0, sizeof(vdc));
  1445. alloc_count = 0;
  1446. if (_vdc_ids && (iter_i.blk->id != _vdc_ids[alloc_count]))
  1447. continue;
  1448. if (!_sde_rm_check_vdc(rm, rsvp, iter_i.blk))
  1449. continue;
  1450. SDE_DEBUG("blk id = %d, _vdc_ids[%d] = %d\n",
  1451. iter_i.blk->id,
  1452. alloc_count,
  1453. _vdc_ids ? _vdc_ids[alloc_count] : -1);
  1454. vdc[alloc_count++] = iter_i.blk;
  1455. }
  1456. if (alloc_count != num_vdc_enc) {
  1457. SDE_ERROR("couldn't reserve %d vdc blocks for enc id %d\n",
  1458. num_vdc_enc, rsvp->enc_id);
  1459. return -EINVAL;
  1460. }
  1461. for (i = 0; i < ARRAY_SIZE(vdc); i++) {
  1462. if (!vdc[i])
  1463. break;
  1464. vdc[i]->rsvp_nxt = rsvp;
  1465. SDE_EVT32(vdc[i]->type, rsvp->enc_id, vdc[i]->id);
  1466. }
  1467. return 0;
  1468. }
  1469. static int _sde_rm_reserve_qdss(
  1470. struct sde_rm *rm,
  1471. struct sde_rm_rsvp *rsvp,
  1472. const struct sde_rm_topology_def *top,
  1473. u8 *_qdss_ids)
  1474. {
  1475. struct sde_rm_hw_iter iter;
  1476. struct msm_drm_private *priv = rm->dev->dev_private;
  1477. struct sde_kms *sde_kms;
  1478. if (!priv->kms) {
  1479. SDE_ERROR("invalid kms\n");
  1480. return -EINVAL;
  1481. }
  1482. sde_kms = to_sde_kms(priv->kms);
  1483. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_QDSS);
  1484. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1485. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1486. continue;
  1487. SDE_DEBUG("blk id = %d\n", iter.blk->id);
  1488. iter.blk->rsvp_nxt = rsvp;
  1489. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1490. return 0;
  1491. }
  1492. if (!iter.hw && sde_kms->catalog->qdss_count) {
  1493. SDE_DEBUG("couldn't reserve qdss for type %d id %d\n",
  1494. SDE_HW_BLK_QDSS, iter.blk->id);
  1495. return -ENAVAIL;
  1496. }
  1497. return 0;
  1498. }
  1499. static int _sde_rm_reserve_dnsc_blur(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1500. uint32_t id, enum sde_hw_blk_type type)
  1501. {
  1502. struct sde_rm_hw_iter iter;
  1503. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DNSC_BLUR);
  1504. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1505. struct sde_hw_dnsc_blur *dnsc_blur = to_sde_hw_dnsc_blur(iter.blk->hw);
  1506. bool match = false;
  1507. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1508. continue;
  1509. if ((type == SDE_HW_BLK_WB) && (id != WB_MAX))
  1510. match = test_bit(id, &dnsc_blur->caps->wb_connect);
  1511. SDE_DEBUG("type %d id %d, dnsc_blur wbs %lu match %d\n",
  1512. type, id, dnsc_blur->caps->wb_connect, match);
  1513. if (!match)
  1514. continue;
  1515. iter.blk->rsvp_nxt = rsvp;
  1516. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1517. break;
  1518. }
  1519. if (!iter.hw) {
  1520. SDE_ERROR("couldn't reserve dnsc_blur for type %d id %d\n", type, id);
  1521. return -ENAVAIL;
  1522. }
  1523. return 0;
  1524. }
  1525. static int _sde_rm_reserve_cdm(
  1526. struct sde_rm *rm,
  1527. struct sde_rm_rsvp *rsvp,
  1528. uint32_t id,
  1529. enum sde_hw_blk_type type)
  1530. {
  1531. struct sde_rm_hw_iter iter;
  1532. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CDM);
  1533. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1534. const struct sde_hw_cdm *cdm = to_sde_hw_cdm(iter.blk->hw);
  1535. const struct sde_cdm_cfg *caps = cdm->caps;
  1536. bool match = false;
  1537. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1538. continue;
  1539. if (type == SDE_HW_BLK_INTF && id != INTF_MAX)
  1540. match = test_bit(id, &caps->intf_connect);
  1541. else if (type == SDE_HW_BLK_WB && id != WB_MAX)
  1542. match = test_bit(id, &caps->wb_connect);
  1543. SDE_DEBUG("type %d id %d, cdm intfs %lu wbs %lu match %d\n",
  1544. type, id, caps->intf_connect, caps->wb_connect,
  1545. match);
  1546. if (!match)
  1547. continue;
  1548. iter.blk->rsvp_nxt = rsvp;
  1549. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1550. break;
  1551. }
  1552. if (!iter.hw) {
  1553. SDE_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
  1554. return -ENAVAIL;
  1555. }
  1556. return 0;
  1557. }
  1558. static int _sde_rm_reserve_intf_or_wb(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1559. uint32_t id, enum sde_hw_blk_type type, struct sde_rm_requirements *reqs)
  1560. {
  1561. struct sde_encoder_hw_resources *hw_res = &reqs->hw_res;
  1562. struct sde_rm_hw_iter iter;
  1563. int ret = 0;
  1564. /* Find the block entry in the rm, and note the reservation */
  1565. sde_rm_init_hw_iter(&iter, 0, type);
  1566. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1567. if (iter.blk->id != id)
  1568. continue;
  1569. if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
  1570. SDE_ERROR("type %d id %d already reserved\n", type, id);
  1571. return -ENAVAIL;
  1572. }
  1573. iter.blk->rsvp_nxt = rsvp;
  1574. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1575. break;
  1576. }
  1577. /* Shouldn't happen since wbs / intfs are fixed at probe */
  1578. if (!iter.hw) {
  1579. SDE_ERROR("couldn't find type %d id %d\n", type, id);
  1580. return -EINVAL;
  1581. }
  1582. /* Expected only one intf or wb will request cdm */
  1583. if (hw_res->needs_cdm)
  1584. ret = _sde_rm_reserve_cdm(rm, rsvp, id, type);
  1585. if (RM_RQ_DNSC_BLUR(reqs))
  1586. ret = _sde_rm_reserve_dnsc_blur(rm, rsvp, id, type);
  1587. return ret;
  1588. }
  1589. static int _sde_rm_reserve_intf_related_hw(struct sde_rm *rm,
  1590. struct sde_rm_rsvp *rsvp, struct sde_rm_requirements *reqs)
  1591. {
  1592. struct sde_encoder_hw_resources *hw_res = &reqs->hw_res;
  1593. int i, ret = 0;
  1594. u32 id;
  1595. for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
  1596. if (hw_res->intfs[i] == INTF_MODE_NONE)
  1597. continue;
  1598. id = i + INTF_0;
  1599. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id, SDE_HW_BLK_INTF, reqs);
  1600. if (ret)
  1601. return ret;
  1602. }
  1603. for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
  1604. if (hw_res->wbs[i] == INTF_MODE_NONE)
  1605. continue;
  1606. id = i + WB_0;
  1607. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id, SDE_HW_BLK_WB, reqs);
  1608. if (ret)
  1609. return ret;
  1610. }
  1611. return ret;
  1612. }
  1613. static bool _sde_rm_is_display_in_cont_splash(struct sde_kms *sde_kms,
  1614. struct drm_encoder *enc)
  1615. {
  1616. int i;
  1617. struct sde_splash_display *splash_dpy;
  1618. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1619. splash_dpy = &sde_kms->splash_data.splash_display[i];
  1620. if (splash_dpy->encoder == enc)
  1621. return splash_dpy->cont_splash_enabled;
  1622. }
  1623. return false;
  1624. }
  1625. static int _sde_rm_make_lm_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1626. struct sde_rm_requirements *reqs,
  1627. struct sde_splash_display *splash_display)
  1628. {
  1629. int ret, i;
  1630. u8 *hw_ids = NULL;
  1631. /* Check if splash data provided lm_ids */
  1632. if (splash_display) {
  1633. hw_ids = splash_display->lm_ids;
  1634. for (i = 0; i < splash_display->lm_cnt; i++)
  1635. SDE_DEBUG("splash_display->lm_ids[%d] = %d\n",
  1636. i, splash_display->lm_ids[i]);
  1637. if (splash_display->lm_cnt != reqs->topology->num_lm)
  1638. SDE_DEBUG("Configured splash LMs != needed LM cnt\n");
  1639. }
  1640. /*
  1641. * Assign LMs and blocks whose usage is tied to them:
  1642. * DSPP & Pingpong.
  1643. */
  1644. ret = _sde_rm_reserve_lms(rm, rsvp, reqs, hw_ids);
  1645. return ret;
  1646. }
  1647. static int _sde_rm_make_ctl_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1648. struct sde_rm_requirements *reqs,
  1649. struct sde_splash_display *splash_display)
  1650. {
  1651. int ret, i;
  1652. u8 *hw_ids = NULL;
  1653. struct sde_rm_topology_def topology;
  1654. /* Check if splash data provided ctl_ids */
  1655. if (splash_display) {
  1656. hw_ids = splash_display->ctl_ids;
  1657. for (i = 0; i < splash_display->ctl_cnt; i++)
  1658. SDE_DEBUG("splash_display->ctl_ids[%d] = %d\n",
  1659. i, splash_display->ctl_ids[i]);
  1660. }
  1661. /*
  1662. * Do assignment preferring to give away low-resource CTLs first:
  1663. * - Check mixers without Split Display
  1664. * - Only then allow to grab from CTLs with split display capability
  1665. */
  1666. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, reqs->topology, hw_ids);
  1667. if (ret && !reqs->topology->needs_split_display &&
  1668. reqs->topology->num_ctl > SINGLE_CTL) {
  1669. memcpy(&topology, reqs->topology, sizeof(topology));
  1670. topology.needs_split_display = true;
  1671. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, &topology, hw_ids);
  1672. }
  1673. return ret;
  1674. }
  1675. /*
  1676. * Returns number of dsc hw blocks previously owned by this encoder.
  1677. * Returns 0 if not found or error
  1678. */
  1679. static int _sde_rm_find_prev_dsc(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1680. u8 *prev_dsc, u32 max_cnt)
  1681. {
  1682. int i = 0;
  1683. struct sde_rm_hw_iter iter_dsc;
  1684. if ((!prev_dsc) || (max_cnt < MAX_DATA_PATH_PER_DSIPLAY))
  1685. return 0;
  1686. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1687. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1688. if (RESERVED_BY_CURRENT(iter_dsc.blk, rsvp))
  1689. prev_dsc[i++] = iter_dsc.blk->id;
  1690. if (i >= MAX_DATA_PATH_PER_DSIPLAY)
  1691. return 0;
  1692. }
  1693. return i;
  1694. }
  1695. static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1696. struct sde_rm_requirements *reqs,
  1697. struct sde_splash_display *splash_display)
  1698. {
  1699. int i;
  1700. u8 *hw_ids = NULL;
  1701. u8 prev_dsc[MAX_DATA_PATH_PER_DSIPLAY] = {0,};
  1702. /* Check if splash data provided dsc_ids */
  1703. if (splash_display) {
  1704. hw_ids = splash_display->dsc_ids;
  1705. if (splash_display->dsc_cnt)
  1706. reqs->hw_res.comp_info->comp_type =
  1707. MSM_DISPLAY_COMPRESSION_DSC;
  1708. for (i = 0; i < splash_display->dsc_cnt; i++)
  1709. SDE_DEBUG("splash_data.dsc_ids[%d] = %d\n",
  1710. i, splash_display->dsc_ids[i]);
  1711. }
  1712. /*
  1713. * find if this encoder has previously allocated dsc hw blocks, use same dsc blocks
  1714. * if found to avoid switching dsc encoders during each modeset, as currently we
  1715. * dont have feasible way of decoupling previously owned dsc blocks by resetting
  1716. * respective dsc encoders mux control and flush them from commit path
  1717. */
  1718. if (!hw_ids && _sde_rm_find_prev_dsc(rm, rsvp, prev_dsc, MAX_DATA_PATH_PER_DSIPLAY))
  1719. return _sde_rm_reserve_dsc(rm, rsvp, reqs, prev_dsc);
  1720. else
  1721. return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
  1722. }
  1723. static int _sde_rm_make_vdc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1724. struct sde_rm_requirements *reqs,
  1725. struct sde_splash_display *splash_display)
  1726. {
  1727. int ret, i;
  1728. u8 *hw_ids = NULL;
  1729. /* Check if splash data provided vdc_ids */
  1730. if (splash_display) {
  1731. hw_ids = splash_display->vdc_ids;
  1732. for (i = 0; i < splash_display->vdc_cnt; i++)
  1733. SDE_DEBUG("splash_data.vdc_ids[%d] = %d\n",
  1734. i, splash_display->vdc_ids[i]);
  1735. }
  1736. ret = _sde_rm_reserve_vdc(rm, rsvp, reqs, reqs->topology, hw_ids);
  1737. return ret;
  1738. }
  1739. static int _sde_rm_make_next_rsvp(struct sde_rm *rm, struct drm_encoder *enc,
  1740. struct drm_crtc_state *crtc_state,
  1741. struct drm_connector_state *conn_state,
  1742. struct sde_rm_rsvp *rsvp,
  1743. struct sde_rm_requirements *reqs)
  1744. {
  1745. struct msm_drm_private *priv;
  1746. struct sde_kms *sde_kms;
  1747. struct sde_splash_display *splash_display = NULL;
  1748. struct sde_splash_data *splash_data;
  1749. int i, ret;
  1750. priv = enc->dev->dev_private;
  1751. sde_kms = to_sde_kms(priv->kms);
  1752. splash_data = &sde_kms->splash_data;
  1753. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1754. for (i = 0; i < ARRAY_SIZE(splash_data->splash_display); i++) {
  1755. if (enc == splash_data->splash_display[i].encoder)
  1756. splash_display =
  1757. &splash_data->splash_display[i];
  1758. }
  1759. if (!splash_display) {
  1760. SDE_ERROR("rm is in cont_splash but data not found\n");
  1761. return -EINVAL;
  1762. }
  1763. }
  1764. /* Create reservation info, tag reserved blocks with it as we go */
  1765. rsvp->seq = ++rm->rsvp_next_seq;
  1766. rsvp->enc_id = enc->base.id;
  1767. rsvp->topology = reqs->topology->top_name;
  1768. rsvp->pending = true;
  1769. list_add_tail(&rsvp->list, &rm->rsvps);
  1770. ret = _sde_rm_make_lm_rsvp(rm, rsvp, reqs, splash_display);
  1771. if (ret) {
  1772. SDE_ERROR("unable to find appropriate mixers\n");
  1773. _sde_rm_print_rsvps_by_type(rm, SDE_HW_BLK_LM);
  1774. return ret;
  1775. }
  1776. ret = _sde_rm_make_ctl_rsvp(rm, rsvp, reqs, splash_display);
  1777. if (ret) {
  1778. SDE_ERROR("unable to find appropriate CTL\n");
  1779. return ret;
  1780. }
  1781. /* Assign INTFs, WBs, and blks whose usage is tied to them: CTL & CDM */
  1782. ret = _sde_rm_reserve_intf_related_hw(rm, rsvp, reqs);
  1783. if (ret)
  1784. return ret;
  1785. ret = _sde_rm_make_dsc_rsvp(rm, rsvp, reqs, splash_display);
  1786. if (ret)
  1787. return ret;
  1788. ret = _sde_rm_make_vdc_rsvp(rm, rsvp, reqs, splash_display);
  1789. if (ret)
  1790. return ret;
  1791. ret = _sde_rm_reserve_qdss(rm, rsvp, reqs->topology, NULL);
  1792. if (ret)
  1793. return ret;
  1794. return ret;
  1795. }
  1796. static int _sde_rm_update_active_only_pipes(
  1797. struct sde_splash_display *splash_display,
  1798. u32 active_pipes_mask)
  1799. {
  1800. struct sde_sspp_index_info *pipe_info;
  1801. int i;
  1802. if (!active_pipes_mask) {
  1803. return 0;
  1804. } else if (!splash_display) {
  1805. SDE_ERROR("invalid splash display provided\n");
  1806. return -EINVAL;
  1807. }
  1808. pipe_info = &splash_display->pipe_info;
  1809. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  1810. if (!(active_pipes_mask & BIT(i)))
  1811. continue;
  1812. if (test_bit(i, pipe_info->pipes) || test_bit(i, pipe_info->virt_pipes))
  1813. continue;
  1814. /*
  1815. * A pipe is active but not staged indicates a non-pixel
  1816. * plane. Register both rectangles as we can't differentiate
  1817. */
  1818. set_bit(i, pipe_info->pipes);
  1819. set_bit(i, pipe_info->virt_pipes);
  1820. SDE_DEBUG("pipe %d is active:0x%x but not staged\n", i, active_pipes_mask);
  1821. }
  1822. return 0;
  1823. }
  1824. /**
  1825. * _sde_rm_get_hw_blk_for_cont_splash - retrieve the LM blocks on given CTL
  1826. * and populate the connected HW blk ids in sde_splash_display
  1827. * @rm: Pointer to resource manager structure
  1828. * @ctl: Pointer to CTL hardware block
  1829. * @splash_display: Pointer to struct sde_splash_display
  1830. * return: number of active LM blocks for this CTL block
  1831. */
  1832. static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
  1833. struct sde_hw_ctl *ctl,
  1834. struct sde_splash_display *splash_display)
  1835. {
  1836. u32 active_pipes_mask = 0;
  1837. struct sde_rm_hw_iter iter_lm, iter_dsc;
  1838. struct sde_kms *sde_kms;
  1839. size_t pipes_per_lm;
  1840. if (!rm || !ctl || !splash_display) {
  1841. SDE_ERROR("invalid input parameters\n");
  1842. return 0;
  1843. }
  1844. sde_kms = container_of(rm, struct sde_kms, rm);
  1845. sde_rm_init_hw_iter(&iter_lm, 0, SDE_HW_BLK_LM);
  1846. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1847. while (_sde_rm_get_hw_locked(rm, &iter_lm)) {
  1848. if (splash_display->lm_cnt >= MAX_DATA_PATH_PER_DSIPLAY)
  1849. break;
  1850. if (ctl->ops.get_staged_sspp) {
  1851. // reset bordercolor from previous LM
  1852. splash_display->pipe_info.bordercolor = false;
  1853. pipes_per_lm = ctl->ops.get_staged_sspp(
  1854. ctl, iter_lm.blk->id,
  1855. &splash_display->pipe_info);
  1856. if (pipes_per_lm ||
  1857. splash_display->pipe_info.bordercolor) {
  1858. splash_display->lm_ids[splash_display->lm_cnt++] =
  1859. iter_lm.blk->id;
  1860. SDE_DEBUG("lm_cnt=%d lm_id %d pipe_cnt%d\n",
  1861. splash_display->lm_cnt,
  1862. iter_lm.blk->id - LM_0,
  1863. pipes_per_lm);
  1864. }
  1865. }
  1866. }
  1867. if (ctl->ops.get_active_pipes)
  1868. active_pipes_mask = ctl->ops.get_active_pipes(ctl);
  1869. if (_sde_rm_update_active_only_pipes(splash_display, active_pipes_mask))
  1870. return 0;
  1871. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1872. if (ctl->ops.read_active_status &&
  1873. !(ctl->ops.read_active_status(ctl,
  1874. SDE_HW_BLK_DSC,
  1875. iter_dsc.blk->id)))
  1876. continue;
  1877. splash_display->dsc_ids[splash_display->dsc_cnt++] =
  1878. iter_dsc.blk->id;
  1879. SDE_DEBUG("CTL[%d] path, using dsc[%d]\n",
  1880. ctl->idx,
  1881. iter_dsc.blk->id - DSC_0);
  1882. }
  1883. return splash_display->lm_cnt;
  1884. }
  1885. int sde_rm_cont_splash_res_init(struct msm_drm_private *priv,
  1886. struct sde_rm *rm,
  1887. struct sde_splash_data *splash_data,
  1888. struct sde_mdss_cfg *cat)
  1889. {
  1890. struct sde_rm_hw_iter iter_c;
  1891. int index = 0, ctl_top_cnt;
  1892. struct sde_kms *sde_kms = NULL;
  1893. struct sde_hw_mdp *hw_mdp;
  1894. struct sde_splash_display *splash_display;
  1895. u8 intf_sel;
  1896. if (!priv || !rm || !cat || !splash_data) {
  1897. SDE_ERROR("invalid input parameters\n");
  1898. return -EINVAL;
  1899. }
  1900. SDE_DEBUG("mixer_count=%d, ctl_count=%d, dsc_count=%d\n",
  1901. cat->mixer_count,
  1902. cat->ctl_count,
  1903. cat->dsc_count);
  1904. ctl_top_cnt = cat->ctl_count;
  1905. if (!priv->kms) {
  1906. SDE_ERROR("invalid kms\n");
  1907. return -EINVAL;
  1908. }
  1909. sde_kms = to_sde_kms(priv->kms);
  1910. hw_mdp = sde_rm_get_mdp(rm);
  1911. sde_rm_init_hw_iter(&iter_c, 0, SDE_HW_BLK_CTL);
  1912. while (_sde_rm_get_hw_locked(rm, &iter_c)
  1913. && (index < splash_data->num_splash_displays)) {
  1914. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter_c.blk->hw);
  1915. if (!ctl->ops.get_ctl_intf) {
  1916. SDE_ERROR("get_ctl_intf not initialized\n");
  1917. return -EINVAL;
  1918. }
  1919. intf_sel = ctl->ops.get_ctl_intf(ctl);
  1920. if (intf_sel) {
  1921. splash_display = &splash_data->splash_display[index];
  1922. SDE_DEBUG("finding resources for display=%d ctl=%d\n",
  1923. index, iter_c.blk->id - CTL_0);
  1924. _sde_rm_get_hw_blk_for_cont_splash(rm,
  1925. ctl, splash_display);
  1926. splash_display->cont_splash_enabled = true;
  1927. splash_display->ctl_ids[splash_display->ctl_cnt++] =
  1928. iter_c.blk->id;
  1929. }
  1930. index++;
  1931. }
  1932. return 0;
  1933. }
  1934. static struct drm_connector *_sde_rm_get_connector(
  1935. struct drm_encoder *enc)
  1936. {
  1937. struct drm_connector *conn = NULL, *conn_search;
  1938. struct sde_connector *c_conn = NULL;
  1939. struct drm_connector_list_iter conn_iter;
  1940. drm_connector_list_iter_begin(enc->dev, &conn_iter);
  1941. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1942. c_conn = to_sde_connector(conn_search);
  1943. if (c_conn->encoder == enc) {
  1944. conn = conn_search;
  1945. break;
  1946. }
  1947. }
  1948. drm_connector_list_iter_end(&conn_iter);
  1949. return conn;
  1950. }
  1951. static int _sde_rm_populate_requirements(
  1952. struct sde_rm *rm,
  1953. struct drm_encoder *enc,
  1954. struct drm_crtc_state *crtc_state,
  1955. struct drm_connector_state *conn_state,
  1956. struct sde_mdss_cfg *cfg,
  1957. struct sde_rm_requirements *reqs)
  1958. {
  1959. const struct drm_display_mode *mode = &crtc_state->mode;
  1960. struct drm_encoder *encoder_iter;
  1961. struct drm_connector *conn;
  1962. int i, num_lm;
  1963. reqs->top_ctrl = sde_connector_get_property(conn_state,
  1964. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1965. sde_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
  1966. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++) {
  1967. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  1968. reqs->hw_res.topology)) {
  1969. reqs->topology = &rm->topology_tbl[i];
  1970. break;
  1971. }
  1972. }
  1973. if (!reqs->topology) {
  1974. SDE_ERROR("invalid topology for the display\n");
  1975. return -EINVAL;
  1976. }
  1977. /*
  1978. * select dspp HW block for all dsi displays and ds for only
  1979. * primary dsi display.
  1980. */
  1981. if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) {
  1982. if (!RM_RQ_DSPP(reqs))
  1983. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
  1984. if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler &&
  1985. sde_encoder_is_primary_display(enc))
  1986. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DS);
  1987. }
  1988. /**
  1989. * Set the requirement for LM which has CWB support if CWB is
  1990. * found enabled.
  1991. */
  1992. if ((!RM_RQ_CWB(reqs) || !RM_RQ_DCWB(reqs))
  1993. && sde_crtc_state_in_clone_mode(enc, crtc_state)) {
  1994. if (test_bit(SDE_FEATURE_DEDICATED_CWB, cfg->features))
  1995. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DCWB);
  1996. else
  1997. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
  1998. /*
  1999. * topology selection based on conn mode is not valid for CWB
  2000. * as WB conn populates modes based on max_mixer_width check
  2001. * but primary can be using dual LMs. This topology override for
  2002. * CWB is to check number of datapath active in primary and
  2003. * allocate same number of LM/PP blocks reserved for CWB
  2004. */
  2005. reqs->topology =
  2006. &rm->topology_tbl[SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE];
  2007. num_lm = sde_crtc_get_num_datapath(crtc_state->crtc,
  2008. conn_state->connector, crtc_state);
  2009. if (num_lm == 1)
  2010. reqs->topology =
  2011. &rm->topology_tbl[SDE_RM_TOPOLOGY_SINGLEPIPE];
  2012. else if (num_lm == 0)
  2013. SDE_ERROR("Primary layer mixer is not set\n");
  2014. SDE_EVT32(num_lm, reqs->topology->num_lm,
  2015. reqs->topology->top_name, reqs->topology->num_ctl);
  2016. }
  2017. if (RM_RQ_DCWB(reqs)) {
  2018. drm_for_each_encoder_mask(encoder_iter, enc->dev,
  2019. crtc_state->encoder_mask) {
  2020. if (drm_encoder_mask(encoder_iter) == drm_encoder_mask(enc))
  2021. continue;
  2022. conn = _sde_rm_get_connector(encoder_iter);
  2023. if (conn)
  2024. reqs->conn_lm_mask = to_sde_connector(conn)->lm_mask;
  2025. break;
  2026. }
  2027. }
  2028. SDE_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
  2029. reqs->hw_res.display_num_of_h_tiles);
  2030. SDE_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d mask: 0x%llX\n",
  2031. reqs->topology->num_lm, reqs->topology->num_ctl,
  2032. reqs->topology->top_name,
  2033. reqs->topology->needs_split_display, reqs->conn_lm_mask);
  2034. SDE_EVT32(mode->hdisplay, rm->lm_max_width, reqs->topology->num_lm,
  2035. reqs->top_ctrl, reqs->topology->top_name,
  2036. reqs->topology->num_ctl, reqs->conn_lm_mask);
  2037. return 0;
  2038. }
  2039. static struct sde_rm_rsvp *_sde_rm_get_rsvp(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  2040. {
  2041. struct sde_rm_rsvp *i;
  2042. if (!rm || !enc) {
  2043. SDE_ERROR("invalid params\n");
  2044. return NULL;
  2045. }
  2046. if (list_empty(&rm->rsvps))
  2047. return NULL;
  2048. list_for_each_entry(i, &rm->rsvps, list)
  2049. if (i->pending == nxt && i->enc_id == enc->base.id)
  2050. return i;
  2051. return NULL;
  2052. }
  2053. static struct sde_rm_rsvp *_sde_rm_get_rsvp_nxt(struct sde_rm *rm, struct drm_encoder *enc)
  2054. {
  2055. return _sde_rm_get_rsvp(rm, enc, true);
  2056. }
  2057. static struct sde_rm_rsvp *_sde_rm_get_rsvp_cur(struct sde_rm *rm, struct drm_encoder *enc)
  2058. {
  2059. return _sde_rm_get_rsvp(rm, enc, false);
  2060. }
  2061. int sde_rm_update_topology(struct sde_rm *rm,
  2062. struct drm_connector_state *conn_state,
  2063. struct msm_display_topology *topology)
  2064. {
  2065. int i, ret = 0;
  2066. struct msm_display_topology top;
  2067. enum sde_rm_topology_name top_name = SDE_RM_TOPOLOGY_NONE;
  2068. if (!conn_state)
  2069. return -EINVAL;
  2070. if (topology) {
  2071. top = *topology;
  2072. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  2073. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i], top)) {
  2074. top_name = rm->topology_tbl[i].top_name;
  2075. break;
  2076. }
  2077. }
  2078. ret = msm_property_set_property(
  2079. sde_connector_get_propinfo(conn_state->connector),
  2080. sde_connector_get_property_state(conn_state),
  2081. CONNECTOR_PROP_TOPOLOGY_NAME, top_name);
  2082. return ret;
  2083. }
  2084. bool sde_rm_topology_is_group(struct sde_rm *rm,
  2085. struct drm_crtc_state *state,
  2086. enum sde_rm_topology_group group)
  2087. {
  2088. int i, ret = 0;
  2089. struct sde_crtc_state *cstate;
  2090. struct drm_connector *conn;
  2091. struct drm_connector_state *conn_state;
  2092. struct msm_display_topology topology;
  2093. enum sde_rm_topology_name name;
  2094. if ((!rm) || (!state) || (!state->state)) {
  2095. pr_err("invalid arguments: rm:%d state:%d atomic state:%d\n",
  2096. !rm, !state, state ? (!state->state) : 0);
  2097. return false;
  2098. }
  2099. cstate = to_sde_crtc_state(state);
  2100. for (i = 0; i < cstate->num_connectors; i++) {
  2101. conn = cstate->connectors[i];
  2102. if (!conn) {
  2103. SDE_DEBUG("invalid connector\n");
  2104. continue;
  2105. }
  2106. conn_state = drm_atomic_get_new_connector_state(state->state,
  2107. conn);
  2108. if (!conn_state) {
  2109. SDE_DEBUG("%s invalid connector state\n", conn->name);
  2110. continue;
  2111. }
  2112. ret = sde_connector_state_get_topology(conn_state, &topology);
  2113. if (ret) {
  2114. SDE_DEBUG("%s invalid topology\n", conn->name);
  2115. continue;
  2116. }
  2117. name = sde_rm_get_topology_name(rm, topology);
  2118. switch (group) {
  2119. case SDE_RM_TOPOLOGY_GROUP_SINGLEPIPE:
  2120. if (TOPOLOGY_SINGLEPIPE_MODE(name))
  2121. return true;
  2122. break;
  2123. case SDE_RM_TOPOLOGY_GROUP_DUALPIPE:
  2124. if (TOPOLOGY_DUALPIPE_MODE(name))
  2125. return true;
  2126. break;
  2127. case SDE_RM_TOPOLOGY_GROUP_QUADPIPE:
  2128. if (TOPOLOGY_QUADPIPE_MODE(name))
  2129. return true;
  2130. break;
  2131. case SDE_RM_TOPOLOGY_GROUP_3DMERGE:
  2132. if (topology.num_lm > topology.num_intf &&
  2133. !topology.num_enc)
  2134. return true;
  2135. break;
  2136. case SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC:
  2137. if (topology.num_lm > topology.num_enc &&
  2138. topology.num_enc)
  2139. return true;
  2140. break;
  2141. case SDE_RM_TOPOLOGY_GROUP_DSCMERGE:
  2142. if (topology.num_lm == topology.num_enc &&
  2143. topology.num_enc)
  2144. return true;
  2145. break;
  2146. default:
  2147. SDE_ERROR("invalid topology group\n");
  2148. return false;
  2149. }
  2150. }
  2151. return false;
  2152. }
  2153. /**
  2154. * _sde_rm_release_rsvp - release resources and release a reservation
  2155. * @rm: KMS handle
  2156. * @rsvp: RSVP pointer to release and release resources for
  2157. */
  2158. static void _sde_rm_release_rsvp(
  2159. struct sde_rm *rm,
  2160. struct sde_rm_rsvp *rsvp,
  2161. struct drm_connector *conn)
  2162. {
  2163. struct sde_rm_rsvp *rsvp_c, *rsvp_n;
  2164. struct sde_rm_hw_blk *blk;
  2165. enum sde_hw_blk_type type;
  2166. if (!rsvp)
  2167. return;
  2168. SDE_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
  2169. list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
  2170. if (rsvp == rsvp_c) {
  2171. list_del(&rsvp_c->list);
  2172. break;
  2173. }
  2174. }
  2175. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2176. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  2177. if (blk->rsvp == rsvp) {
  2178. blk->rsvp = NULL;
  2179. SDE_DEBUG("rel rsvp %d enc %d %d %d\n",
  2180. rsvp->seq, rsvp->enc_id,
  2181. blk->type, blk->id);
  2182. _sde_rm_inc_resource_info(rm,
  2183. &rm->avail_res, blk);
  2184. }
  2185. if (blk->rsvp_nxt == rsvp) {
  2186. blk->rsvp_nxt = NULL;
  2187. SDE_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
  2188. rsvp->seq, rsvp->enc_id,
  2189. blk->type, blk->id);
  2190. }
  2191. }
  2192. }
  2193. kfree(rsvp);
  2194. }
  2195. void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  2196. {
  2197. struct sde_rm_rsvp *rsvp;
  2198. struct drm_connector *conn = NULL;
  2199. struct msm_drm_private *priv;
  2200. struct sde_kms *sde_kms;
  2201. uint64_t top_ctrl = 0;
  2202. if (!rm || !enc) {
  2203. SDE_ERROR("invalid params\n");
  2204. return;
  2205. }
  2206. priv = enc->dev->dev_private;
  2207. if (!priv->kms) {
  2208. SDE_ERROR("invalid kms\n");
  2209. return;
  2210. }
  2211. sde_kms = to_sde_kms(priv->kms);
  2212. mutex_lock(&rm->rm_lock);
  2213. rsvp = _sde_rm_get_rsvp(rm, enc, nxt);
  2214. if (!rsvp) {
  2215. SDE_DEBUG("failed to find rsvp for enc %d, nxt %d",
  2216. enc->base.id, nxt);
  2217. goto end;
  2218. }
  2219. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  2220. _sde_rm_release_rsvp(rm, rsvp, conn);
  2221. goto end;
  2222. }
  2223. conn = _sde_rm_get_connector(enc);
  2224. if (!conn) {
  2225. SDE_EVT32(enc->base.id, 0x0, 0xffffffff);
  2226. _sde_rm_release_rsvp(rm, rsvp, conn);
  2227. SDE_DEBUG("failed to get conn for enc %d nxt %d\n",
  2228. enc->base.id, nxt);
  2229. goto end;
  2230. }
  2231. top_ctrl = sde_connector_get_property(conn->state,
  2232. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  2233. SDE_EVT32(enc->base.id, conn->base.id, rsvp->seq, top_ctrl, nxt);
  2234. if (top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK)) {
  2235. SDE_DEBUG("rsvp[s%de%d] not releasing locked resources\n",
  2236. rsvp->seq, rsvp->enc_id);
  2237. } else {
  2238. SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
  2239. rsvp->enc_id);
  2240. _sde_rm_release_rsvp(rm, rsvp, conn);
  2241. }
  2242. end:
  2243. mutex_unlock(&rm->rm_lock);
  2244. }
  2245. static void _sde_rm_commit_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  2246. struct drm_connector_state *conn_state)
  2247. {
  2248. struct sde_rm_hw_blk *blk;
  2249. enum sde_hw_blk_type type;
  2250. /* Swap next rsvp to be the active */
  2251. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2252. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  2253. if (blk->rsvp_nxt && conn_state->best_encoder->base.id
  2254. == blk->rsvp_nxt->enc_id) {
  2255. blk->rsvp = blk->rsvp_nxt;
  2256. blk->rsvp_nxt = NULL;
  2257. _sde_rm_dec_resource_info(rm,
  2258. &rm->avail_res, blk);
  2259. }
  2260. }
  2261. }
  2262. rsvp->pending = false;
  2263. SDE_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id, rsvp->topology);
  2264. SDE_EVT32(rsvp->enc_id, rsvp->topology);
  2265. }
  2266. static void _sde_rm_populate_dp_lm_mask(struct sde_rm *rm,
  2267. struct drm_connector *conn)
  2268. {
  2269. struct sde_connector *c_conn = NULL;
  2270. struct sde_rm_hw_blk *blk;
  2271. if (!rm || !conn) {
  2272. SDE_ERROR("invalid arguments\n");
  2273. return;
  2274. }
  2275. if (conn->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
  2276. return;
  2277. c_conn = to_sde_connector(conn);
  2278. if (!c_conn || !c_conn->encoder)
  2279. return;
  2280. list_for_each_entry(blk, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  2281. if (!blk->rsvp)
  2282. continue;
  2283. if (blk->rsvp->enc_id == c_conn->encoder->base.id)
  2284. c_conn->lm_mask |= BIT(blk->id - 1);
  2285. }
  2286. SDE_DEBUG("conn lm_mask %d for conn %d enc %d\n", c_conn->lm_mask,
  2287. conn->base.id, c_conn->encoder->base.id);
  2288. SDE_EVT32(c_conn->encoder->base.id, conn->base.id, c_conn->lm_mask);
  2289. }
  2290. /* call this only after rm_mutex held */
  2291. struct sde_rm_rsvp *_sde_rm_poll_get_rsvp_nxt_locked(struct sde_rm *rm,
  2292. struct drm_encoder *enc)
  2293. {
  2294. int i;
  2295. u32 loop_count = 20;
  2296. struct sde_rm_rsvp *rsvp_nxt = NULL;
  2297. u32 sleep = RM_NXT_CLEAR_POLL_TIMEOUT_US / loop_count;
  2298. for (i = 0; i < loop_count; i++) {
  2299. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2300. if (!rsvp_nxt)
  2301. return rsvp_nxt;
  2302. mutex_unlock(&rm->rm_lock);
  2303. SDE_DEBUG("iteration i:%d sleep range:%uus to %uus\n",
  2304. i, sleep, sleep * 2);
  2305. usleep_range(sleep, sleep * 2);
  2306. mutex_lock(&rm->rm_lock);
  2307. }
  2308. /* make sure to get latest rsvp_next to avoid use after free issues */
  2309. return _sde_rm_get_rsvp_nxt(rm, enc);
  2310. }
  2311. int sde_rm_reserve(
  2312. struct sde_rm *rm,
  2313. struct drm_encoder *enc,
  2314. struct drm_crtc_state *crtc_state,
  2315. struct drm_connector_state *conn_state,
  2316. bool test_only)
  2317. {
  2318. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  2319. struct sde_rm_requirements reqs = {0,};
  2320. struct msm_drm_private *priv;
  2321. struct sde_kms *sde_kms;
  2322. struct msm_compression_info *comp_info;
  2323. int ret = 0;
  2324. if (!rm || !enc || !crtc_state || !conn_state) {
  2325. SDE_ERROR("invalid arguments\n");
  2326. return -EINVAL;
  2327. }
  2328. if (!enc->dev || !enc->dev->dev_private) {
  2329. SDE_ERROR("drm device invalid\n");
  2330. return -EINVAL;
  2331. }
  2332. priv = enc->dev->dev_private;
  2333. if (!priv->kms) {
  2334. SDE_ERROR("invalid kms\n");
  2335. return -EINVAL;
  2336. }
  2337. sde_kms = to_sde_kms(priv->kms);
  2338. /* Check if this is just a page-flip */
  2339. if (!_sde_rm_is_display_in_cont_splash(sde_kms, enc) &&
  2340. !msm_atomic_needs_modeset(crtc_state, conn_state))
  2341. return 0;
  2342. comp_info = kzalloc(sizeof(*comp_info), GFP_KERNEL);
  2343. if (!comp_info)
  2344. return -ENOMEM;
  2345. SDE_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
  2346. conn_state->connector->base.id, enc->base.id,
  2347. crtc_state->crtc->base.id, test_only);
  2348. SDE_EVT32(enc->base.id, conn_state->connector->base.id, test_only);
  2349. mutex_lock(&rm->rm_lock);
  2350. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_BEGIN);
  2351. rsvp_cur = _sde_rm_get_rsvp_cur(rm, enc);
  2352. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2353. /*
  2354. * RM currently relies on rsvp_nxt assigned to the hw blocks to
  2355. * commit rsvps. This rsvp_nxt can be cleared by a back to back
  2356. * check_only commit with modeset when its predecessor atomic
  2357. * commit is delayed / not committed the reservation yet.
  2358. * Poll for rsvp_nxt clear, allow the check_only commit if rsvp_nxt
  2359. * gets cleared and bailout if it does not get cleared before timeout.
  2360. */
  2361. if (test_only && rsvp_nxt) {
  2362. rsvp_nxt = _sde_rm_poll_get_rsvp_nxt_locked(rm, enc);
  2363. rsvp_cur = _sde_rm_get_rsvp_cur(rm, enc);
  2364. if (rsvp_nxt) {
  2365. pr_err("poll timeout cur %d nxt %d enc %d\n",
  2366. (rsvp_cur) ? rsvp_cur->seq : -1,
  2367. rsvp_nxt->seq, enc->base.id);
  2368. SDE_EVT32(enc->base.id, (rsvp_cur) ? rsvp_cur->seq : -1,
  2369. rsvp_nxt->seq, SDE_EVTLOG_ERROR);
  2370. ret = -EAGAIN;
  2371. goto end;
  2372. }
  2373. }
  2374. if (!test_only && rsvp_nxt)
  2375. goto commit_rsvp;
  2376. reqs.hw_res.comp_info = comp_info;
  2377. ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
  2378. conn_state, sde_kms->catalog, &reqs);
  2379. if (ret) {
  2380. SDE_ERROR("failed to populate hw requirements\n");
  2381. goto end;
  2382. }
  2383. /*
  2384. * We only support one active reservation per-hw-block. But to implement
  2385. * transactional semantics for test-only, and for allowing failure while
  2386. * modifying your existing reservation, over the course of this
  2387. * function we can have two reservations:
  2388. * Current: Existing reservation
  2389. * Next: Proposed reservation. The proposed reservation may fail, or may
  2390. * be discarded if in test-only mode.
  2391. * If reservation is successful, and we're not in test-only, then we
  2392. * replace the current with the next.
  2393. */
  2394. rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
  2395. if (!rsvp_nxt) {
  2396. ret = -ENOMEM;
  2397. goto end;
  2398. }
  2399. /*
  2400. * User can request that we clear out any reservation during the
  2401. * atomic_check phase by using this CLEAR bit
  2402. */
  2403. if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) {
  2404. SDE_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
  2405. rsvp_cur->seq, rsvp_cur->enc_id);
  2406. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2407. rsvp_cur = NULL;
  2408. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
  2409. }
  2410. /* Check the proposed reservation, store it in hw's "next" field */
  2411. ret = _sde_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
  2412. rsvp_nxt, &reqs);
  2413. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_RSVPNEXT);
  2414. if (ret) {
  2415. SDE_ERROR("failed to reserve hw resources: %d, test_only %d\n",
  2416. ret, test_only);
  2417. _sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
  2418. goto end;
  2419. } else if (test_only && !RM_RQ_LOCK(&reqs)) {
  2420. /*
  2421. * Normally, if test_only, test the reservation and then undo
  2422. * However, if the user requests LOCK, then keep the reservation
  2423. * made during the atomic_check phase.
  2424. */
  2425. SDE_DEBUG("test_only: rsvp[s%de%d]\n",
  2426. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2427. goto end;
  2428. } else {
  2429. if (test_only && RM_RQ_LOCK(&reqs))
  2430. SDE_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
  2431. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2432. }
  2433. commit_rsvp:
  2434. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2435. _sde_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
  2436. _sde_rm_populate_dp_lm_mask(rm, conn_state->connector);
  2437. end:
  2438. kfree(comp_info);
  2439. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_FINAL);
  2440. mutex_unlock(&rm->rm_lock);
  2441. return ret;
  2442. }