sde_fence.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  7. #include <linux/sync_file.h>
  8. #include <linux/dma-fence.h>
  9. #include <linux/dma-fence-array.h>
  10. #include "msm_drv.h"
  11. #include "sde_kms.h"
  12. #include "sde_fence.h"
  13. #define TIMELINE_VAL_LENGTH 128
  14. #define SPEC_FENCE_FLAG_FENCE_ARRAY 0x10
  15. #define SPEC_FENCE_FLAG_ARRAY_BIND 0x11
  16. /**
  17. * struct sde_fence - release/retire fence structure
  18. * @base: base fence structure
  19. * @ctx: fence context
  20. * @name: name of each fence- it is fence timeline + commit_count
  21. * @fence_list: list to associated this fence on timeline/context
  22. * @fd: fd attached to this fence - debugging purpose.
  23. * @hwfence_out_ctl: hw ctl for the output fence
  24. * @hwfence_index: hw fence index for this fence
  25. * @txq_updated_fence: flag to indicate that a fence has been updated in txq
  26. */
  27. struct sde_fence {
  28. struct dma_fence base;
  29. struct sde_fence_context *ctx;
  30. char name[SDE_FENCE_NAME_SIZE];
  31. struct list_head fence_list;
  32. int fd;
  33. struct sde_hw_ctl *hwfence_out_ctl;
  34. u64 hwfence_index;
  35. bool txq_updated_fence;
  36. };
  37. /**
  38. * enum sde_hw_fence_clients - sde clients for the hw-fence feature
  39. *
  40. * Do not modify the order of this struct and/or add more elements
  41. * without modify/add fields in the 'hw_fence_data' structs.
  42. */
  43. enum sde_hw_fence_clients {
  44. SDE_HW_FENCE_CLIENT_CTL_0,
  45. SDE_HW_FENCE_CLIENT_CTL_1,
  46. SDE_HW_FENCE_CLIENT_CTL_2,
  47. SDE_HW_FENCE_CLIENT_CTL_3,
  48. SDE_HW_FENCE_CLIENT_CTL_4,
  49. SDE_HW_FENCE_CLIENT_CTL_5,
  50. SDE_HW_FENCE_CLIENT_MAX,
  51. };
  52. /**
  53. * hw_fence_data_dpu_client - this table maps the dpu ipcc input and output signals for each display
  54. * clients to communicate with the fence controller.
  55. * This struct must match the order of the 'sde_hw_fence_clients' enum,
  56. * the output signal must match with the signals that FenceCTL expects for each display client.
  57. * This 'hw_fence_data_dpu_client' must be used for HW that does not support dpu-signal.
  58. */
  59. struct sde_hw_fence_data hw_fence_data_no_dpu[SDE_HW_FENCE_CLIENT_MAX] = {
  60. {SDE_HW_FENCE_CLIENT_CTL_0, HW_FENCE_CLIENT_ID_CTL0, NULL, {0}, 8, 14, {2, 3}, 0, 8, 8},
  61. {SDE_HW_FENCE_CLIENT_CTL_1, HW_FENCE_CLIENT_ID_CTL1, NULL, {0}, 8, 15, {4, 5}, 0, 8, 8},
  62. {SDE_HW_FENCE_CLIENT_CTL_2, HW_FENCE_CLIENT_ID_CTL2, NULL, {0}, 8, 16, {6, 7}, 0, 8, 8},
  63. {SDE_HW_FENCE_CLIENT_CTL_3, HW_FENCE_CLIENT_ID_CTL3, NULL, {0}, 8, 17, {8, 9}, 0, 8, 8},
  64. {SDE_HW_FENCE_CLIENT_CTL_4, HW_FENCE_CLIENT_ID_CTL4, NULL, {0}, 8, 18, {10, 11}, 0, 8, 8},
  65. {SDE_HW_FENCE_CLIENT_CTL_5, HW_FENCE_CLIENT_ID_CTL5, NULL, {0}, 8, 19, {12, 13}, 0, 8, 8}
  66. };
  67. /**
  68. * hw_fence_data_dpu_client - this table maps the dpu ipcc input and output signals for each display
  69. * clients to communicate with the fence controller.
  70. * This struct must match the order of the 'sde_hw_fence_clients' enum,
  71. * the output signal must match with the signals that FenceCTL expects for each display client.
  72. * This 'hw_fence_data_dpu_client' must be used for HW that supports dpu-signal
  73. */
  74. struct sde_hw_fence_data hw_fence_data_dpu_client[SDE_HW_FENCE_CLIENT_MAX] = {
  75. {SDE_HW_FENCE_CLIENT_CTL_0, HW_FENCE_CLIENT_ID_CTL0, NULL, {0}, 8, 0, {0, 6}, 0, 8, 25},
  76. {SDE_HW_FENCE_CLIENT_CTL_1, HW_FENCE_CLIENT_ID_CTL1, NULL, {0}, 8, 1, {1, 7}, 0, 8, 25},
  77. {SDE_HW_FENCE_CLIENT_CTL_2, HW_FENCE_CLIENT_ID_CTL2, NULL, {0}, 8, 2, {2, 8}, 0, 8, 25},
  78. {SDE_HW_FENCE_CLIENT_CTL_3, HW_FENCE_CLIENT_ID_CTL3, NULL, {0}, 8, 3, {3, 9}, 0, 8, 25},
  79. {SDE_HW_FENCE_CLIENT_CTL_4, HW_FENCE_CLIENT_ID_CTL4, NULL, {0}, 8, 4, {4, 10}, 0, 8, 25},
  80. {SDE_HW_FENCE_CLIENT_CTL_5, HW_FENCE_CLIENT_ID_CTL5, NULL, {0}, 8, 5, {5, 11}, 0, 8, 25}
  81. };
  82. int sde_hw_fence_init(struct sde_hw_ctl *hw_ctl, bool use_dpu_ipcc)
  83. {
  84. struct sde_hw_fence_data *sde_hw_fence_data;
  85. struct sde_hw_fence_data *hwfence_data;
  86. int ctl_id;
  87. if (!hw_ctl)
  88. return -EINVAL;
  89. ctl_id = hw_ctl->idx - CTL_0;
  90. if (ctl_id >= SDE_HW_FENCE_CLIENT_MAX || ctl_id < 0) {
  91. SDE_ERROR("unexpected ctl_id:%d\n", ctl_id);
  92. return -EINVAL;
  93. }
  94. hwfence_data = &hw_ctl->hwfence_data;
  95. sde_hw_fence_data = use_dpu_ipcc ? hw_fence_data_dpu_client : hw_fence_data_no_dpu;
  96. if (sde_hw_fence_data[ctl_id].client_id != ctl_id) {
  97. SDE_ERROR("Unexpected client_id:%d for ctl_id:%d\n",
  98. sde_hw_fence_data[ctl_id].client_id, ctl_id);
  99. return -EINVAL;
  100. }
  101. /* init the default fence-data for this client */
  102. memcpy(hwfence_data, &sde_hw_fence_data[ctl_id], sizeof(struct sde_hw_fence_data));
  103. SDE_DEBUG("hwfence register ctl:%d client:%d\n", ctl_id, hwfence_data->hw_fence_client_id);
  104. hwfence_data->hw_fence_handle = msm_hw_fence_register(hwfence_data->hw_fence_client_id,
  105. &hwfence_data->mem_descriptor);
  106. if (IS_ERR_OR_NULL(hwfence_data->hw_fence_handle)) {
  107. hwfence_data->hw_fence_handle = NULL;
  108. SDE_ERROR("error cannot register ctl_id:%d hw-fence client:%d\n", ctl_id,
  109. hwfence_data->hw_fence_client_id);
  110. return -EINVAL;
  111. }
  112. SDE_DEBUG("hwfence registered ctl_id:%d hw_fence_client_id:%d handle:0x%p\n",
  113. ctl_id, hwfence_data->hw_fence_client_id, hwfence_data->hw_fence_handle);
  114. return 0;
  115. }
  116. void sde_hw_fence_deinit(struct sde_hw_ctl *hw_ctl)
  117. {
  118. struct sde_hw_fence_data *hwfence_data;
  119. if (!hw_ctl)
  120. return;
  121. hwfence_data = &hw_ctl->hwfence_data;
  122. /* client was not registered */
  123. if (IS_ERR_OR_NULL(hwfence_data->hw_fence_handle))
  124. return;
  125. SDE_DEBUG("hwfence deregister ctl_id:%d hw_fence_client_id:%d\n",
  126. hw_ctl->idx - CTL_0, hwfence_data->hw_fence_client_id);
  127. msm_hw_fence_deregister(hwfence_data->hw_fence_handle);
  128. hwfence_data->hw_fence_handle = NULL;
  129. }
  130. static int sde_fence_create_hw_fence(struct sde_hw_ctl *hw_ctl, struct sde_fence *sde_fence)
  131. {
  132. struct sde_hw_fence_data *data;
  133. struct msm_hw_fence_create_params params;
  134. int ctl_id;
  135. u64 hwfence_index;
  136. int ret;
  137. if (!hw_ctl)
  138. return -EINVAL;
  139. ctl_id = hw_ctl->idx - CTL_0;
  140. data = &hw_ctl->hwfence_data;
  141. if (IS_ERR_OR_NULL(data->hw_fence_handle)) {
  142. SDE_ERROR("unexpected handle for ctl_id:%d\n", ctl_id);
  143. return -EINVAL;
  144. }
  145. params.fence = &sde_fence->base;
  146. params.handle = &hwfence_index;
  147. /* Create the HW fence */
  148. ret = msm_hw_fence_create(data->hw_fence_handle, &params);
  149. if (ret) {
  150. SDE_ERROR("failed to create hw_fence for client:%d ctx:%llu seqno:%llu\n", ctl_id,
  151. sde_fence->base.context, sde_fence->base.seqno);
  152. } else {
  153. /* store ctl and index for this fence */
  154. sde_fence->hwfence_out_ctl = hw_ctl;
  155. sde_fence->hwfence_index = hwfence_index;
  156. SDE_DEBUG("create hfence index:%llu ctl:%d ctx:%llu seqno:%llu name:%s\n",
  157. sde_fence->hwfence_index, ctl_id, sde_fence->base.context,
  158. sde_fence->base.seqno, sde_fence->name);
  159. }
  160. return ret;
  161. }
  162. static inline char *_get_client_id_name(int hw_fence_client_id)
  163. {
  164. switch (hw_fence_client_id) {
  165. case HW_FENCE_CLIENT_ID_CTX0:
  166. return "HW_FENCE_CLIENT_ID_CTX0";
  167. case HW_FENCE_CLIENT_ID_CTL0:
  168. return "HW_FENCE_CLIENT_ID_CTL0";
  169. case HW_FENCE_CLIENT_ID_CTL1:
  170. return "HW_FENCE_CLIENT_ID_CTL1";
  171. case HW_FENCE_CLIENT_ID_CTL2:
  172. return "HW_FENCE_CLIENT_ID_CTL2";
  173. case HW_FENCE_CLIENT_ID_CTL3:
  174. return "HW_FENCE_CLIENT_ID_CTL3";
  175. case HW_FENCE_CLIENT_ID_CTL4:
  176. return "HW_FENCE_CLIENT_ID_CTL4";
  177. case HW_FENCE_CLIENT_ID_CTL5:
  178. return "HW_FENCE_CLIENT_ID_CTL15";
  179. default:
  180. return "Unknown";
  181. }
  182. return "unknown";
  183. }
  184. int sde_fence_register_hw_fences_wait(struct sde_hw_ctl *hw_ctl, struct dma_fence **fences,
  185. u32 num_fences)
  186. {
  187. struct sde_hw_fence_data *data;
  188. int i, ret;
  189. int ctl_id;
  190. if (!hw_ctl) {
  191. SDE_ERROR("wrong ctl\n");
  192. return -EINVAL;
  193. }
  194. ctl_id = hw_ctl->idx - CTL_0;
  195. data = &hw_ctl->hwfence_data;
  196. if (IS_ERR_OR_NULL(data->hw_fence_handle)) {
  197. SDE_ERROR("unexpected handle for ctl_id:%d\n", ctl_id);
  198. return -EINVAL;
  199. }
  200. SDE_DEBUG("register for wait fences:%d ctl_id:%d hw_fence_client:%s\n",
  201. num_fences, ctl_id, _get_client_id_name(data->hw_fence_client_id));
  202. for (i = 0; i < num_fences; i++) {
  203. SDE_DEBUG("registering fence: ctx:%llu seqno:%llu\n",
  204. (fences[i])->context, (fences[i])->seqno);
  205. }
  206. /* register for wait */
  207. ret = msm_hw_fence_wait_update(data->hw_fence_handle, fences, num_fences, true);
  208. if (ret)
  209. SDE_ERROR("failed to register wait fences for ctl_id:%d ret:%d\n", ctl_id, ret);
  210. SDE_EVT32_VERBOSE(ctl_id, num_fences, ret);
  211. return ret;
  212. }
  213. static int _arm_output_hw_fence(struct sde_hw_ctl *hw_ctl, u32 line_count, u32 debugfs_hw_fence)
  214. {
  215. struct sde_hw_fence_data *data;
  216. u32 ipcc_out_signal;
  217. int ctl_id;
  218. if (!hw_ctl || !hw_ctl->ops.hw_fence_trigger_output_fence ||
  219. !hw_ctl->ops.hw_fence_update_output_fence) {
  220. SDE_ERROR("missing ctl/trigger or update fence %d\n", !hw_ctl);
  221. return -EINVAL;
  222. }
  223. ctl_id = hw_ctl->idx - CTL_0;
  224. data = &hw_ctl->hwfence_data;
  225. if (data->ipcc_out_signal_pp_idx >= MAX_SDE_HFENCE_OUT_SIGNAL_PING_PONG) {
  226. /* This should not have happened!, review the ping pong calculation */
  227. SDE_ERROR("Wrong pp_idx:%d, max:%d\n", data->ipcc_out_signal_pp_idx,
  228. MAX_SDE_HFENCE_OUT_SIGNAL_PING_PONG);
  229. return -EINVAL;
  230. }
  231. ipcc_out_signal = data->ipcc_out_signal_pp[data->ipcc_out_signal_pp_idx];
  232. data->ipcc_out_signal_pp_idx = (++data->ipcc_out_signal_pp_idx %
  233. MAX_SDE_HFENCE_OUT_SIGNAL_PING_PONG);
  234. SDE_DEBUG("out-fence ctl_id:%d out_signal:%d hw_fence_client:%s\n",
  235. ctl_id, ipcc_out_signal, _get_client_id_name(data->hw_fence_client_id));
  236. if ((debugfs_hw_fence & SDE_OUTPUT_HW_FENCE_TIMESTAMP) &&
  237. hw_ctl->ops.hw_fence_output_timestamp_ctrl)
  238. hw_ctl->ops.hw_fence_output_timestamp_ctrl(hw_ctl, true, false);
  239. /* update client/signal output fence */
  240. hw_ctl->ops.hw_fence_update_output_fence(hw_ctl, data->ipcc_out_client, ipcc_out_signal);
  241. SDE_EVT32_VERBOSE(ctl_id, ipcc_out_signal);
  242. /* arm dpu to trigger output fence signal once ready */
  243. if (line_count)
  244. hw_ctl->ops.hw_fence_trigger_output_fence(hw_ctl,
  245. HW_FENCE_TRIGGER_SEL_PROG_LINE_COUNT);
  246. else
  247. hw_ctl->ops.hw_fence_trigger_output_fence(hw_ctl, HW_FENCE_TRIGGER_SEL_CTRL_DONE);
  248. return 0;
  249. }
  250. static int _sde_fence_arm_output_hw_fence(struct sde_fence_context *ctx, u32 line_count,
  251. u32 debugfs_hw_fence)
  252. {
  253. struct sde_hw_ctl *hw_ctl = NULL;
  254. struct sde_fence *fc, *next;
  255. spin_lock(&ctx->list_lock);
  256. if (list_empty(&ctx->fence_list_head)) {
  257. spin_unlock(&ctx->list_lock);
  258. return 0;
  259. }
  260. list_for_each_entry_safe(fc, next, &ctx->fence_list_head, fence_list) {
  261. struct dma_fence *fence = &fc->base;
  262. /* this is not hw-fence, or already processed */
  263. if (!test_bit(MSM_HW_FENCE_FLAG_ENABLED_BIT, &fence->flags))
  264. continue;
  265. hw_ctl = fc->hwfence_out_ctl;
  266. if (!hw_ctl) {
  267. /*
  268. * We flaged an output dma-fence as hw-fence but the hw ctl to handle
  269. * it is not available, this should not have happened, but if it does,
  270. * this can translate to a fence-timeout!
  271. */
  272. SDE_ERROR("invalid hw ctl, this can cause a fence-timeout!\n");
  273. SDE_EVT32(SDE_EVTLOG_ERROR, SDE_EVTLOG_FUNC_CASE1, fence->flags,
  274. fence->context, fence->seqno);
  275. spin_unlock(&ctx->list_lock);
  276. return -EINVAL;
  277. }
  278. }
  279. spin_unlock(&ctx->list_lock);
  280. /* arm dpu to trigger output hw-fence ipcc signal upon completion */
  281. if (hw_ctl)
  282. _arm_output_hw_fence(hw_ctl, line_count, debugfs_hw_fence);
  283. return 0;
  284. }
  285. /* update output hw_fences txq */
  286. int sde_fence_update_hw_fences_txq(struct sde_fence_context *ctx, bool vid_mode, u32 line_count,
  287. u32 debugfs_hw_fence)
  288. {
  289. int ret = 0;
  290. struct sde_hw_fence_data *data;
  291. struct sde_fence *fc, *next;
  292. struct sde_hw_ctl *hw_ctl = NULL;
  293. int ctl_id;
  294. bool txq_updated = false;
  295. spin_lock(&ctx->list_lock);
  296. if (list_empty(&ctx->fence_list_head)) {
  297. spin_unlock(&ctx->list_lock);
  298. return 0;
  299. }
  300. list_for_each_entry_safe(fc, next, &ctx->fence_list_head, fence_list) {
  301. struct dma_fence *fence = &fc->base;
  302. /* this is not hw-fence, or already processed */
  303. if (!test_bit(MSM_HW_FENCE_FLAG_ENABLED_BIT, &fence->flags) ||
  304. fc->txq_updated_fence)
  305. continue;
  306. hw_ctl = fc->hwfence_out_ctl;
  307. if (!hw_ctl) {
  308. /* We flaged an output dma-fence as hw-fence but the hw ctl to handle
  309. * it is not available, this should not have happened, but if it does,
  310. * this can translate to a fence-timeout!
  311. */
  312. SDE_ERROR("invalid hw ctl, this can cause a fence-timeout!\n");
  313. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, fence->flags, fence->context,
  314. fence->seqno, SDE_EVTLOG_ERROR);
  315. ret = -EINVAL;
  316. goto exit;
  317. }
  318. ctl_id = hw_ctl->idx - CTL_0;
  319. data = &hw_ctl->hwfence_data;
  320. if (IS_ERR_OR_NULL(data->hw_fence_handle)) {
  321. SDE_ERROR("unexpected handle for ctl_id:%d, this can fence-timeout\n",
  322. ctl_id);
  323. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, fence->flags, fence->context,
  324. fence->seqno, ctl_id, SDE_EVTLOG_ERROR);
  325. ret = -EINVAL;
  326. goto exit;
  327. }
  328. /* update hw-fence tx queue */
  329. ret = msm_hw_fence_update_txq(data->hw_fence_handle, fc->hwfence_index, 0, 0);
  330. if (ret) {
  331. SDE_ERROR("fail txq update index:%llu fctx:%llu seqno:%llu client:%d\n",
  332. fc->hwfence_index, fence->context, fence->seqno,
  333. data->hw_fence_client_id);
  334. SDE_EVT32(SDE_EVTLOG_FUNC_CASE3, fence->flags, fence->context,
  335. fence->seqno, ctl_id, SDE_EVTLOG_ERROR);
  336. goto exit;
  337. }
  338. /* avoid updating txq more than once and avoid repeating the same fence twice */
  339. txq_updated = fc->txq_updated_fence = true;
  340. SDE_DEBUG("update txq fence:0x%pK ctx:%llu seqno:%llu f:0x%llx ctl:%d vid:%d\n",
  341. fence, fence->context, fence->seqno, fence->flags, ctl_id, vid_mode);
  342. /* We will update TxQ one time per frame */
  343. if (txq_updated)
  344. break;
  345. }
  346. exit:
  347. spin_unlock(&ctx->list_lock);
  348. /* arm dpu to trigger output hw-fence ipcc signal upon completion in vid-mode */
  349. if ((txq_updated && hw_ctl) || line_count)
  350. _sde_fence_arm_output_hw_fence(ctx, line_count, debugfs_hw_fence);
  351. return ret;
  352. }
  353. static void _sde_hw_fence_release(struct sde_fence *f)
  354. {
  355. struct sde_hw_fence_data *data;
  356. struct sde_hw_ctl *hw_ctl = f->hwfence_out_ctl;
  357. int ctl_id;
  358. int ret;
  359. if (!hw_ctl) {
  360. SDE_ERROR("invalid hw_ctl\n");
  361. return;
  362. }
  363. ctl_id = hw_ctl->idx - CTL_0;
  364. data = &hw_ctl->hwfence_data;
  365. if (IS_ERR_OR_NULL(data->hw_fence_handle)) {
  366. SDE_ERROR("unexpected handle for ctl_id:%d\n", ctl_id);
  367. return;
  368. }
  369. SDE_DEBUG("destroy hw fence ctl_id:%d ctx:%llu seqno:%llu name:%s\n",
  370. ctl_id, f->base.context, f->base.seqno, f->name);
  371. /* Delete the HW fence */
  372. ret = msm_hw_fence_destroy(data->hw_fence_handle, &f->base);
  373. if (ret)
  374. SDE_ERROR("failed to destroy hw_fence for ctl_id:%d ctx:%llu seqno:%llu\n", ctl_id,
  375. f->base.context, f->base.seqno);
  376. }
  377. static int _reset_hw_fence_timeline(struct sde_hw_ctl *hw_ctl, u32 flags)
  378. {
  379. struct sde_hw_fence_data *data;
  380. int ret = 0;
  381. data = &hw_ctl->hwfence_data;
  382. if (!IS_ERR_OR_NULL(data->hw_fence_handle)) {
  383. SDE_EVT32(data->hw_fence_client_id);
  384. ret = msm_hw_fence_reset_client(data->hw_fence_handle, flags);
  385. if (ret) {
  386. pr_err("failed to reset client %d\n", data->hw_fence_client_id);
  387. return -EINVAL;
  388. }
  389. }
  390. return ret;
  391. }
  392. int sde_fence_update_input_hw_fence_signal(struct sde_hw_ctl *hw_ctl, u32 debugfs_hw_fence,
  393. struct sde_hw_mdp *hw_mdp, bool disable)
  394. {
  395. struct sde_hw_fence_data *data;
  396. u32 ipcc_signal_id;
  397. u32 ipcc_client_id;
  398. int ctl_id;
  399. /* we must support sw_override as well, so check both functions */
  400. if (!hw_mdp || !hw_ctl || !hw_ctl->ops.hw_fence_update_input_fence ||
  401. !hw_ctl->ops.hw_fence_trigger_sw_override) {
  402. SDE_ERROR("missing ctl/override/update fence %d\n", !hw_ctl);
  403. return -EINVAL;
  404. }
  405. ctl_id = hw_ctl->idx - CTL_0;
  406. data = &hw_ctl->hwfence_data;
  407. if (disable) {
  408. hw_ctl->ops.hw_fence_ctrl(hw_ctl, false, false, 0);
  409. return -EPERM;
  410. }
  411. if ((debugfs_hw_fence & SDE_INPUT_HW_FENCE_TIMESTAMP)
  412. && hw_mdp->ops.hw_fence_input_timestamp_ctrl)
  413. hw_mdp->ops.hw_fence_input_timestamp_ctrl(hw_mdp, true, false);
  414. ipcc_signal_id = data->ipcc_in_signal;
  415. ipcc_client_id = data->ipcc_in_client;
  416. SDE_DEBUG("configure input signal:%d out client:%d ctl_id:%d\n", ipcc_signal_id,
  417. ipcc_client_id, ctl_id);
  418. SDE_EVT32(ctl_id, ipcc_signal_id, ipcc_client_id);
  419. /* configure dpu hw for the client/signal pair signaling input-fence */
  420. hw_ctl->ops.hw_fence_update_input_fence(hw_ctl, ipcc_client_id, ipcc_signal_id);
  421. /* Enable hw-fence for this ctrl-path */
  422. hw_ctl->ops.hw_fence_ctrl(hw_ctl, true, true, 1);
  423. return 0;
  424. }
  425. void *sde_sync_get(uint64_t fd)
  426. {
  427. /* force signed compare, fdget accepts an int argument */
  428. return (signed int)fd >= 0 ? sync_file_get_fence(fd) : NULL;
  429. }
  430. void sde_sync_put(void *fence)
  431. {
  432. if (fence)
  433. dma_fence_put(fence);
  434. }
  435. void sde_fence_dump(struct dma_fence *fence)
  436. {
  437. char timeline_str[TIMELINE_VAL_LENGTH];
  438. if (fence->ops->timeline_value_str)
  439. fence->ops->timeline_value_str(fence, timeline_str, TIMELINE_VAL_LENGTH);
  440. SDE_ERROR(
  441. "fence drv name:%s timeline name:%s seqno:0x%llx timeline:%s signaled:0x%x status:%d flags:0x%x\n",
  442. fence->ops->get_driver_name(fence),
  443. fence->ops->get_timeline_name(fence),
  444. fence->seqno, timeline_str,
  445. fence->ops->signaled ?
  446. fence->ops->signaled(fence) : 0xffffffff,
  447. dma_fence_get_status(fence), fence->flags);
  448. }
  449. static void sde_fence_dump_user_fds_info(struct dma_fence *base_fence)
  450. {
  451. struct dma_fence_array *array;
  452. struct dma_fence *user_fence;
  453. int i;
  454. array = container_of(base_fence, struct dma_fence_array, base);
  455. if (test_bit(SPEC_FENCE_FLAG_FENCE_ARRAY, &base_fence->flags) &&
  456. test_bit(SPEC_FENCE_FLAG_ARRAY_BIND, &base_fence->flags)) {
  457. for (i = 0; i < array->num_fences; i++) {
  458. user_fence = array->fences[i];
  459. if (user_fence) {
  460. dma_fence_get(user_fence);
  461. sde_fence_dump(user_fence);
  462. dma_fence_put(user_fence);
  463. }
  464. }
  465. }
  466. }
  467. signed long sde_sync_wait(void *fnc, long timeout_ms)
  468. {
  469. struct dma_fence *fence = fnc;
  470. int rc, status = 0;
  471. if (!fence)
  472. return -EINVAL;
  473. else if (dma_fence_is_signaled(fence))
  474. return timeout_ms ? msecs_to_jiffies(timeout_ms) : 1;
  475. rc = dma_fence_wait_timeout(fence, true,
  476. msecs_to_jiffies(timeout_ms));
  477. if (!rc || (rc == -EINVAL) || fence->error) {
  478. status = dma_fence_get_status(fence);
  479. if (test_bit(SPEC_FENCE_FLAG_FENCE_ARRAY, &fence->flags)) {
  480. if (status == -EINVAL) {
  481. SDE_INFO("spec fence bind failure status:%d\n", status);
  482. rc = -EBADF;
  483. } else if (fence->ops->signaled && fence->ops->signaled(fence)) {
  484. SDE_INFO("spec fence status:%d\n", status);
  485. } else {
  486. sde_fence_dump(fence);
  487. sde_fence_dump_user_fds_info(fence);
  488. }
  489. } else {
  490. sde_fence_dump(fence);
  491. }
  492. }
  493. return rc;
  494. }
  495. uint32_t sde_sync_get_name_prefix(void *fence)
  496. {
  497. const char *name;
  498. uint32_t i, prefix;
  499. struct dma_fence *f = fence;
  500. if (!fence)
  501. return 0;
  502. name = f->ops->get_driver_name(f);
  503. if (!name)
  504. return 0;
  505. prefix = 0x0;
  506. for (i = 0; i < sizeof(uint32_t) && name[i]; ++i)
  507. prefix = (prefix << CHAR_BIT) | name[i];
  508. return prefix;
  509. }
  510. static void sde_fence_destroy(struct kref *kref)
  511. {
  512. struct sde_fence_context *ctx;
  513. if (!kref) {
  514. SDE_ERROR("received invalid kref\n");
  515. return;
  516. }
  517. ctx = container_of(kref, struct sde_fence_context, kref);
  518. kfree(ctx);
  519. }
  520. static inline struct sde_fence *to_sde_fence(struct dma_fence *fence)
  521. {
  522. return container_of(fence, struct sde_fence, base);
  523. }
  524. static const char *sde_fence_get_driver_name(struct dma_fence *fence)
  525. {
  526. struct sde_fence *f = to_sde_fence(fence);
  527. return f->name;
  528. }
  529. static const char *sde_fence_get_timeline_name(struct dma_fence *fence)
  530. {
  531. struct sde_fence *f = to_sde_fence(fence);
  532. return f->ctx->name;
  533. }
  534. static bool sde_fence_enable_signaling(struct dma_fence *fence)
  535. {
  536. return true;
  537. }
  538. static bool sde_fence_signaled(struct dma_fence *fence)
  539. {
  540. struct sde_fence *f = to_sde_fence(fence);
  541. bool status;
  542. status = ((int)(fence->seqno - f->ctx->done_count) <= 0);
  543. SDE_DEBUG("status:%d fence seq:%llu and timeline:%u\n",
  544. status, fence->seqno, f->ctx->done_count);
  545. return status;
  546. }
  547. static void sde_fence_release(struct dma_fence *fence)
  548. {
  549. struct sde_fence *f;
  550. if (fence) {
  551. f = to_sde_fence(fence);
  552. /* Delete the HW fence */
  553. if (test_bit(MSM_HW_FENCE_FLAG_ENABLED_BIT, &fence->flags))
  554. _sde_hw_fence_release(f);
  555. kref_put(&f->ctx->kref, sde_fence_destroy);
  556. kfree(f);
  557. }
  558. }
  559. static void sde_fence_value_str(struct dma_fence *fence, char *str, int size)
  560. {
  561. if (!fence || !str)
  562. return;
  563. snprintf(str, size, "%llu", fence->seqno);
  564. }
  565. static void sde_fence_timeline_value_str(struct dma_fence *fence, char *str,
  566. int size)
  567. {
  568. struct sde_fence *f = to_sde_fence(fence);
  569. if (!fence || !f->ctx || !str)
  570. return;
  571. snprintf(str, size, "%d", f->ctx->done_count);
  572. }
  573. static struct dma_fence_ops sde_fence_ops = {
  574. .get_driver_name = sde_fence_get_driver_name,
  575. .get_timeline_name = sde_fence_get_timeline_name,
  576. .enable_signaling = sde_fence_enable_signaling,
  577. .signaled = sde_fence_signaled,
  578. .wait = dma_fence_default_wait,
  579. .release = sde_fence_release,
  580. .fence_value_str = sde_fence_value_str,
  581. .timeline_value_str = sde_fence_timeline_value_str,
  582. };
  583. /**
  584. * _sde_fence_create_fd - create fence object and return an fd for it
  585. * This function is NOT thread-safe.
  586. * @timeline: Timeline to associate with fence
  587. * @val: Timeline value at which to signal the fence
  588. * Return: File descriptor on success, or error code on error
  589. */
  590. static int _sde_fence_create_fd(void *fence_ctx, uint32_t val, struct sde_hw_ctl *hw_ctl)
  591. {
  592. struct sde_fence *sde_fence;
  593. struct sync_file *sync_file;
  594. signed int fd = -EINVAL;
  595. struct sde_fence_context *ctx = fence_ctx;
  596. if (!ctx) {
  597. SDE_ERROR("invalid context\n");
  598. goto exit;
  599. }
  600. sde_fence = kzalloc(sizeof(*sde_fence), GFP_KERNEL);
  601. if (!sde_fence)
  602. return -ENOMEM;
  603. sde_fence->ctx = fence_ctx;
  604. snprintf(sde_fence->name, SDE_FENCE_NAME_SIZE, "sde_fence:%s:%u",
  605. sde_fence->ctx->name, val);
  606. dma_fence_init(&sde_fence->base, &sde_fence_ops, &ctx->lock,
  607. ctx->context, val);
  608. kref_get(&ctx->kref);
  609. /* create fd */
  610. fd = get_unused_fd_flags(0);
  611. if (fd < 0) {
  612. SDE_ERROR("failed to get_unused_fd_flags(), %s\n",
  613. sde_fence->name);
  614. dma_fence_put(&sde_fence->base);
  615. goto exit;
  616. }
  617. /* create fence */
  618. sync_file = sync_file_create(&sde_fence->base);
  619. if (sync_file == NULL) {
  620. put_unused_fd(fd);
  621. fd = -EINVAL;
  622. SDE_ERROR("couldn't create fence, %s\n", sde_fence->name);
  623. dma_fence_put(&sde_fence->base);
  624. goto exit;
  625. }
  626. /* If ctl_id is valid, try to create a hw-fence */
  627. if (hw_ctl)
  628. sde_fence_create_hw_fence(hw_ctl, sde_fence);
  629. fd_install(fd, sync_file->file);
  630. sde_fence->fd = fd;
  631. spin_lock(&ctx->list_lock);
  632. list_add_tail(&sde_fence->fence_list, &ctx->fence_list_head);
  633. spin_unlock(&ctx->list_lock);
  634. exit:
  635. return fd;
  636. }
  637. struct sde_fence_context *sde_fence_init(const char *name, uint32_t drm_id)
  638. {
  639. struct sde_fence_context *ctx;
  640. if (!name) {
  641. SDE_ERROR("invalid argument(s)\n");
  642. return ERR_PTR(-EINVAL);
  643. }
  644. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  645. if (!ctx) {
  646. SDE_ERROR("failed to alloc fence ctx\n");
  647. return ERR_PTR(-ENOMEM);
  648. }
  649. strlcpy(ctx->name, name, ARRAY_SIZE(ctx->name));
  650. ctx->drm_id = drm_id;
  651. kref_init(&ctx->kref);
  652. ctx->context = dma_fence_context_alloc(1);
  653. spin_lock_init(&ctx->lock);
  654. spin_lock_init(&ctx->list_lock);
  655. INIT_LIST_HEAD(&ctx->fence_list_head);
  656. return ctx;
  657. }
  658. void sde_fence_deinit(struct sde_fence_context *ctx)
  659. {
  660. if (!ctx) {
  661. SDE_ERROR("invalid fence\n");
  662. return;
  663. }
  664. kref_put(&ctx->kref, sde_fence_destroy);
  665. }
  666. void sde_fence_prepare(struct sde_fence_context *ctx)
  667. {
  668. unsigned long flags;
  669. if (!ctx) {
  670. SDE_ERROR("invalid argument(s), fence %pK\n", ctx);
  671. } else {
  672. spin_lock_irqsave(&ctx->lock, flags);
  673. ++ctx->commit_count;
  674. spin_unlock_irqrestore(&ctx->lock, flags);
  675. }
  676. }
  677. static void _sde_fence_trigger(struct sde_fence_context *ctx, bool error, ktime_t ts)
  678. {
  679. unsigned long flags;
  680. struct sde_fence *fc, *next;
  681. bool is_signaled = false;
  682. kref_get(&ctx->kref);
  683. spin_lock(&ctx->list_lock);
  684. if (list_empty(&ctx->fence_list_head)) {
  685. SDE_DEBUG("nothing to trigger!\n");
  686. goto end;
  687. }
  688. list_for_each_entry_safe(fc, next, &ctx->fence_list_head, fence_list) {
  689. spin_lock_irqsave(&ctx->lock, flags);
  690. if (error)
  691. dma_fence_set_error(&fc->base, -EBUSY);
  692. is_signaled = sde_fence_signaled(&fc->base);
  693. if (is_signaled)
  694. dma_fence_signal_timestamp_locked(&fc->base, ts);
  695. spin_unlock_irqrestore(&ctx->lock, flags);
  696. if (is_signaled) {
  697. list_del_init(&fc->fence_list);
  698. dma_fence_put(&fc->base);
  699. }
  700. }
  701. end:
  702. spin_unlock(&ctx->list_lock);
  703. kref_put(&ctx->kref, sde_fence_destroy);
  704. }
  705. int sde_fence_create(struct sde_fence_context *ctx, uint64_t *val,
  706. uint32_t offset, struct sde_hw_ctl *hw_ctl)
  707. {
  708. uint32_t trigger_value;
  709. int fd, rc = -EINVAL;
  710. unsigned long flags;
  711. if (!ctx || !val) {
  712. SDE_ERROR("invalid argument(s), fence %d, pval %d\n",
  713. ctx != NULL, val != NULL);
  714. return rc;
  715. }
  716. /*
  717. * Allow created fences to have a constant offset with respect
  718. * to the timeline. This allows us to delay the fence signalling
  719. * w.r.t. the commit completion (e.g., an offset of +1 would
  720. * cause fences returned during a particular commit to signal
  721. * after an additional delay of one commit, rather than at the
  722. * end of the current one.
  723. */
  724. spin_lock_irqsave(&ctx->lock, flags);
  725. trigger_value = ctx->commit_count + offset;
  726. spin_unlock_irqrestore(&ctx->lock, flags);
  727. fd = _sde_fence_create_fd(ctx, trigger_value, hw_ctl);
  728. *val = fd;
  729. SDE_DEBUG("fd:%d trigger:%d commit:%d offset:%d\n",
  730. fd, trigger_value, ctx->commit_count, offset);
  731. SDE_EVT32(ctx->drm_id, trigger_value, fd, hw_ctl ? hw_ctl->idx : 0);
  732. rc = (fd >= 0) ? 0 : fd;
  733. return rc;
  734. }
  735. void sde_fence_signal(struct sde_fence_context *ctx, ktime_t ts,
  736. enum sde_fence_event fence_event, struct sde_hw_ctl *hw_ctl)
  737. {
  738. unsigned long flags;
  739. if (!ctx) {
  740. SDE_ERROR("invalid ctx, %pK\n", ctx);
  741. return;
  742. }
  743. spin_lock_irqsave(&ctx->lock, flags);
  744. if (fence_event == SDE_FENCE_RESET_TIMELINE) {
  745. /* reset hw-fences without error */
  746. if (hw_ctl)
  747. _reset_hw_fence_timeline(hw_ctl, MSM_HW_FENCE_RESET_WITHOUT_ERROR |
  748. MSM_HW_FENCE_RESET_WITHOUT_DESTROY);
  749. if ((int)(ctx->done_count - ctx->commit_count) < 0) {
  750. SDE_DEBUG(
  751. "timeline reset attempt! ctx:0x%x done count:%d commit:%d\n",
  752. ctx->drm_id, ctx->done_count, ctx->commit_count);
  753. ctx->done_count = ctx->commit_count;
  754. SDE_EVT32(ctx->drm_id, ctx->done_count,
  755. ctx->commit_count, ktime_to_us(ts),
  756. fence_event, SDE_EVTLOG_FUNC_CASE1);
  757. } else {
  758. spin_unlock_irqrestore(&ctx->lock, flags);
  759. return;
  760. }
  761. } else if ((int)(ctx->done_count - ctx->commit_count) < 0) {
  762. ++ctx->done_count;
  763. SDE_DEBUG("fence_signal:done count:%d commit count:%d\n",
  764. ctx->done_count, ctx->commit_count);
  765. } else {
  766. SDE_ERROR("extra signal attempt! done count:%d commit:%d\n",
  767. ctx->done_count, ctx->commit_count);
  768. SDE_EVT32(ctx->drm_id, ctx->done_count, ctx->commit_count,
  769. ktime_to_us(ts), fence_event, SDE_EVTLOG_FATAL);
  770. spin_unlock_irqrestore(&ctx->lock, flags);
  771. return;
  772. }
  773. spin_unlock_irqrestore(&ctx->lock, flags);
  774. SDE_EVT32(ctx->drm_id, ctx->done_count, ctx->commit_count,
  775. ktime_to_us(ts));
  776. _sde_fence_trigger(ctx, (fence_event == SDE_FENCE_SIGNAL_ERROR), ts);
  777. }
  778. void sde_fence_timeline_status(struct sde_fence_context *ctx,
  779. struct drm_mode_object *drm_obj)
  780. {
  781. char *obj_name;
  782. if (!ctx || !drm_obj) {
  783. SDE_ERROR("invalid input params\n");
  784. return;
  785. }
  786. switch (drm_obj->type) {
  787. case DRM_MODE_OBJECT_CRTC:
  788. obj_name = "crtc";
  789. break;
  790. case DRM_MODE_OBJECT_CONNECTOR:
  791. obj_name = "connector";
  792. break;
  793. default:
  794. obj_name = "unknown";
  795. break;
  796. }
  797. SDE_ERROR("drm obj:%s id:%d type:0x%x done_count:%d commit_count:%d\n",
  798. obj_name, drm_obj->id, drm_obj->type, ctx->done_count,
  799. ctx->commit_count);
  800. }
  801. void sde_fence_list_dump(struct dma_fence *fence, struct seq_file **s)
  802. {
  803. char timeline_str[TIMELINE_VAL_LENGTH];
  804. if (fence->ops->timeline_value_str)
  805. fence->ops->timeline_value_str(fence,
  806. timeline_str, TIMELINE_VAL_LENGTH);
  807. seq_printf(*s, "fence name:%s timeline name:%s seqno:0x%llx timeline:%s signaled:0x%x\n",
  808. fence->ops->get_driver_name(fence),
  809. fence->ops->get_timeline_name(fence),
  810. fence->seqno, timeline_str,
  811. fence->ops->signaled ?
  812. fence->ops->signaled(fence) : 0xffffffff);
  813. }
  814. void sde_debugfs_timeline_dump(struct sde_fence_context *ctx,
  815. struct drm_mode_object *drm_obj, struct seq_file **s)
  816. {
  817. char *obj_name;
  818. struct sde_fence *fc, *next;
  819. struct dma_fence *fence;
  820. if (!ctx || !drm_obj) {
  821. SDE_ERROR("invalid input params\n");
  822. return;
  823. }
  824. switch (drm_obj->type) {
  825. case DRM_MODE_OBJECT_CRTC:
  826. obj_name = "crtc";
  827. break;
  828. case DRM_MODE_OBJECT_CONNECTOR:
  829. obj_name = "connector";
  830. break;
  831. default:
  832. obj_name = "unknown";
  833. break;
  834. }
  835. seq_printf(*s, "drm obj:%s id:%d type:0x%x done_count:%d commit_count:%d\n",
  836. obj_name, drm_obj->id, drm_obj->type, ctx->done_count,
  837. ctx->commit_count);
  838. spin_lock(&ctx->list_lock);
  839. list_for_each_entry_safe(fc, next, &ctx->fence_list_head, fence_list) {
  840. fence = &fc->base;
  841. sde_fence_list_dump(fence, s);
  842. }
  843. spin_unlock(&ctx->list_lock);
  844. }