dp_panel.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #ifndef _DP_PANEL_H_
  7. #define _DP_PANEL_H_
  8. #include <drm/sde_drm.h>
  9. #include "dp_aux.h"
  10. #include "dp_link.h"
  11. #include "sde_edid_parser.h"
  12. #include "sde_connector.h"
  13. #include "msm_drv.h"
  14. #define DP_RECEIVER_DSC_CAP_SIZE 15
  15. #define DP_RECEIVER_FEC_STATUS_SIZE 3
  16. #define DP_RECEIVER_EXT_CAP_SIZE 4
  17. /*
  18. * A source initiated power down flag is set
  19. * when the DP is powered off while physical
  20. * DP cable is still connected i.e. without
  21. * HPD or not initiated by sink like HPD_IRQ.
  22. * This can happen if framework reboots or
  23. * device suspends.
  24. */
  25. #define DP_PANEL_SRC_INITIATED_POWER_DOWN BIT(0)
  26. #define DP_EXT_REC_CAP_FIELD BIT(7)
  27. enum dp_lane_count {
  28. DP_LANE_COUNT_1 = 1,
  29. DP_LANE_COUNT_2 = 2,
  30. DP_LANE_COUNT_4 = 4,
  31. };
  32. enum dp_output_format {
  33. DP_OUTPUT_FORMAT_RGB,
  34. DP_OUTPUT_FORMAT_YCBCR420,
  35. DP_OUTPUT_FORMAT_YCBCR422,
  36. DP_OUTPUT_FORMAT_YCBCR444,
  37. DP_OUTPUT_FORMAT_INVALID,
  38. };
  39. #define DP_MAX_DOWNSTREAM_PORTS 0x10
  40. struct dp_panel_info {
  41. u32 h_active;
  42. u32 v_active;
  43. u32 h_back_porch;
  44. u32 h_front_porch;
  45. u32 h_sync_width;
  46. u32 h_active_low;
  47. u32 v_back_porch;
  48. u32 v_front_porch;
  49. u32 v_sync_width;
  50. u32 v_active_low;
  51. u32 h_skew;
  52. u32 refresh_rate;
  53. u32 pixel_clk_khz;
  54. u32 bpp;
  55. bool widebus_en;
  56. struct msm_compression_info comp_info;
  57. s64 dsc_overhead_fp;
  58. };
  59. struct dp_display_mode {
  60. struct dp_panel_info timing;
  61. u32 capabilities;
  62. s64 fec_overhead_fp;
  63. s64 dsc_overhead_fp;
  64. /**
  65. * @output_format:
  66. *
  67. * This is used to indicate DP output format.
  68. * The output format can be read from drm_mode.
  69. */
  70. enum dp_output_format output_format;
  71. };
  72. struct dp_panel;
  73. struct dp_panel_in {
  74. struct device *dev;
  75. struct dp_aux *aux;
  76. struct dp_link *link;
  77. struct dp_catalog_panel *catalog;
  78. struct drm_connector *connector;
  79. struct dp_panel *base_panel;
  80. struct dp_parser *parser;
  81. };
  82. struct dp_dsc_caps {
  83. bool dsc_capable;
  84. u8 version;
  85. bool block_pred_en;
  86. u8 color_depth;
  87. };
  88. struct dp_audio;
  89. #define DP_PANEL_CAPS_DSC BIT(0)
  90. struct dp_panel {
  91. /* dpcd raw data */
  92. u8 dpcd[DP_RECEIVER_CAP_SIZE + DP_RECEIVER_EXT_CAP_SIZE + 1];
  93. u8 ds_ports[DP_MAX_DOWNSTREAM_PORTS];
  94. u8 dsc_dpcd[DP_RECEIVER_DSC_CAP_SIZE + 1];
  95. u8 fec_dpcd;
  96. u8 fec_sts_dpcd[DP_RECEIVER_FEC_STATUS_SIZE + 1];
  97. struct drm_dp_link link_info;
  98. struct sde_edid_ctrl *edid_ctrl;
  99. struct dp_panel_info pinfo;
  100. bool video_test;
  101. bool spd_enabled;
  102. u32 vic;
  103. u32 max_pclk_khz;
  104. s64 mst_target_sc;
  105. /* debug */
  106. u32 max_bw_code;
  107. u32 lane_count;
  108. u32 link_bw_code;
  109. /* By default, stream_id is assigned to DP_INVALID_STREAM.
  110. * Client sets the stream id value using set_stream_id interface.
  111. */
  112. enum dp_stream_id stream_id;
  113. int vcpi;
  114. u32 channel_start_slot;
  115. u32 channel_total_slots;
  116. u32 pbn;
  117. u32 dsc_blks_in_use;
  118. u32 max_lm;
  119. /* DRM connector assosiated with this panel */
  120. struct drm_connector *connector;
  121. struct dp_audio *audio;
  122. bool audio_supported;
  123. struct dp_dsc_caps sink_dsc_caps;
  124. bool dsc_feature_enable;
  125. bool fec_feature_enable;
  126. bool dsc_en;
  127. bool fec_en;
  128. bool widebus_en;
  129. bool dsc_continuous_pps;
  130. bool mst_state;
  131. /* override debug option */
  132. bool mst_hide;
  133. bool mode_override;
  134. int hdisplay;
  135. int vdisplay;
  136. int vrefresh;
  137. int aspect_ratio;
  138. s64 fec_overhead_fp;
  139. int (*init)(struct dp_panel *dp_panel);
  140. int (*deinit)(struct dp_panel *dp_panel, u32 flags);
  141. int (*hw_cfg)(struct dp_panel *dp_panel, bool enable);
  142. int (*read_sink_caps)(struct dp_panel *dp_panel,
  143. struct drm_connector *connector, bool multi_func);
  144. u32 (*get_mode_bpp)(struct dp_panel *dp_panel, u32 mode_max_bpp,
  145. u32 mode_pclk_khz, bool dsc_en);
  146. int (*get_modes)(struct dp_panel *dp_panel,
  147. struct drm_connector *connector, struct dp_display_mode *mode);
  148. void (*handle_sink_request)(struct dp_panel *dp_panel);
  149. int (*setup_hdr)(struct dp_panel *dp_panel,
  150. struct drm_msm_ext_hdr_metadata *hdr_meta,
  151. bool dhdr_update, u64 core_clk_rate, bool flush);
  152. int (*set_colorspace)(struct dp_panel *dp_panel,
  153. u32 colorspace);
  154. void (*tpg_config)(struct dp_panel *dp_panel, u32 pattern);
  155. int (*spd_config)(struct dp_panel *dp_panel);
  156. bool (*hdr_supported)(struct dp_panel *dp_panel);
  157. int (*set_stream_info)(struct dp_panel *dp_panel,
  158. enum dp_stream_id stream_id, u32 ch_start_slot,
  159. u32 ch_tot_slots, u32 pbn, int vcpi);
  160. int (*read_sink_status)(struct dp_panel *dp_panel, u8 *sts, u32 size);
  161. int (*update_edid)(struct dp_panel *dp_panel, struct edid *edid);
  162. bool (*read_mst_cap)(struct dp_panel *dp_panel);
  163. void (*convert_to_dp_mode)(struct dp_panel *dp_panel,
  164. const struct drm_display_mode *drm_mode,
  165. struct dp_display_mode *dp_mode);
  166. void (*update_pps)(struct dp_panel *dp_panel, char *pps_cmd);
  167. int (*sink_crc_enable)(struct dp_panel *dp_panel, bool enable);
  168. int (*get_src_crc)(struct dp_panel *dp_panel, u16 *crc);
  169. int (*get_sink_crc)(struct dp_panel *dp_panel, u16 *crc);
  170. };
  171. struct dp_tu_calc_input {
  172. u64 lclk; /* 162, 270, 540 and 810 */
  173. u64 pclk_khz; /* in KHz */
  174. u64 hactive; /* active h-width */
  175. u64 hporch; /* bp + fp + pulse */
  176. int nlanes; /* no.of.lanes */
  177. int bpp; /* bits */
  178. int pixel_enc; /* 444, 420, 422 */
  179. int dsc_en; /* dsc on/off */
  180. int async_en; /* async mode */
  181. int fec_en; /* fec */
  182. int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
  183. int num_of_dsc_slices; /* number of slices per line */
  184. };
  185. struct dp_vc_tu_mapping_table {
  186. u32 vic;
  187. u8 lanes;
  188. u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
  189. u8 bpp;
  190. u32 valid_boundary_link;
  191. u32 delay_start_link;
  192. bool boundary_moderation_en;
  193. u32 valid_lower_boundary_link;
  194. u32 upper_boundary_count;
  195. u32 lower_boundary_count;
  196. u32 tu_size_minus1;
  197. };
  198. /**
  199. * is_link_rate_valid() - validates the link rate
  200. * @lane_rate: link rate requested by the sink
  201. *
  202. * Returns true if the requested link rate is supported.
  203. */
  204. static inline bool is_link_rate_valid(u32 bw_code)
  205. {
  206. return ((bw_code == DP_LINK_BW_1_62) ||
  207. (bw_code == DP_LINK_BW_2_7) ||
  208. (bw_code == DP_LINK_BW_5_4) ||
  209. (bw_code == DP_LINK_BW_8_1));
  210. }
  211. /**
  212. * dp_link_is_lane_count_valid() - validates the lane count
  213. * @lane_count: lane count requested by the sink
  214. *
  215. * Returns true if the requested lane count is supported.
  216. */
  217. static inline bool is_lane_count_valid(u32 lane_count)
  218. {
  219. return (lane_count == DP_LANE_COUNT_1) ||
  220. (lane_count == DP_LANE_COUNT_2) ||
  221. (lane_count == DP_LANE_COUNT_4);
  222. }
  223. struct dp_panel *dp_panel_get(struct dp_panel_in *in);
  224. void dp_panel_put(struct dp_panel *dp_panel);
  225. void dp_panel_calc_tu_test(struct dp_tu_calc_input *in,
  226. struct dp_vc_tu_mapping_table *tu_table);
  227. #endif /* _DP_PANEL_H_ */