EXTRA_CFLAGS += -DWLAN_CFG_PER_PDEV_TX_RING=0
EXTRA_CFLAGS += -DWLAN_CFG_IPA_UC_TX_BUF_SIZE=0
EXTRA_CFLAGS += -DWLAN_CFG_IPA_UC_TX_PARTITION_BASE=0
EXTRA_CFLAGS += -DWLAN_CFG_IPA_UC_RX_IND_RING_COUNT=0
EXTRA_CFLAGS += -DWLAN_CFG_PER_PDEV_RX_RING=0
EXTRA_CFLAGS += -DWLAN_CFG_PER_PDEV_LMAC_RING=1
EXTRA_CFLAGS += -DWLAN_LRO_ENABLE=0
EXTRA_CFLAGS += -DWLAN_CFG_NUM_TX_EXT_DESC=0x80000
EXTRA_CFLAGS += -DWLAN_CFG_INT_BATCH_THRESHOLD_TX=256
EXTRA_CFLAGS += -DWLAN_CFG_INT_BATCH_THRESHOLD_RX=128
EXTRA_CFLAGS += -DWLAN_CFG_INT_BATCH_THRESHOLD_OTHER=1
EXTRA_CFLAGS += -DWLAN_CFG_INT_TIMER_THRESHOLD_TX=1000
EXTRA_CFLAGS += -DWLAN_CFG_INT_TIMER_THRESHOLD_RX=500
EXTRA_CFLAGS += -DWLAN_CFG_INT_TIMER_THRESHOLD_OTHER=1000
EXTRA_CFLAGS += -DWLAN_CFG_TX_RING_SIZE=512
EXTRA_CFLAGS += -DWLAN_CFG_TX_COMP_RING_SIZE=0x80000
EXTRA_CFLAGS += -DWLAN_CFG_TX_FLOW_START_QUEUE_OFFSET=0
EXTRA_CFLAGS += -DWLAN_CFG_TX_FLOW_STOP_QUEUE_TH=0
EXTRA_CFLAGS += -DWLAN_CFG_RXDMA1_ENABLE=1
EXTRA_CFLAGS += -DDP_PPDU_TXLITE_STATS_BITMASK_CFG=0xFFFF
EXTRA_CFLAGS += -DDP_TX_NAPI_BUDGET_DIV_MASK=0xFFFF
EXTRA_CFLAGS += -DCONFIG_PROCESS_RX_STATUS=0
EXTRA_CFLAGS += -DCONFIG_PROCESS_TX_STATUS=0
EXTRA_CFLAGS += -DWLAN_CFG_MAC_PER_TARGET=3
ifeq ($(strip ${CONFIG_WIFI_EMULATION_WIFI_3_0}),1)
EXTRA_CFLAGS += -DWLAN_CFG_NUM_TX_DESC=0x2000
else
EXTRA_CFLAGS += -DWLAN_CFG_NUM_TX_DESC=0x320000
endif

ifeq ($(strip ${NO_RX_PKT_HDR_TLV}),1)
#RX_BUFFER_SIZE = 1536 data bytes + 256 RX TLV bytes. We are avoiding
#128 bytes of RX_PKT_HEADER_TLV.
EXTRA_CFLAGS += -DRX_DATA_BUFFER_SIZE=1792
EXTRA_CFLAGS += -DRX_DATA_BUFFER_ALIGNMENT=0
endif