/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.*/
/* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.*/

#ifndef __AUDIO_EXT_CLK_H
#define __AUDIO_EXT_CLK_H

/* Audio External Clocks */
#define AUDIO_PMI_CLK                 0
#define AUDIO_PMIC_LNBB_CLK           1
#define AUDIO_LPASS_MCLK              2  /* VA CORE CLK */
#define AUDIO_LPASS_MCLK_2            3  /* WSA1 CORE CLK */
#define AUDIO_LPASS_MCLK_3            4  /* WSA1 NPL CLK */
#define AUDIO_LPASS_MCLK_4            5  /* RX CORE CLK */
#define AUDIO_LPASS_MCLK_5            6  /* RX NPL CLK */
#define AUDIO_LPASS_MCLK_6            7  /* TX CORE CLK */
#define AUDIO_LPASS_MCLK_7            8  /* TX NPL CLK */
#define AUDIO_LPASS_CORE_HW_VOTE      9
#define AUDIO_LPASS_MCLK_8            10 /* VA NPL CLK */
#define AUDIO_LPASS_AUDIO_HW_VOTE     11
#define AUDIO_LPASS_MCLK_9            12 /* WSA2 CORE CLK */
#define AUDIO_LPASS_MCLK_10           13 /* RX_TX CORE CLK */
#define AUDIO_LPASS_MCLK_11           14 /* WSA_TX CORE CLK */
#define AUDIO_LPASS_MCLK_12           15 /* WSA2_TX CORE CLK */
#define AUDIO_LPASS_MCLK_13           16 /* RX_MCLK2 2X CLK */
#define AUDIO_LPASS_MCLK_14           17 /* HW SEQUNCER MCLK */
#define AUDIO_LPASS_MCLK_15           18 /* BT_SWR CLK */
#define AUDIO_LPASS_MCLK_16           19 /* BT_SWR 2X CLK */
#endif