The following change introduced new misspellings of "address", so fix
them.
- Change-Id Idc9eec559b71ebb2dc39ea1d648a384ea0eb9559
qcacmn: Fetch the reo qdesc from the peer
Change-Id: I29c71972d46a06c24fef2ed90d2a4226cc2ac654
CRs-Fixed: 3319356
When compact rx tlv feature is enabled fetch the
reo qdesc from the peer instead of rx pkt tlvs.
Change-Id: Idc9eec559b71ebb2dc39ea1d648a384ea0eb9559
CRs-Fixed: 3311270
Adding compact tlv support for QCN9224, As part of this change
Rx tlv size will reduce from 384 bytes to 128 bytes.
Change-Id: I3f42a781e42b2e696a5b25d9c5f333c8cc83b7fe
CRs-Fixed: 3274152
In WIN BE chipsets, replace the REO tid
queue programming in FW via WMI with writing to a
Host managed table shared by HW and SW. REO HW will
pick the tid queue address from the table indexed by
peer id and tid number.
Change-Id: I8107ca5116425538329b11ae3519f02b32573bac
Prefetch RX HW desc, SW desc and SKB in pipeline
fasion in the first loop of RX processing.
This has improved TPUT by 200Mbps and provided a
10% gain in CPU (single core)
PINE with other optimizations: 3960Mbps @ 100% core-3
PINE + pipeline prefetch: 4130Mbps @ 90% core-3
Change-Id: I47f351601b264eb3a2b50e4154229d55da738724
Adding a nbuf and nbuf->data prefetches in 2nd loop
of Lithium datapath RX improved UDP throughput by
about 250Mbps.
PINE default driver: 3189Mbps @ 100% core-3
PINE with prefetch: 3469Mbps @ 100% core-3
Note: PINE reo ring is mapped to core-3.
Change-Id: I7f166b52c3697facdce3954994755c9c1412c1f3
Take care of the MLO peer bit indication to be
concatenated with peer_id to access the peer map
object.
Change-Id: Ia603a728101e83829a8906d1b847f42389e78ca6
CRs-Fixed: 3039326
Implement core DP rx processing to functions in to corresponding
architecture specific be/li rx files. Keep common utility functions
in DP common files.
Change-Id: I40083e10772fd2b6ce2f1fa9e197f2ad92d0522a
CRs-Fixed: 2891021
