Limit clock rate of shadow VCO clock as normal VCO clock.
For larger bit clock rate gap between switched ones, the clock switching
would fail due to mismatched VCO clock rate between normal VCO clock and
shadow one.
Change-Id: I9d68725de360ac28c243a3ce1800bfb139f39757
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This change updates the DSI PHY PLL programming for kona target
as per the hardware recommendation.
Change-Id: I706169fb635e72bd0ccd3057107ea749408733d0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Remove dividers that are not recommended for DSI DPHY mode
when setting up the clock tree for the DSI pixel clock.
Change-Id: I2563a35ece541c1f5b46c72af7bd2cc79e72a90e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add support for 7nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch and dfps feature.
Change-Id: I870f961c7af4d404e61b45a4ad860ffb0e71ae7c
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
This change updates SSC offset value according to recent
hardware recommendation.
Change-Id: Ie822ed6ae8e383f93ca91615617dad4b4324b8a0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The divider clocks in the DSI PLL are 1-based and can accept
a value of 0. Set the flags accordingly in the PLL driver.
CRs-Fixed: 2433864
Change-Id: I82361ae3e2119f9e1922153bd5aba6354e8c5442
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Remove the CLK_GET_RATE_NOCACHE flag from all the DP and DSI
pll clocks. This will eliminate the need to recalculate the
clock rates from HW registers when querying the rates for the
PLL clocks. This will ensure that no unclocked register accesses
are done when these clocks are queried while the display core
is power collapsed.
Change-Id: Ia5e993195cadc2bced32c052bb604e9980ecd4d8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
In continuous splash use cases, the display is enabled in
the boot-loader. During display kernel probe, to enable clocks,
the rate is calculated by reading the hardware registers before
the corresponding software rate is set. At times when these rates
are nearly equal, the call for set rate never happens. This can
cause abnormal behavior. In this change during hand-off we don't
recalculate the clock rate to ensure the software programs the clock
registers accordingly.
Change-Id: I421c523ffd48a0cb73d7721c6d74c8e68aa6d9a5
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
