Pineapple target adds support for writeback contributing to
fal status. This removes the need to signal fal10 veto in those
usecases. In addition, it is no longer needed to program uidle
active per ctl path.
Change-Id: I5e3509fa6399d212563322d51eba04c38a41e9b8
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change enables the WB rotation feature support for pineapple target.
Change-Id: Ib222c2b2996a40c72414c6c3a581916b95ebffd6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
MDSS 10.0.0 HW supports rotation of input image with
writeback HW but output color formats are restricted to
32 bit uncompressed A5X tile formats. This change exposes
the supported WB output color formats to client for WB
rotation usecase.
Change-Id: Ic52e6ee4ab882b7dad6edd0daa91b593afbcae01
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change installs required drm properties for writeback
connector to implement rotation with writeback hw in mdss.
Change-Id: I85ed359d06ff4bafee85a4bfa5b8a99774311e60
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Set the boolean property to enable second dedicated
CWB feature on pineapple hardware.
Change-Id: Ibacf0ec327c5d6d803f1fc5211dedb3a591b441a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Update the hardware blocks and corresponding APIs
to configure new D-CWB data path. Add new hardware
pingpong blocks that are dedicated for second DCWB.
Change-Id: I529c24ac5aa483f30b6c9e7653eb1713c6b8fb8a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This feature enables using all available bits when ICH
error calculations are made. This improves precision and
image quality when there are more than 8 bits per component.
Change-Id: I851f05418283d0e731332d4069e3b6e57487b9a3
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds support for INTF TE using 32 bit values and
single update per TE. These features help ensure that during
QSync mode the TE does not overrun in certain late trigger uses.
Change-Id: I893d0cde81320c3f17604694a4d8ee52b29a9425
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Currently, the driver uses the panel frame count along with
mdp vsync timestamp which can be unreliable if there are any
latencies. This change adds support to use mdp vsync frame
count, if the hardware supports it.
Change-Id: I784d4f4e525212269371a40071bcb912181cba9f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds pineapple mdss revision and enables features
based on the hardware capabilities.
Change-Id: I930e1ffd8e070f5bd258e5d3e441a966ade5f760
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
During dcwb mixer allocation, resource manager allocates
the first available mixer in the free list. In dual display
uses case with 1 1 1 topology if only secondary is running
CWB then, resource manager allocates DCWB0 which leads to wb
timeout due to HW does not have the connection between LM1
and DCWB0. This change allocates proper dcwb for the LMs in RM.
Change-Id: I0c8b04b46ccad5a7d7dd591fbfa3ea0915eccdc6
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
When cwb is triggered on built-in display secondary display
with (1,1,1) topology, improper dcwb_idx value is passed
to pp_dither and CTL registers. This change populates proper
dcwb_idx during pp block dt parsing and passes the same for
programming.
Change-Id: I543eede6f5fd9c2c80799503e3639ea9e89058ca
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Add bound check for number of dnsc_blur blocks, while parsing from
device tree. Fix out of bound access while setting the llcc_active
during system cache disable case in writeback.
Change-Id: I7e604db5ebfaa6e8b6f066e0f6efb76e7d78e604
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support display emulation targets on RUMI
This change does the following:
-parse dt node to enable display emulation mode.
-use sde_reg_read for pool timeout ops and debug fs dump.
-increases the kickoff timeout when emulation is enabled.
-bypass AXI halt operation when emulation is enabled.
Change-Id: Idc493964c0b8fc89f5d85fcc5755e0874a12d211
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add support for localized CLK_CTRL access through LUTDMA
hardware block.
This change aggregates RD/WR LUTDMA CLK_CTRL in a single
ops.
Change-Id: Id5c24bebf7dfcd9f768b2a6f6fa03f8b01747354
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.
Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently only LLCC_DISP SCID is used to read and write to
system cache during static display use case.
This changes adds SCID LLCC_DISP_1 to allow each SCID to
have a dedicated function (read/write).
Change-Id: I5604ec1183d99a8492b005ec06ac94e5db60b5f7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.
This change converts it to use a feature bit instead.
Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
UBWC revision is in the expanded form, no need to process it again.
Change-Id: Ie4aafeea5459a76f325a07e58af1de5665fe45ba
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Add sde hw catalog change to enable LLCC_DISP_WB system cache, which
is used for 2-pass composition usecases with offline writeback path.
Change-Id: Ic320b95a6699e59c62fed41f7fb88c484d98ffd0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
Remove hardcoding LLCC use case id and use catalog information
to decide which system cache section to use.
Change-Id: I9748ca1f3569db0cf77689af296def0759fe94cc
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Enable trusted vm flag for kalama target
Change-Id: I2f2c0a838914d5fccf6642690c082c592e04e38d
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.
Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add check to avoid more than 1 CWB active per commit as
hardware doesn't support multiple CWB even if they are
on different OP.
Change-Id: I13416cc2af881de0d8bdd6544a4fdc180fb7a050
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Kalama adds support for uidle fill level scaling to allow
fal10 mode for 90 and above fps use cases.
Pre-Kalama, the fill levels are clamped at 4-bit values supported
by the threshold registers. But to achieve the targeted 50us idle
time on fal10 modes with higher FPS use cases, we need fill levels
higher than 15 (max for 4 bit). The hardware change in Kalama
achieves by using a 5 bit scale factor in combination with the
programmed threshold values.
Change-Id: I638705355c03910a83e7d922b6fe48ab11c120a8
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change adds Detail Enhancer LPF blend support from MDSS 9.0.
Support is added for qseed block in both SSPP and Destination Scaler.
Change-Id: Ic8e3732059498a156f51fb93c5fd6638bd731c57
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Parametrize RC minimum region width restriction as it
differs starting from Kailua.
Change-Id: I41e7cd6812ed2fadb5719ee51f4db0723be632fe
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.
Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the cwb block offset and stride values for kalama
target in sde hw catalog. As part of the change, allow the
ctl wb-flush bit for cwb to be set based on the wb idx used.
Change-Id: Ibf7ccda88cbb47bddacf53b5af9841d381a4766c
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
From kalama, add support for QoS fill level calculations based on
line-based QoS calculations.
Change-Id: I524ca29c6e9d1912b44a328a2a88d08341cccefc
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support to parse and configure QoS values for offline writeback.
Expose a writeback connector property to allow user-mode to set
the usage type of the writeback block - WFD, CWB, offline-WB.
Change-Id: I864f79c4896ec757ac2d8b0f57a6a5775d164f21
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the sde HW catalog parsing to get separate values for rp_remap
and lvl_remap for each qos level. Previously, only rp_remap were provided
and the same was applied for lvl_remap. As part of the change, add cnoc
remap level which is added as part of MDSS 9.x.
Change-Id: I112a715f8b33cd4b028886d8074e35fef75b8aab
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the DT parsing logic to get danger/safe LUT values for
both portrait & landscape for all the usage types.
As part of the change, fix the correct CDP write setting for
CWB usecase.
Change-Id: I4fb6d17537de5df31c9b7f52983c0c3890265174
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
