DCS commands are not supported on DP displays, thus there is
no need to wait for active region to start before triggering
a DCS command which can cause additional latency during power
ON use case.
This change skips the active region wait for non DSI panels.
Change-Id: I50c6b808f839468bda74b13d7a75e8410d81dd0d
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
When VSYNC interrupts are delayed due to irq latencies, there is a
possibility that the timeout handler checking the irq status and the
irq handler clearing the status bit happening at the same time on
different CPU cores. This is reported as an error, though there is
not actual issue. Handle this case, by adding an additional ctl-flush
register check in the vsync timeout handler. As part of the change
add error/eventlogs in commit-done wait failures.
Change-Id: Ie7e30dc4ef1e50651cee9015cd3f2caeacf47e5f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds the value of hw-fence ready to
event logs for video and command modes.
Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
DCS commands triggered right after timing engine enable can conflict
with blanking period causing command transfer failures. Right after
timing engine enable poll for frame start and line count reaching
active region of display before any DCS commands.
Change-Id: Ia3967e01c3bb5bc82aa3549c300fa8335e00210c
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.
Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
allocates new resources and CTL_1 is allocated.
sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.
Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
The sde_hw_blk was meant to be a generic base object for all
SDE HW blocks, however, it enforces using a common set of ops
which is not practical when blocks have different capabilities.
Since this object was never used as intended and is not doing
anything functional today, remove the dead weight.
Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.
Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.
Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
VA minidumps supports to add any allocated variable or data to
minidumps. Add panic notifier and wrapper function to add
sde data to minidump va. Add event log, register log, register dumps,
debug bus and different sde variables and states info to minidump.
Change-Id: If54da0b7067df17877e4da645d82f1705baa3f6d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
This change adds line count to info being added to the
event log buffer.
Change-Id: Ic51b12bb3fbff206603ca8265cd916972418d0d2
Signed-off-by: Grace An <gracan@codeaurora.org>
Add AVR step support so SW can trigger a late frame and instead
of immediately triggering, HW will perform the update at the
start of the next step interval. This allows for a fixed SW
vsync timeline to be maintained in userland, eliminating the
usual drift from the actual HW vsync caused by a late frame.
This change adds AVR_STEP support via a DRM property.
Change-Id: I4cf8a296989805f134c2165a3bed0b050bb09c96
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Currently, SDE_DBG_DUMP takes any number of hw block names along with
few defined strings as arguments. This set of arguments is used to
determine which HW block registers needs to be dumped. Move to a
blk bitmask to avoid passing a large set of arguments. The bitmask is
split based on the clks required to access the HW block for ease of use.
The lower 0-23 bits are used for HW blocks which can be accessed by just
enabling the MDP clks. DP is kept separate as it needs DP specific
clks to be enabled. Add a debugfs node through which the mask can be
modified, which can be useful while using the debugfs dump option to
force a panic.
As part of the change, remove in-log/in-mem enable mask debugfs node
for every debugbus and use a single node to control the logging
mechanism for all the HW blocks debugbus.
Change-Id: Ibb6354b3e3265c9911104bb0f964616eb8a898c9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 8.x INTF line/frame counters can be reset through
a register. Reset these counters during timing engine enable /
tear-check enable to keep track of meaningful counters, which
would be useful during debugging. Additionally, reset the
counters during cont-splash modeset to track the number of
auto-refresh frames while disabling it during the first frame.
Change-Id: I66b45f5b29793df1fb4635972b1c614ad8c3b5b3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Use of drm_display_mode vrefresh is being deprecated in
upstream DRM framework. Downstream driver need to use
drm_mode_vrefresh API from now on.
This change removes dependency on drm_display_mode vrefresh
and replaces it with drm_mode_vrefresh API in SDE, DSI and
DP driver. In addition, it also modifies drm_display_mode clock
to align with upstream approach where an uncompressed mode clock
is required to match drm_mode_vrefresh API.
Change-Id: Ie972a2e140adfd81c4e68df8e7bc69feaaca22e1
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Currently sde_encoder_phys_vid_wait_for_active function
tries to precisely wait for the first line in the active
region. This logic can be simplified by waiting a fixed
amount of time considering that this feature is only used
during hardware recovery use case.
Change-Id: Ibfd5a22c8384a184f9576275e46739a99a263323
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Move away from the private and private_flags fields from drm_mode,
as it is being deprecated in latest kernel version. Instead, Add
msm_display_mode as a wrapper to be used in downstream to store these
parameters. Also, store msm_mode in connector_state to be accessed
in commit path.
Change-Id: Ia5bdebe75f00aa15fb7db4dc3a0d50c30894a95c
Signed-off-by: Orion Brody <obrody@codeaurora.org>
Enabling and disabling programmable fetch dynamically
across different fps can cause dsi underflow/overflow followed
by underrun. Add changes to always enable prog fetch to handle
such cases. Fix needed_prefill_lines calculation for vfp method
of dfps since linetime is constant in this method and hence
prefill lines need to be based on max_fps. For panels whose
linetime varies with fps, the needed_prefill_lines calculation
remains unchanged.
Change-Id: Ib7b68b577ff903fc2359a8e8c4573d62d55c3828
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
On frame timeouts, the driver should only be responsible for
reporting the error event to user space clients. Handling of
the error events should be left to the user space clients.
This change removes explicit mechanism in SDE driver to track
error events for a pre-defined threshold levels and RESET hints
sent to the user space on handling those error events during
frame timeouts.
Change-Id: I7bdf2495fae6430384b4031a7edf043b6efe88c5
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
During frame updates if vsync timeout happens, the probable reason
is pixel_clock is turned off. In such a case the recent update is
not applied on hw and can lead to issues. For example if a pipe
was detached it will not get detached since this update will not
take place.
This change detects the timeout and requests a hard reset from user mode
driver so as to ensure that all the displays are power off and footswitch
is turned off. This will ensure dpu hardware gets reset.
Change-Id: Ic9bade88b6502feb7334d239eaf669977233dbac
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Currently, during ctl reset in video mode, irq register or
unregister might result in race condition with vblank
enable/disable calls on event thread resulting in enable
cnt mismatch. This change adds mutex locks to avoid race
conditions in such cases.
Change-Id: I45aef19864475ac1b02dd8e84810eee233fc60ea
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
This change adds support to program both qsync and variable
refresh rate in the same atomic commit. During vrr
usecase, if qsync is enabled, avr ctrl gets programmed
during prepare phase as well as after configuring timing
engine. This change also handles such scenarios to prevent
double programming of avr ctrl.
Change-Id: I19461423b0ae08c8204b5edeb98e3d73ce16a21b
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
In current implementation qsync min fps is single value.
It is same for all the list of supported dfps list.
Added support for new dt entry dsi-supported-qsync-min-fps-list
corresponding to the fps supported in the dfps list
dsi-supported-dfps-list.
Change-Id: Ifd5309c2f51865a3c0d9fadb65cbcd291b6ef42b
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Add the INTF interrupt status register value to the underrun
line count event log to assist in debugging these issues.
Change-Id: I847cb12f8b4565d5f04667e0abda5d051a6194b2
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change adds 2 vsync delay after changing the timing engine
parameters namely the porches to update the refresh rate.
This ensures that panel vsync is updated as per new timing before
modifying it again.
Change-Id: I5866ea2f6f2e68bc8ce7435c4a5dbe27d8ebdd91
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Fix prefill line calculation for high refresh rate
usecase and define correct number of prefill lines
for lahaina target.
Change-Id: Ib3467b9beb43de9c5faa2b1af2d8873a89c9c481
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
With 120 fps panels and vfp method of dfps ,the vfp is very large in lower
fps and there is huge time gap between programmable fetch start (MDP vsync)
and panel vsync. As fence is released early timing registers are modified
by the next commit before the previous timing parameters takes effect and
this is leading to underrun. With variable programmable fetch start MDP
vsync is close to panel vsync and avoids such condition.
Change-Id: Id88b5e2957bf4af751f49f1f32327715a34b102b
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
VM switches during TUI usecase are expected to be seamless i.e without
display reset. In SDE language, this translates to respective display
drivers not tearing down the HW pipeline while releasing the HW.
In Primary VM, this taken care by keeping the DRM pipeline alive when
TUI is active.
In Trusted VM, since the client creates and destroys the display per
session, checks are needed to bypass the physical encoder disable(s).
Change-Id: Iac42f02806962405c9364b1ffed85778229977e9
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.
Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Add null check for pingpong block used during
the commit phase.
Change-Id: I3ebbcfe9c42ee6d1201a141f553bbb0a0ae97ad6
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
This change adds logic to align timing engine vsync with panel
tear check if it is supported.
Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add underrun line count information for each underrun.
Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.
Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This change enables the interface hw block to accept
64-bit compressed pixels. This configuration is enabled based
on hw capability. For current hw, this is required any time
the compressed pixels flow through the interface block,
whereas in the previous version of DPU hw this configuration
is only required for topology using 4 way dsc merge.
Change-Id: I7bf79d035dba5084c5057022a7fa1117479e8d52
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.
Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.
Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
As overall display driver is moving away from hard-coded compression
ratios, prepare the DP driver for the same by removing the usage of
the compression ratio enum.
Change-Id: I298db7d20baed8afec9f96dff8c7e950702bfec9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support to configure the DPU pipeline to support VDC-m
topologies.
Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
