Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).
This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.
Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Update the hardware blocks and corresponding APIs
to configure new D-CWB data path. Add new hardware
pingpong blocks that are dedicated for second DCWB.
Change-Id: I529c24ac5aa483f30b6c9e7653eb1713c6b8fb8a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Add support display emulation targets on RUMI
This change does the following:
-parse dt node to enable display emulation mode.
-use sde_reg_read for pool timeout ops and debug fs dump.
-increases the kickoff timeout when emulation is enabled.
-bypass AXI halt operation when emulation is enabled.
Change-Id: Idc493964c0b8fc89f5d85fcc5755e0874a12d211
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
When qsync is enabled with a large threshold start window, there
is a chance that two frames can be latched by mdp HW in single
vsync window. This change overrides the tearcheck rd_ptr_val
to a value larger than the end of the Tear check start window
to ensure new frame is not latched in current vsync window.
Change-Id: I21273f0bca83747210792b911e964dfd2d50079f
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates the autorefresh disable sequence to manually
trigger output hw_fence during the transition. This is required
since on the last autorefresh frame HW will not trigger the output fence.
Change-Id: I6789fc6b51421524f88dcbdd1a063ae947646ae4
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Disable the autorefresh during encoder disable to avoid any
pending frame transfers while disabling. Additionally, handle
frame_done for new autorefresh frames to signal the fences and
proper accounting of pending_kickoff counter.
Change-Id: I8af114972b19ccdf0edab6b4c454ee90b4e8d8cf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.
Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
allocates new resources and CTL_1 is allocated.
sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.
Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
From Kalama, the HW scheduler abstracts the low level
PP_DONE/WB_DONE interrupts and generates a common
CTL_DONE interrupt per hw ctl. This saves the software
the irq latency delays to process the frame complete
operations when multiple encoders are involved.
If supported, this change enables and waits for the
CTL_DONE interrupt instead of PP_DONE and WB_DONE.
This change adds support to wait for CTL_DONE irq in
only command mode panels as we don't drive two WB blocks
with single CTL.
Change-Id: I084d6bfb6a9fb0b48f912fe5787401c460ec5b56
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Add changes to configure the downscale blur hardware block based on
the conifgs set by user-mode. Program the ctl's writeback flush and
active bits when dnsc_blur is enabled. Bind the pingpong block that
feeds pixels to dnsc_blur hw block. Disable the active bits and unbind
the pp block binding during wb disable.
Change-Id: I1961ab437e344b13d0c186c1675a5bf79b84ea74
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a custom cache_enable property in writeback connector to allow
user-mode to control the cache setting on a frame basis. Configure
the hw and activate/deactivate the llcc based on the property. The
custom property is added based on the availability of the system
cache for writeback.
Change-Id: I812b31955eb36c75c33ac279b56502a13f7cdcbf
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a writeback connector property EARLY-FENCE-LINE to give usermode
the control on when to trigger the retire fence. This option is useful
in 2-pass composition, where the writeback triggers the retire-fence
early based on the prog-line which allows primary to start the fetch
before wb transaction is fully completed. This helps to keep the clks
and bw low. WB hardware generates the line-ptr-irq when wb output reaches
the configured prog-line. Retire fence is triggered based on the irq by
default and wb-done handles for cases where line-ptr-irq is missed.
Change-Id: I20867979693dc3447f77da24cd7e88305947fb6d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 9.0, writeback supports a programmable lineptr support, which
generates an interrupt when the configured writeback output height is
reached. Add software support to configure the prog_line and to process
the interrupt.
Change-Id: I3293ad2984c51417e4691c5b11e9c9a010067e1c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Currently, writeback frame-triggers are serialized by default. Add
logic to support the different frame-trigger modes which can be set
through the connector property or encoder debugfs node.
- default: waits for frame(N-1) completion (wb-done-irq) before
configuring current frame(N) and releases the commit-thread on
frame-start (ctl-start-irq)
- posted-start: no previous frame(N-1) completion wait. Configures
frame(N) and releases the commit-thread on frame-start (ctl-start-irq)
- serialize: no previous frame(N-1) completion wait. Configures frame(N)
and releases the commit-thread on frame(N) completion (wb-done-irq)
(wb-done-irq) before configuring the next frame.
Restrict wb posted-start support only for MDSS 9.x+ targets, with older
targets defaulted to default-mode.
Change-Id: Id441378fd79ecbfcfb820da1ff23b14ccfd8e798
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Remove the writeback kickoff_count/frame_count & start/end time
logging. These are redundant counters used for debug purpose. The
pending_retire_fence_cnt and event-logs timestamp can be used for
this purpose. Remove the bypass_irqreg flag as well as its not used.
Change-Id: I1644325afc214f75c76baad615da90c8114836cc
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.
Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
VA minidumps supports to add any allocated variable or data to
minidumps. Add panic notifier and wrapper function to add
sde data to minidump va. Add event log, register log, register dumps,
debug bus and different sde variables and states info to minidump.
Change-Id: If54da0b7067df17877e4da645d82f1705baa3f6d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
While setting up vsync source, display info is used to decide whether
or not watchdog TE should be used. This change passes display info
as a parameter to vsync setup rather than using the encoder's display
info which is not updated in the case of panel dead error.
Change-Id: I928ee2012eec7bf63f4ba3538082bc3e47d5e99d
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Change adds support for splitlink and disables
dsc merge or 3dmerge which is not needed for splitlink.
Change-Id: I77a794d3ea6f53988f493a7af792add81abb22f0
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Calculate line_time once during modeset and allow
each plane to use it instead of calculating for each frame.
It also simplifies the line_time calculation for
command mode display.
Change-Id: I94ce29eec94bfdbee9016fbf93378661ebf79c03
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Avoid irq enable/disable during modeset and trigger
frame as posted start frame. This saves mode_set time
and also avoids unbalanced vblank_irq in this usecase.
Change-Id: I06958da5e52bc2aca0ddc60d2783615f80a839a4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Add precise vblank timestamp support through the DRM framework.
Implement the vblank related hooks to get the vblank count and
timestamp. Use MDSS 8.x, hardware feature that supports logging
of the vsync timestamp counter which can be used to derive the
accurate kernel timestamp. The current ktime would be returned
for older targets to support backward compatibility.
Change-Id: I2d35ed4a643a519e602278b6d16e67ccee16a60b
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
For dedicated CWB pingpong blocks, the overflow irq needs
to be mapped properly to existing IRQ handlers. Add the
needed changes in code.
Change-Id: Ibf398faac60acc027e4577504f9292ac2b72bae2
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Watchdog timer is moving from TOP to INTF. This change adds
support for movement and ensures backwards compatibility.
Vsync select only needs to specify whether or not to use
Timer 0 associated with the interface. It does not need to
select between Timer 0-4.
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Change-Id: I9d89a8cb1ea607e9fc0bdbffa0a6a9acceff7f13
In current implementation qsync min fps is single value.
It is same for all the list of supported dfps list.
Added support for new dt entry dsi-supported-qsync-min-fps-list
corresponding to the fps supported in the dfps list
dsi-supported-dfps-list.
Change-Id: Ifd5309c2f51865a3c0d9fadb65cbcd291b6ef42b
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Commit Ifa100424733 ("disp: msm: sde: delay
encoder disable for clone mode") delays the CWB
encoder disable but it is also skipping the CWB
disable flush. That can cause the underrun on dp
display if it uses the same 3d_merge HW block. This
change reverts the portion of original code and
only delays the last cwb frame done wait. It still
keep the last CWB frame done wait as it is if crtc
is also moving to inactive state.
Change-Id: I3461188a35197f2925899ceea7ef705adf00a398
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change adds 2 vsync delay after changing the timing engine
parameters namely the porches to update the refresh rate.
This ensures that panel vsync is updated as per new timing before
modifying it again.
Change-Id: I5866ea2f6f2e68bc8ce7435c4a5dbe27d8ebdd91
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Adjust the QSYNC line count calculation to compensate for the
idle time, when no transfers are actively taking place.
Change-Id: If91eab25321eea6e6880f07605c5a9c1b7b7ee05
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Vblank refcount can reach out of sync with below case
1. event_thread triggers the vblank_enable
2. commit_thread triggers the modeset
2.a modeset resets the vblank refcount with mode_set
3. event_thread triggers the vblank_disable
Event 2.a resets the vblank refcount and vblank disable
request after 2.a is going to fail. This can be fixed
by avoiding concurrency between mode_set call and vblank
request.
Change-Id: Ibb810ec90e81d63feee443f1c37dd736d5cfac0d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I5358d60634070bdb26059056db884ad4161c073e
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I20785c96569fd07cbd8016d244a7e4c929bfa071
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
With posted start enabled SW no longer waits for ppdone events
unless more than one frame is in queue. HW recovery logic relied
on these waits to know when we recover from a timeout. This
change moves the HW recovery SUCCESS event signalling outside of
the wait to ensure this event is sent to user-space regardless
of the status of posted start.
Change-Id: I8896e8126284b415513499723ccf0155ee8bc6a7
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Make msm_drm into single module and all child driver
registers and unregisters are handled from parent's
register and unregister respectively.
Change-Id: I017513d1de3b6b25dd5543d7fa7741c0bac1740d
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.
Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Reset MDP ctl path and DSI ctl on autorefresh
disable failure. This will enable the hardware
to recover from the hang.
Change-Id: Ia9acc8573c22e0713179ef4f6ef604caacabfadb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change adds logic to align timing engine vsync with panel
tear check if it is supported.
Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add underrun line count information for each underrun.
Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.
Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.
Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
