Commit History

Author SHA1 Message Date
  qctecmdr 125cc02596 Merge "disp: msm: dsi: fix mutiplier frac_bits assignment" 4 years ago
  Satya Rama Aditya Pinapala 7eef141621 disp: msms: dsi: avoid hardcoding pll_lockdet_rate 4 years ago
  Satya Rama Aditya Pinapala ddbd9adaaf disp: msm: dsi: fix mutiplier frac_bits assignment 4 years ago
  Satya Rama Aditya Pinapala b54e355c84 disp: msm: dsi: fix pclk divider calculation 4 years ago
  Satya Rama Aditya Pinapala 0a93edbae6 disp: msm: dsi: rework DSI PLL to be configured within PHY 5 years ago
  Satya Rama Aditya Pinapala fcb453c0b8 disp: msm: dsi: Add support for 5nm C-PHY shadow clock 4 years ago
  Ritesh Kumar ba3d7304f5 disp: pll: Fix cfg1 value when pclk_src_mux parent is updated 4 years ago
  Yuan Zhao 00fd38bec4 disp: msm: pll: add additional dividers for CPHY support 5 years ago
  Satya Rama Aditya Pinapala e0a892dcd5 disp: msm: dsi: fix dsi pll debugfs errors 5 years ago
  Satya Rama Aditya Pinapala 64ee7e84b3 disp: msm: dsi: call pll set rate directly instead of a function pointer cb 5 years ago
  Satya Rama Aditya Pinapala 5694bc2eee disp: msm: dsi: move dsi pll as subnode to dsi PHY 5 years ago