 Satya Rama Aditya Pinapala
|
fcb453c0b8
disp: msm: dsi: Add support for 5nm C-PHY shadow clock
|
4 éve |
 Ritesh Kumar
|
ba3d7304f5
disp: pll: Fix cfg1 value when pclk_src_mux parent is updated
|
4 éve |
 Yuan Zhao
|
00fd38bec4
disp: msm: pll: add additional dividers for CPHY support
|
5 éve |
|
Satya Rama Aditya Pinapala
|
e0a892dcd5
disp: msm: dsi: fix dsi pll debugfs errors
|
5 éve |
|
Satya Rama Aditya Pinapala
|
64ee7e84b3
disp: msm: dsi: call pll set rate directly instead of a function pointer cb
|
5 éve |
|
Satya Rama Aditya Pinapala
|
5694bc2eee
disp: msm: dsi: move dsi pll as subnode to dsi PHY
|
5 éve |
