Currently two RXDMA_STATUS rings are allocated for the station targets
irrespective of whether DBS supported or not. Only one RXDMA_STATUS_RING
being used for non-DBS targets like QCA6750 and WCN6450, hence change
the number of RXDMA_STATUS_RING allocations to 1 for non-DBS targets.
Change-Id: I4f14c8b5cee892979765f776b37d44e99ba2d558
CRs-Fixed: 3578733
Tx completion is processed in napi context, which should follow
napi's max quota, otherwise once process count is over napi quota,
it will trigger napi repoll in kernel, meanwhile by current design,
tx completion hard irq will be enabled when the 1st napi process
finished, in such case 2nd napi process will conflict with repoll process,
finally trigger kernel side napi list crash.
Since napi quota is used in serval cases, while for tx completion
process, we want to process tx completion count as many as possbile
in one cycle, set 64k transmit frames account for 1 napi work unit
to gain max tx kpi.
Change-Id: Ic24f131c90b90b0e118edffcab559ddf31779dcf
CRs-Fixed: 3421368
Increase the number of DP interrupts to 16. The interrupt assignment
table is updated to add new values for different MSI interrupts
available. 9, 10 and 11 MSIs configuration will take the same
configuration as that of 8 MSI. 13, 14 and 15 MSIs configuration
will take the same configuration as that of 12 MSI. New MSI assignment
configuration is introduced for 12 and 16 MSIs.
Change-Id: I82af75b21c793a62fc8f0bd5515e1160b601c0c2
CRs-Fixed: 3209397
Limit the desc pools such that the max ppt entries
do not cross limit for the hardware cookie conversion.
Change-Id: I9149b20bea0d72b466ef8c3e2ee9c0b536ffe24e
CRs-Fixed: 3201792
This is a WAR to match the TX_DESC_POOL size
to maximum number of VDEVs allowed.
Change-Id: I646a67ef2b611bea1ca5a6e2bf781a9454d409ed
CRs-Fixed: 3168359
Enable the 4th Tx. completion ring to save CPU load
Initialization and interrupt handling for 4th completion ring
is done here.
Change-Id: I2db27218a3c3e14d719d012f03454a6a7aa647fe
Currently, we are assigning 9 MSI Vector to DP.
But in some target available MSI Vector are less
because of which they are unable to assign 9 MSI
Vector to DP.
So, to fix the issue reduces MSI requirement for
DP from 9 to 7 and mux DP interrupts.
Change-Id: I48da2d0e8921db3298903a398f981e5b45a60987
CRs-Fixed: 3111170
Repurpose the IPA tx and tx completions rings for
normal use when IPA is disabled either via config
flag or ini.
Change-Id: Ia4b6a89c73d888a217bdef40e3c05435c3bb1bb2
CRs-Fixed: 3059730
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
Some platforms do not support cached descripts for DP Rings.
Add support to set WLAN_CFG_DST_RING_CACHED_DESC to 0 and make
__qdf_nbuf_dma_inv_range as stub if DP_NO_CACHE_DESC_SUPPORT flag is
enabled during compilation.
Change-Id: Ic6b483be25c32f3f3c79b170fb7d7557a232b4ac
CRs-Fixed: 3027649
