Commit Graph

290 Commits

Author SHA1 Message Date
Rahul Sharma
aea055ebc6 disp: msm: dsi: pass DRM_BRIDGE_ATTACH_NO_CONNECTOR during bride attach
Pass the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag when attaching the
bridge so that the bridge driver would not create another
drm connector.

Change-Id: I838bd87c40d0eea3df36187befeb7195fb87d5b3
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
2022-05-17 22:09:43 +05:30
Yahui Wang
6f22c2c636 disp: msm: dsi: parse panel ack disabled property for sim panels
Sim panels are not working well with video mode, parse panel ack
disabled property to fix sim video mode identification issue.

Change-Id: Ife3b533d5a6db97618459dacf1f7ce8d3fc896bf
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
2022-04-01 12:55:29 +08:00
Nilaan Gunabalachandran
e5fcf7f263 disp: msm: add capability to dynamically update the transfer time
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.

It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.

Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-03-21 14:13:32 -04:00
Shamika Joshi
896e10ee2d disp: msm: sde: refactor dsi_display_get_modes function
Refactor the function 'dsi_display_get_modes' to
reduce its complexity.

Change-Id: I1a8ecaa780e5070bac7fa40404677c0a8a5d7cd8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-03-07 17:55:35 -08:00
Narendra Muppalla
daa511cb90 Merge remote-tracking branch 'quic/display-kernel.lnx.5.10' into display-kernel.lnx.5.15
* quic/display-kernel.lnx.5.10:
  disp: msm: sde: avoid error during fal10_veto override enablement
  disp: msm: update copyright description
  disp: msm: sde: configure dest_scaler op_mode for two independent displays
  disp: msm: dp: updated copyright set for 4nm target
  Revert "disp: msm: sde: consider max of actual and default prefill lines"
  disp: msm: sde: Reset backlight scale when HWC is stopped
  disp: msm: dp: avoid duplicate read of link status
  disp: msm: dsi: update vreg_ctrl settings for cape
  disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
  disp: msm: dp: updated register values for 4nm target
  disp: msm: sde: update framedata event handling
  disp: msm: dsi: Add new phy comaptible string for cape
  disp: msm: sde: software override for fal10 in cwb enable
  disp: msm: update cleanup during bind failure in msm_drm_component_init
  disp: msm: sde: dump user input_fence info on spec fence timeout
  disp: msm: sde: add null pointer check for encoder current master
  disp: msm: dsi: enable DMA start window scheduling for broadcast commands
  disp: msm: sde: avoid alignment checks for linear formats
  disp: msm: reset thread priority work on every new run
  disp: msm: sde: send power on event for cont. splash
  disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
  disp: msm: use vzalloc for large allocations
  disp: msm: sde: Add support to limit DSC size to 10k
  disp: msm: sde: add tx wait during DMS for sim panel
  disp: msm: dsi: add check for any queued DSI CMDs before clock force update
  disp: msm: sde: correct pp block allocation during dcwb dither programming
  disp: msm: sde: avoid setting of max vblank count
  disp: msm: sde: add cached lut flag in sde plane
  disp: msm: sde: avoid use after free in msm_lastclose
  disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
  disp: msm: dsi: Support uncompressed rgb101010 format
  disp: msm: sde: update idle_pc_enabled flag for all encoders
  disp: msm: sde: flush esd work before disabling the encoder
  disp: msm: sde: allow qsync update along with modeset
  disp: msm: dp: avoid dp sw reset on disconnect path
  disp: msm: sde: consider max of actual and default prefill lines
  disp: msm: ensure vbif debugbus not in use is disabled
  disp: msm: sde: update cached encoder mask if required
  disp: msm: sde: while timing engine enabling poll for active region
  disp: msm: enable cache flag for dumb buffer
  disp: msm: sde: disable ot limit for cwb
  disp: msm: sde: avoid race condition at vm release
  disp: msm: dsi: set qsync min fps list length to zero
  disp: msm: sde: reset mixers in crtc when ctl datapath switches
  disp: msm: sde: update vm state atomic check for non-primary usecases
  disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled

Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-02-08 16:38:13 -08:00
Yashwanth
107f473e54 disp: msm: update copyright description
This change updates copyright description with correct
license marking as per the guidelines.

Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
2022-02-01 11:29:21 +05:30
GG Hou
e29493c71d disp: msm: avoid using #ifdef for configurations
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.

Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.

The differences are as follows:
	1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
		module (=m) or built-in (=y).
	2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
		built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
		Use this only when you're certain you want to do the same thing
		when the config is set to module or is disabled.

Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
2022-01-17 10:10:04 +08:00
Ritesh Kumar
fd2dc5be06 disp: msm: dsi: enable DMA start window scheduling for broadcast commands
As per the HW requirements it is highly recommended to use DMA start window
to trigger broadcast commands. If not used then it can result in a hardware
hang with the DSI controllers going out of sync. This behavior is even more
prominent in cases of higher refresh rates.

Currently, reset_trigger_controls is called as part of next command.
Due to this, when unicast command is sent after broadcast command,
reset_trigger_controls does not get called for slave controller,
leading to issues.

As part of this change, DMA start window scheduling is enabled as default
for broadcast commands and reset_trigger_controls is done as part of
post_cmd_transfer operations.

Change-Id: I2402214ed79b376d102b88d4f7e6a06fcb5712d3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
2022-01-12 09:57:42 +05:30
Veera Sundaram Sankaran
56862f8118 disp: msm: use pm_runtime_resume_and_get instead of pm_runtime_get_sync
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.

Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:28:41 -08:00
Satya Rama Aditya Pinapala
c5c2af4297 disp: msm: dsi: add check for any queued DSI CMDs before clock force update
During a force update of DSI clocks, the state of the byte and pclks are
toggled irrespective of the ref-count. This in addition with ASYNC
command wait can result in interrupt storm, if and when the clocks are
being toggled a previous command that was triggered using the ASYNC
wait flag fires an ISR. The interrupt status doesn't get cleared if
the ISR is being serviced with the clocks are off.

The change adds a check for pending queued commands before any force
update of DSI clocks.

Change-Id: I4ca60d0ad43767791255f00c9af8e99e74786097
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
2021-12-29 00:03:35 -08:00
Jeykumar Sankaran
cf39b00660 Merge branch 'display-kernel.lnx.5.10' into display-kernel.lnx.1.0
Change-Id: I5d2b08380b6b0eb09492b950fb38cd9a0b3196c1
2021-12-08 12:37:35 -08:00
Bruce Hoo
c9d1adc535 disp: msm: dsi: adapt MIPI_DSI_* flags for multiple SIs
Commit bf0d220 ("disp: msm: dsi: add _NO_ to MIPI_DSI_* flags
disabling features") update names of DSI flags to follow upstream
convention. Purpose of the name change is to more clearly indicate
what is not supported when the flag is set.
This change puts macros around MIPI_DSI_* flags to adapt the name change
of flags for kernel version 5.10 and version 5.15..

Change-Id: I1c9a8da3819a6b641ca9b6d81191bc944913b49e
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
2021-11-30 10:57:13 +08:00
Kashish Jain
c079b51c81 disp: msm: dsi: allocate priv info and bit clk list per fps
Currently, in dsi_display_get_modes, priv_info, rates,
front_porches and pixel_clks_khz memory is allocated for each
timing node and the same memory is copied for each supported fps.
The values of front porches calculated to maintain constant fps for
each bit clk rate gets overwritten with the values for last fps in
the dfps list. But the values of front porches should be different
in case where DFPS and dynamic clock are both supported either by
vfp approach or hfp approach. To fix this, allocate memory
separately for each fps.

Change-Id: Ibf753aa8cca8d77b02b20785b5435f1aba05106e
Signed-off-by: Kashish Jain <kashjain@codeaurora.org>
2021-11-21 23:51:10 -08:00
Ritesh Kumar
986c7b1028 disp: msm: dsi: Logging Improvement in dsi driver
This change adds additional logs in dsi driver for
easy debugging of issues related to command transfer.

Change-Id: Ica784bed6c360b2760d6606d625837e23a22410c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-11-05 02:08:17 -07:00
qctecmdr
24057ec69c Merge "disp: msm: dsi: implement ESD recovery cleanup" 2021-11-02 14:52:24 -07:00
qctecmdr
d6d5bcebe3 Merge "disp: msm: dsi: avoid updating bitclk when dyn clk is disabled" 2021-10-22 04:30:39 -07:00
Satya Rama Aditya Pinapala
1317b11bc2 disp: msm: dsi: implement ESD recovery cleanup
After an ESD failure, the PHY lanes and controller can be stuck in
an unknown state. This can result in interrupt storms and watchdog
failures, if these error states are not handled correctly. The following
change implements the below mechanism to avoid failures.

1) Disable error interrupts during an ESD reg read, which are re-enabled once
ESD check is successful.
2) On ESD failure, before turning off LP clocks, reset the PHY lanes and DSI
controller.
3) After the HS clocks are turned off, issue a PHY hard reset.
4) Before enabling/disabling error interrupts, clear the error status registers
as they are not cleared as part of controller reset.

Change-Id: If10e4edf095a334a9416d109ec4b1401d1a84505
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-10-21 16:25:44 -07:00
qctecmdr
5f25adc693 Merge "disp: msm: dsi: add const qualifer for device node in get_named_gpio" 2021-10-20 09:37:40 -07:00
qctecmdr
a6400b2c81 Merge "disp: msm: dsi: remove check for reset gpio config in ext bridge mode" 2021-10-19 22:14:08 -07:00
Bruce Hoo
bf0d2209a0 disp: msm: dsi: add _NO_ to MIPI_DSI_* flags disabling features
Update names of DSI flags to follow upstream convention. Purpose of
the name change is to more clearly indicate what is not supported
when the flag is set.

Change-Id: Ifd62610c4dfebcbbccb0fb2046a7c453e39c9107
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2021-10-15 17:26:53 -07:00
Jeykumar Sankaran
425df29bb6 disp: msm: sde: avoid checking debugfs_create_bool return value
Adapt 5.15 kernel upstream change to return void for debugfs_create_bool.

Change-Id: I9f2ece04dddeba8f43d603fbb62517ea5fb48e7c
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2021-10-15 17:25:51 -07:00
qctecmdr
e967184207 Merge "disp: msm: dsi: change allocation to kvzalloc" 2021-10-13 20:40:23 -07:00
Shashank Babu Chinta Venkata
e13444d9ac disp: msm: dsi: avoid updating bitclk when dyn clk is disabled
Currently the bit clk rate is overridden by cached clock rate
even in dynamic clock disabled usecase where it is not configured.
Avoid this override by retaining calculated bit clock rate for respective
mode in such usecase.

Change-Id: Ib159219fd50ab977edb8332c83bc8b34aee2dc0f
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
2021-10-13 14:08:44 -07:00
Shashank Babu Chinta Venkata
b14335c311 disp: msm: dsi: change allocation to kvzalloc
Alter allocation method from kzalloc to kvzalloc since virtually
contiguous allocation should suffice requirement. This will avoid
unnecessary invocation of OOO handlers.

Change-Id: I8291ddae08f6427478cdd9b88d6148e02d7ab002
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
2021-10-12 11:34:51 -07:00
qctecmdr
493cb4b048 Merge "disp: msm: dsi: flush workers during pre-release" 2021-10-11 13:32:47 -07:00
Yu Wu
1b6075d5c1 disp: msm: dsi: remove check for reset gpio config in ext bridge mode
When validating panel resource, no need to check reset gpio if using
ext bridge mode.

Change-Id: Id0df84b9e0d8b10f4dd6851d5b3ab31b220f8622
Signed-off-by: Yu Wu <zwy@codeaurora.org>
2021-10-10 22:58:58 -07:00
Steve Cohen
bd01b504a5 disp: msm: dsi: flush workers during pre-release
Wait for asynchronous DSI DCS command transfers to complete
before disabling DSI interrupts during pre-release. This is
required to resolve a race condition where dsi worker threads
can trigger HW access while a VM lend/release is occurring on
the CRTC commit thread.

Change-Id: Ia1f153a2cd008c617dba274473e7678b01a38d29
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-10-07 17:24:57 -04:00
Satya Rama Aditya Pinapala
bcd04f60da disp: msm: dsi: swap DSI timing engine programming and ROI cmd tx
The ROI commands are sent with an asynchronous command transfer wait.
If the queued CMD DMA wait for done gets scheduled before the DSI
controller timing engine programming, the later will be blocked waiting
on the ctrl_lock, which was acquired by the queued DMA wait for done work.
This effectively negates any advantage of having the async wait flag for
ROI commands blocking the main commit thread.

The change swaps this order to ensure that such a scenario never happens.

Change-Id: I8a971c0c7733eea3d435b637ca41b34fa60adfc1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-10-07 10:58:32 -07:00
Ping Li
629228c353 disp: msm: sde: add new support for digital dimming
Add new properties to support dynamically turning on and off digital
dimming and setting new minimum backlight.

Change-Id: I3b94190877d556768ba2c92ec59432dec44de0de
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-10-05 21:15:09 -07:00
qctecmdr
c0dad8fa08 Merge "disp: msm: dsi: add qsync min fps val in dsi display mode priv info" 2021-09-17 03:46:41 -07:00
Yashwanth
6619470eb6 disp: msm: dsi: add qsync min fps val in dsi display mode priv info
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.

Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-09-15 12:09:35 +05:30
qctecmdr
16d516dc35 Merge "disp: msm: dsi: add support for setting backlight min level" 2021-09-10 14:04:54 -07:00
Yahui Wang
23582c4de3 disp: msm: dsi: add support for setting backlight min level
Current display driver can't support kernel dts property
qcom,mdss-dsi-bl-min-level to adjust backlight min level,
so adding this change to make it work well if user wants to
increase the backlight min level of display panel.

Change-Id: Iac74ee44aafac88548ceba6b221d13251dc3d5ef
Signed-off-by: Yahui Wang <yahuiw@codeaurora.org>
2021-09-10 15:08:34 +08:00
Steve Cohen
3c40c5c903 disp: msm: dsi: allow CMD engine enable for cont-splash
Issuing a DSI command transfer while in continuous splash can
disable the CMD engine since no enable call has taken place.
Ignore updating the engine during display enable/disable paths
only for trusted VM and allow it for continuous splash.

Change-Id: I250df6a78af5558ad1e03a3931d11fd8d13e4555
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-26 12:39:50 -04:00
Steve Cohen
1416e72e62 Revert "disp: msm: dsi: allow cmd-engine enable/disable HW op at all times"
This reverts commit 65f3cc37a4.

This change breaks TUI use-cases by allowing CMD engine to be
disabled on trusted VM without primary VM having knowledge of
this HW update.

Change-Id: Ieb67dc841299a149e9f1028fd8f98bd857f1f711
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-26 12:37:45 -04:00
Steve Cohen
b57a445cf4 Revert "disp: msm: dsi: skip DSI disable operations in trusted VM"
This reverts commit 61518d4f5f.

This change corrupts the DSI engine state machine which expects
all the state tracking updates from the calls that are now being
skipped.

Change-Id: I506ecbd98cc771950b17212a2702e7dde81fe539
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-26 12:35:38 -04:00
Steve Cohen
61518d4f5f disp: msm: dsi: skip DSI disable operations in trusted VM
Secondary VM will do a disable commit when transferring HW
ownership back to primary. This will end up disabling the CMD
engine before releasing HW back to primary VM. Primary is
unaware that the engine has been disabled and ends up in a
bad state until it gets re-enabled.

This issue was introduced by: commit 65f3cc3 (disp: msm: dsi:
allow cmd-engine enable/disable HW op at all times).

Fix the issue by ensuring CMD engine does not get turned off
in the display disable path for trusted VM.

Change-Id: I1638a181d136e18a836c3ba08daee1c5fcaa9de3
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-20 19:39:48 -04:00
qctecmdr
d55bc8d204 Merge "disp: msm: dsi: acquire panel lock for command transfer through debugfs" 2021-08-15 18:31:11 -07:00
qctecmdr
c9fb272a73 Merge "disp: msm: dsi: allow cmd-engine enable/disable HW op at all times" 2021-08-13 20:50:45 -07:00
Satya Rama Aditya Pinapala
adfbc98df7 disp: msm: dsi: acquire panel lock for command transfer through debugfs
To ensure that no other command transfer is in progress, during DSI
TX operation through debugfs, panel lock needs to be acquired.

Change-Id: I8d3871e32277840867d9494720e77df3566e30d3
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-08-13 13:18:44 -07:00
Yashwanth
64b732f335 disp: msm: add qsync refresh rate support per mode
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.

Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-05 15:37:20 +05:30
qctecmdr
f7e7964840 Merge "disp:msm:sde: correct the brightness bound check" 2021-07-29 19:41:43 -07:00
Amine Najahi
e3c76571dc disp: msm: dsi: fix RFI mode set detection
Currently mode fixup function is called multiple times
in the same commit. This causes invalid combination of
DSI mode flags to be set when there is an RFI change
with proch compensation feature enabled.

This change modifies the mode switch condition for DMS
to compare internal dsi mode and flags and fixes the
dynamic clock change detection by using a single variable.

Change-Id: Iaf9c8ca7c6a27f26aefead399bc93fbbb02b404b
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 07:43:27 -07:00
Amine Najahi
1881acdb2b disp: msm: dsi: publish RFI porch values for rate matching calculation
Currently when RFI is used on a video mode panel the horizontal or
vertical front porch values can be adjusted to maintain a constant FPS.
When this feature is enabled, driver is not propagating the new
htotal or vtotal values to usermode for accurate BW and MDP clock
calculation, which may lead to underrun in some usecase.

This change publishes beforehand all the RFI related timing
such as compensation type, hfp or vfp and clock values for
each mode for accurate BW and clock calculation.

Change-Id: Ib89c5e318fe978b0ae2215dedc430e057a9a81b9
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 10:35:27 -04:00
Ping Li
b7506f0222 disp:msm:sde: correct the brightness bound check
The brightness value from backlight device is OS brightness, not panel
backlight value. This change corrects the brightness bound check to
check against the OS brightness max value instead of panel backlight max
value. This change also move the bound check in dsi display to make sure
the max backlight value send to panel is within the expected range.

Change-Id: Ic9e3ba69700ae4c0e950cb665837a1f0a1317b26
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-07-28 12:32:45 -07:00
Satya Rama Aditya Pinapala
095f5dd58a disp: msm: dsi: prepare resources for cmd transfer at the start of the cmd packet
For batched commands, prepare resources at the start of the command packet and not for the
command with LAST_COMMAND flag set.

Change-Id: Ibbb0d1d1acd4ddeebd07bf9dd6ea1a949edd8d02
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-07-22 10:37:58 -07:00
Steve Cohen
65f3cc37a4 disp: msm: dsi: allow cmd-engine enable/disable HW op at all times
In cases of continuous splash, when command engine is
enabled/disabled as part of commands that are sent before
continuous splash config is called the HW op will disable the
command engine by the end of the command transfer. As part of
continuous splash handoff, the command engine enable call skips
the hardware operation to actually set the CMD_ENGINE_EN bit
as it is guarded by the skip op flag.

With the current change, we allow the HW op to take place, despite
continuous splash being enabled. This way, the HW will always maintain
the correct state pre and post continuous splash handoff.

Change-Id: Id32ebf6f0d7eac46c118b701c138fcf6b9b10318
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-07-09 12:22:17 -07:00
Yashwanth
981508c215 disp: msm: dsi: use dynamic memory allocation for dsi_display_mode_priv_info variable
This change adds dynamic memory allocation/free for struct
dsi_display_mode_priv_info variable as it is only temporary
variable to find mode and also reduces stack consumption in
dsi_display_find_mode function.

Change-Id: I2116757f11614f9e8406ddfdb08b5a4b6292cfea
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-07-08 22:13:22 -07:00
qctecmdr
bb76263607 Merge "disp: msm: dsi: add warning message for rx debugfs commands during suspend" 2021-06-30 21:31:16 -07:00
Satya Rama Aditya Pinapala
38a94cc558 disp: msm: dsi: add warning message for rx debugfs commands during suspend
Change adds a check to return a warning rather than an error during a
debugfs read command transfer while the device is suspended.

Change-Id: If65ba642f73f4c8e6b9609bbed6e376ef7836145
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-06-30 15:44:28 -07:00