1. Changes to get correct write address in hal_get_window_address_5332.
2. Fix for monitor init crash - Added dummy entries to match the
ring_id.
Change-Id: If59b1c231d4595a95e7c1f02de1dbe0ce27a8805
CRs-Fixed: 3268933
When FW was enabling WOW, a ring HP update interrupt is seen
which led to fw crash.
This change records any PCI writes that went through during
runtime suspend from host.
Change-Id: I3c44760ebaf49a131b483813522fe3e451957215
CRs-Fixed: 3280166
For Beryllium LMAC rings, hal_get_srng_ring_id() provides the ring IDs
separately per each LMAC only if that LMAC ring is a destination ring
(This is done to use a common source ring for the DMAC rings).
But the ring IDs for LMAC source rings like DIR_BUF_RX_SRC_DMA_RING are not
being provided separately per LMAC. As a result, these ring IDs in
split-PHY mode are colliding for the 2 LMACs.
Fix this by doing the following.
- Mark the DMAC common rings within the LMAC rings.
- Provide ring ID separately per each LMAC if the ring is an LMAC ring
but not a DMAC common ring.
Change-Id: Ifdae085b5784a03763abfc4edb42d94593e3ea21
CRs-Fixed: 3282702
Hal layer changes to handle Umac post reset
and post reset complete events from firmware.
Change-Id: Ib25427930aab25650731c87b38e2ef7e47ae98d9
CRs-Fixed: 3267222
Add support to track the high watermark for the number
of entries which are used at any given instant. This helps
in identifying if the ring size is sufficient or is being
full for certain use-cases.
Change-Id: Id3ffa52c653696699fbcfbb556a815d5f7908863
CRs-Fixed: 3235115
Move the function attribute to common file so that the
parsing issue due to unreferenced tcl_data_cmd can be
fixed on other targets also.
Change-Id: I40a7196926061e8d232f0f070c0ed045dafd97e2
CRs-Fixed: 3228562
With restructuring in HIF runtime PM module, modules are
required to register with the HIF runtime PM module. Also,
changes are done in functions of allowing and preventing
runtime PM suspend as part of restructuring.
This change registers DP, HTC and HAL internal modules
with runtime PM module and update HIF runtime PM function
calls with the restructured code of HIF runtime PM module.
Change-Id: I8899a1d3b92a90a05c5eaf4df7609f4008f739f8
CRs-Fixed: 3169372
For reo_cmd ring, in current implementation, we call hal_srng_access_end
in case a descriptor is not available before baling out. This may cause
a write to the shadow register for the reo_cmd ring. In case we are in
the middle of WOW, this can be problematic.
Modify existing implementation to use hal_srng_access_end_reap, which
will not schedule a write to the register and simply return.
Change-Id: Ifb83d904e39b3d749522cd246a5ab3fe51a3104e
CRs-Fixed: 3194289
Shadow config v2 can support max of 36 shadow
registers only. For KIWI target, there are 40
shadow registers supported.
Hence add support to send shadow config v3
for KIWI.
Change-Id: If57e6597397da3e239f25a6c0cc24f8fd37dcdf1
CRs-Fixed: 3167758
Flush and invalidation of descriptor memory at allocation is helping
to avoid NULL descriptors issues in TX and RX path.
Change-Id: Ifcdb65df01365e7ec0b0be59d8b4bf862d90943d
CRs-Fixed: 3180696
In WIN BE chipsets, replace the REO tid
queue programming in FW via WMI with writing to a
Host managed table shared by HW and SW. REO HW will
pick the tid queue address from the table indexed by
peer id and tid number.
Change-Id: I8107ca5116425538329b11ae3519f02b32573bac
For Kiwi, if UMAC force wake is enabled, HIF window register
support is needed as well. currently hal_soc->init_phase just be
true for a very short periord, this lead to hif_force_wake_request
is called frequently when configure register during initialization,
this is not necessary as pld and device is not in power collapse
state during this period.
Enable HIF window register and increase init_phase true period
Change-Id: I0b5394bbc1ca73d20b2fcabbf2a261e6f8335626
CRs-Fixed: 3097991
Use the tracepoints to trace delayed register write, ce
tasklet scheduling latency, tx, and rx packets.
Change-Id: I63a89276177a9d0466dcb0c831eeb8e938a2bf79
CRs-Fixed: 3081870
In hal_delayed_reg_write change the order of
hal_is_reg_write_tput_level_high and pld_is_device_awake check. This
ensures that throughput level is checked before checking for device
wake state. This is beneficial in saving CPU cycles in high throughput
scenarios.
Change-Id: I23d0bde46779df9dca4388bf67c9395999274f3a
CRs-Fixed: 3078096
Added an API to do a batch invalidation of REO descs
saw an improvement of 40 to 45 Mbps.
Note: this change is applicable only for cached
descriptors
PINE with Default driver: 3189 @ 100% core-3
PINE with skb prefetch: 3469 @ 100% core-3
PINE with skb pre + batch inv: 3506 @ 100% core-3
Change-Id: Ic2cf294972acfe5765448a18bed7e903562836c3
Currently reg work is being cancelled in deinit path,
cancel work will remove all the pending work items
and wait for completion of current executing work.
But in reg work case even pending work items has to be
executed because we don't want to skip HP/TP values update.
To avoid this make sure all the pending reg work items are
flushed then disable the work for further queueing.
Change-Id: I2ba1e26cf41fb3b0c33ec584c56525cbfac94d8f
CRs-Fixed: 3065038
Add API to get dp peer authorize state.
Also modify dp_tx_get_rbm_id_li to update rbm for IPA offload
scenario
Change-Id: I0f8cca4623a1c3b840f336aa6d67740951cb6700
This FEATURE_HAL_DELAYED_REG_WRITE_V2 was added to fix the
Audio jank issue, but it could not resolve it completely,
so that was later fixed by existing delayed reg write
support with the help of SMP2P messages to communicate
with FW regarding PCIe link status. This code is not being
used, so removing it and cleaning up the redundant code.
Change-Id: Iada088e72a76b4c071c8a80ee945f36ac959670e
CRs-Fixed: 3056475
Initialize the last_desc_cleared pointer to -1 not 0, and
also fix the check it should always behind tp.
Change-Id: I281e066d45a99ac99d4f3c4e0bcc3f65f14bb589
CRs-Fixed: 2987029
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
hal_reg_write_need_delay is invoked immediately after
q_elem->valid check. The first two instructions in
hal_reg_write_need_delay could be in the CPU instruction
pipeline which could result in possible loading and
dereferencing of NULL srng from an invalid q_elem.
Fix is to invoke hal_reg_write_need_delay just before
hal_process_reg_write_q_elem and also add NULL checks
to avoid the srng NULL pointer dereference.
Change-Id: I2de50b1e78782e3c91a9cb4477f28d91f9c29439
CRs-Fixed: 2973257
Return LMAC start id also as part of hal_get_meminfo API.
This field is added to hal_mem_info struct.
Change-Id: I013d357cf4337702c06a91ed15e8337469865270
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.
This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).
Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
Introduce intermediate EP voting state during this transition state
access the votes only if direct writes are not possible.
Change-Id: Ib4522aef2209b4797100ca84e4e230a00e14b654
CRs-Fixed: 2954903
Even though HP/TP updates are posted writes at CPU level, they
are getting blocked until soc comes out retention which is hogging
CPU.
To avoid this if EP is in low power state update HP/TP writes from
delayed work context. In delayed work vote for EP awake wait till it
comes out low power state and then proceed to HP/TP update.
Change-Id: I61d5795f58f25f850b5a9ad4d30e3181dba23713
CRs-Fixed: 2913495
Add support to update CE srngs HP/TP in delayed manner
for QCA6750 target. This avoids busy wait in register update.
Change-Id: Id825a6fdf709187765ff823cb3015db21a024af3
CRs-Fixed: 2894094
For the minidump feature, the wlan_minidump_remove function
definition is modified. So, update the function parameters
accordingly at all instances of the wlan_minidump_remove function.
Change-Id: I5a346f6cdf423ece02fb08d68e4422251af54876
CRs-Fixed: 2860435
Enable force wake recipe feature DEVICE_FORCE_WAKE_ENABLE
and disable the generic shadow register write feature
GENERIC_SHADOW_REGISTER_ACCESS_ENABLE.
Force wake recipe will be used to write to the REO remap
control registers by waking up the UMAC instead of using
shadow register writes.
Assert soc wake reg and poll on the scratch reg to check
if UMAC is awake.
Enable HIF_REG_WINDOW_SUPPORT to enable windowed reg
read/write in HIF layer.
Change-Id: Ib696e27e19a07c0084c097b95b7780b56e643c8b
CRs-Fixed: 2850590
Add delayed SRNG register writes support for Tx Ring, also add
dedicated workqueue to do the delayed Tx SRNG register writes.
Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b
CRs-Fixed: 2868989
WLAN HW can still access the IPA tx doorbell address post
disable pipes if there are any pending tx completions which
could result in a NOC error.
Fix is to reset the WBM2SW ring HP addr to shadow addr in
DDR before pipes are disabled.
Change-Id: I52900eb34530388487923a887354ef8839d8c728
CRs-Fixed: 2846421
Currently, we decrement active_work_cnt in a while loop in delayed
register worker and later on make a "allow_l1" call to enable L1ss.
The bus suspend routine depends on the value of active_work_cnt to
determine if any register writes are pending. In case there are, bus
suspend is rejected.
As a result its possible that when bus suspend happens, the
delayed worker while processing the last remaining enqueued
write, makes the active_work_cnt to 0. This will allow the bus suspend
routine to continue to disable the bus, even before the
delayed-reg-worker has called allow_l1 and run to completion. This may
lead to a NOC error while calling "allow_l1" API from
delayed-reg-worker.
Hence, move the decrement of active_work_cnt to the very end in
hal_reg_write_work function.
Change-Id: Iec602f97c953df1c6a018310fd02ab458547ce3a
CRs-fixed: 2813733
This change fixed compilation error about implicit-fallthrough and
pointer to in cast.
Change-Id: Iea2c25d97d8a039ed0f8083078427a8f8de70cd1
CRs-Fixed: 2814658
Delayed register write work needs to be flushed before bus suspend to
make sure there are on pending writes after driver's bus suspend routine
exits. In case delayed work context is not able to finish before the bus
(PCI) is suspended (DRV), it may lead to a NOC error.
Change-Id: I40cbcec5d23ddd75ec87aed69ac45d95510fa880
CRs-Fixed: 2813733
Add apis to map generic registers to shadow region. Existing
logic includes mapping only srng based regs to the shadow
region.
Add support to map REO control regs and WBM2SW2 rel
ring HP reg address to the shadow region in case the direct
reg writes in IPA enable/disable autonomy fail due to UMAC
block being in a power collapsed state.
Shadow reg mapping for these regs is provided to FW during
init. Add stat shadow_reg_write_fail to track shadow reg
write failure and shadow_reg_write_succ to track successful
shadow writes.
Change-Id: I04790765a3de80047689657e2cad0b73123440b9
CRs-Fixed: 2790321
If reo_dst_ctrl register writing failed, this is a fatal error for
IPA pipe going to down case as RX frames will still be routed to
IPA rings then hit NOC error. retry register writing to see any
chance to write successfully, if fail always, trigger SSR or panic.
Change-Id: I3c03faa28e6cc93f396944579a360d5405c8138e
CRs-Fixed: 2774789
The logging macros implicitly takes care of embedding function name
in the log, hence there is no need to include __func__ again.
Getting rid of redundant __func__ reduces driver memory footprint.
Change-Id: I6b5beea990e78486e1e5aab5a8df5fc2f1e5ab51
CRs-Fixed: 2774457
