While altering ESD check to te_signal_check, return error
as this option is no longer allowed and should not
change ESD mode.
Change-Id: I32a9a47aba4e41451ba3d8ffc1eeba41d9f547d7
Signed-off-by: Samantha Tran <samtran@codeaurora.com>
This change adds allowed_dsc_reservation_switch to determine if
dsc seamless switch is supported for DP. Also, based on the
flag, it determines and populates the required number of
available resources for DP.
Change-Id: I9cd7219a50d352369c5bc8386ce7dc25c30b80b6
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Mode information apart from the fields in
drm_mode_modeinfo that can trigger a modeset like
dsc-nondsc, video-cmd are defined in sub mode.
For each mode in connector->modes there can be
multiple submodes.
Change-Id: Ib8697d3fa4ea5261d9ac4943b1a4149e22c4da2f
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
This change adds logic to determine dsc switch based on
the connector property "CONNECTOR_PROP_DSC_MODE" and
performs seamless DSC switch if there is any change in
DSC configuration. The connector property is populated
in msm_sub_mode based on which suitable mode is selected.
Change-Id: Ifc4931f16dfb814781bc1d72b103e09103e6bfee
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Change adds more panel and display information during the DSI
display bind.
Change-Id: I3571244501149a95ea4f6ab0e496112199f7bbde
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For simulation panels read commands need to be avoided. The change
also adds and substitues sim panel check with a new is_sim_panel API.
Change-Id: Idafdad8a852cad87d97bbc64e9c7cb82460e25b7
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Avoid registering for te interrupts to check te status
for ESD detection during commit failure path.
Change-Id: I447473f7c32a396f72d838c68287bed0eda64b20
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Update the dump_mem pointer offset while storing the debugbus
data for the second DSI to avoid overwriting to same memory.
As part of the change, register the DSI ctrl with sde_dbg from
ctrl_init directly, instead of debugfs_init to avoid code replication.
Change-Id: I4089f3038ffa89136eaea956d27270f638a99043
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The change ensures that during a Trusted UI case, configuring
and toggling the DSI PHY PLL is skipped.
Change-Id: I3246c8e5f01d47ac6fd58098f859ef8436a762bf
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
In dumping display registers, physical address will be appended after
each block name. This is to support register compare between kernel
and UEFI.
Change-Id: Ic20d3e2bd4c95aa7c71c4b646a149f7e83ad731a
Signed-off-by: Yu Wu <zwy@codeaurora.org>
The change ensures that for the slave PLL the PHY post divider
always needs to be configured to 0x1.
Change-Id: I481b4fd206d9f8e05af724687beb2e89fd6c2ea6
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Currently, the demura parsing has info logs, this change reduces
the log level to debug for all the parsing logs.
Change-Id: Icd9e73a7788cb01e09068e4d0957bc1e11a329da
Signed-off-by: Santosh Kumar Aenugu <santoshkumar@codeaurora.org>
Define 64 bit variables as unsigned long long to ensure
8 bytes in 32 bit builds.
Change-Id: I723ae0c4ba6a0de07c92d14eeef95bde095c8e3d
Signed-off-by: Venkata Prahlad Valluru <vvalluru@codeaurora.org>
Add full mode information to dump panel info debugFS
node to allow for additional verification.
Change-Id: Ie56f3b44a8b35075d78575def1469b12bed60252
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
For simulation panels, GPIOS are not needed for panel bootup.
This change handles GPIO parsing, toggle sequences in
simulation panels.
Change-Id: I0a3f03d1958ffe9079a7d9fef3f412e2445b0b9b
Signed-off-by: Santosh Kumar Aenugu <santoshkumar@codeaurora.org>
Currently on video mode panel, when the RFI bit clock
rate is set back to the default rate, the driver is not
detecting that a VRR operation is necessary due to
unchanged porches value.
This change is forcing a VRR update on video mode panel
whenever the RFI bit clock rate is changed.
Change-Id: I16520b6ca1909f878bff1bb97472b15fe2a3d13b
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Currently, on a video mode panel when a mode switch occurs after the RFI
bit clock rate has been changed, the driver fails to find the new mode
in the list of panel modes due to different porches value between
the adjusted mode and the default panel mode.
This change removes the front and back porch value check from mode
matching function when dynamic bit clock and maintain constant FPS
features are enabled.
Change-Id: If267a4f732fea2c7d84c8bb3d5650f3e93722ec4
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
The change adds a check for DSI controller and PHY resources during the
DSI display probe. The validation now only checks for the availabilty
of the resources without increasing the refcount of the controller or
PHY till an exact match is found after the device tree is parsed.
Change-Id: I96a5022a8ab5f55271e0df36675037b597e1ec85
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Some panels require a fixed step rate for a particular mode.
This change allows DSI panels to specify a single supported
step rate for each nominal fps rate which SDE will enforce
during atomic check of AVR parameters.
Change-Id: I049415449bc88ccd396fced16d4534251eac3a06
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change expands on the checks comparing different dsi modes.
Previously, only h and v active and refresh rate were checked to
decide if a matching mode is found. Now the check will include
all h and v components in dsi_mode_info.
Change-Id: I6a4ca3456138c38615fbd5c50dfd9658cc3a2119
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Request for display in firmware only if no display enabled form
the UEFI.
In the targets supporting dual DSI display having both displays
DT nodes part of the connector list, if only one display is
enabled from the UEFI, then the driver requests for display
in firmware for the second display. Getting the display panel node
from firmware is time taking process, and it can take up to
ten seconds. This causes a delay in adding the component for the second
display, resulting in a delay in bind calls for components of the
msm drm driver.
Change-Id: Ic0aa5ca890fc874d38d3e7eef745f2942e12f9bc
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
In CPHY, packet header and checksum is sent twice and SYNC is
sent in between two headers. So, increase packet overhead used
in clock calculation to 15 bytes. Packet Header: 8 bytes,
CRC: 4 bytes, SYNC: 2 bytes and dcs command: 1 byte.
Change-Id: I7a1160cbb57ba4f1faeb4b36a16c322e6069d58f
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Change fixes issues with the recalculation and DSI PHY PLL
toggle sequences while using continuous splash.
Change-Id: I6e63dd176e3ad5160b4df9f2da6d981951b696ab
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The boot_disp_en flag for secondary display is getting enabled
all the time, even if its boot_param string is empty.
Correct the boot display name parsing from boot_param string
to fix this issue.
Change-Id: Ica1465611f592b22518061987571919838914891
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
