Ideally in MLO, Rx buffers should be routed to error
rings of the SOC which owns the RX buffer or link desc
incase of any error or fragment
But in case of HW issue if the packets are routed to
partner soc. Handle gracefully instead of assert
Change-Id: Ia56188808dfd034e960e1c1345de8f760e4b05f1
CRs-Fixed: 3327959
The following change introduced new misspellings of "address", so fix
them.
- Change-Id Idc9eec559b71ebb2dc39ea1d648a384ea0eb9559
qcacmn: Fetch the reo qdesc from the peer
Change-Id: I29c71972d46a06c24fef2ed90d2a4226cc2ac654
CRs-Fixed: 3319356
When compact rx tlv feature is enabled fetch the
reo qdesc from the peer instead of rx pkt tlvs.
Change-Id: Idc9eec559b71ebb2dc39ea1d648a384ea0eb9559
CRs-Fixed: 3311270
Adding compact tlv support for QCN9224, As part of this change
Rx tlv size will reduce from 384 bytes to 128 bytes.
Change-Id: I3f42a781e42b2e696a5b25d9c5f333c8cc83b7fe
CRs-Fixed: 3274152
Add HW, SW and nbuf prefetch support in Berryllium, this will
ensure we have prefetched the HW desc, SW desc and nbuf by
the time we are in the 3rd iteration of the dp_rx_be_process
first loop.
CRs-Fixed: 3218647
Change-Id: I27d371c5d1c9a37d61e4fc00d5eb03609fad589c
prefetch certain nbuf fields and nbuf data fields, this
will ensure these fields are in cacheline by the next
iteration of the rx processing loop.
CRs-Fixed: 3146589
Change-Id: I69fd9a7800c7e881cf6635f329343195d19735c5
In WIN BE chipsets, replace the REO tid
queue programming in FW via WMI with writing to a
Host managed table shared by HW and SW. REO HW will
pick the tid queue address from the table indexed by
peer id and tid number.
Change-Id: I8107ca5116425538329b11ae3519f02b32573bac
Multicast support for MLO
1. Following functions are newly added.
dp_rx_igmp_handler()
dp_tx_mlo_mcast_handler_be()
dp_rx_mlo_mcast_handler_be()
dp_mlo_get_mcast_primary_vdev()
Change-Id: If215f843369e6e2621ef302b924e524c86f0d30b
Use chip ID and destination peer to determine the target soc
and partner vdev for Intra-BSS in MLO case.
Change-Id: I709c52e74426c5e81b50c8063cad7669c0e7002d
Rx patch changes for multichip MLO
1. Create ini for rx ring mask for each chip
2. Configure hash based routing for each chip based
on lmac_peer_id_msb
3. Peer setup changes to configure lmac_peer_id_msb
to enable hash based routing
4. Rx Replenish changes to provide buffers back to owner
SOC of reo ring
Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
Take care of the MLO peer bit indication to be
concatenated with peer_id to access the peer map
object.
Change-Id: Ia603a728101e83829a8906d1b847f42389e78ca6
CRs-Fixed: 3039326
In Beryllium the HW does the ast lookup and match
and sets the intra-bss bit in the msdu_desc_info
structure of reo_destination ring and WBM Rx release ring.
So, change the Beryllium code to make use of this
hardware assistance for intra-bss.
Change-Id: Ic7c89efc741fefe35603082309204fbe3c9a97c7
(1)naming change in HW CC related function
(2)refinement for cookie ID generation regardless of
SPT page address 4k aligned or not
(3)move CMEM size check under cookie conversion macro
Change-Id: Ib32d802f5512e5facfa4130826406943fb3d27f1
CRs-Fixed: 2977304
Add the handlers to process the near-full irqs for
the rx, tx_completion, wbm_error and reo_status rings.
Change-Id: Ia5a2abb6d66a96e8dcb5c651d24769382db0d666
CRs-Fixed: 2965081
Implement core DP rx processing to functions in to corresponding
architecture specific be/li rx files. Keep common utility functions
in DP common files.
Change-Id: I40083e10772fd2b6ce2f1fa9e197f2ad92d0522a
CRs-Fixed: 2891021
