enable swr comp port. but not set any DRE
related registers unless comp switch is
set from the mixers.
Change-Id: I57b45bb504f0851aed90521e20a94fcb359b29ff
Signed-off-by: Sarath Varma Ganapathiraju <quic_ganavarm@quicinc.com>
mark OTP_0 register as read register instead of read and write.
Change-Id: I666c388ba10cd00daf8ac902e0b05177503b1e26
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
System gain is miscalculated due to incorrect parsing of
device tree property. Correct the parsing logic of the
system gain device tree property.
Change-Id: I8c9c5198a139a69c2d5d9520a071123261b0581f
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
added condition to check for spkr status before enabling
GLOBAL_PA to make sure PA is enabled only when Speaker
is in Enabled state.
Change-Id: Ifa4eeb7d8561bb68193abae16221dd8b2464029c
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Remove handling for PRE_SSR event.
Move the gpio handling during SSR to SSR UP event.
Change-Id: I2bb1b66db455c6211f1bf12c9e19d7e306a6243a
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
Issue: when we change the UVLO_DEGLITCH_SETTING (0x3460) 6.8ms
and above, we can’t hear any audio playback from the Music app
even at max voltage (4.1V).
HW team suggest to change the UVLO_DEGLITCH_SETTING from 0x1B
to 0x1D and WSA884X_PA_FSM_TIMER0(0x3433) to 0xC0. By these
two settings playback is not getting mute.
Change-Id: I5d2d57c26d7f467ba3d2231f1642f34643f6d716
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
In PDR cases INTR_CLEAR registers values are not updating
properly while doing reg_cache in recover from PDR. So add
these registers as volatile to get the exact HW values.
When these registe values are properly updated the FSM_PA
status is reseting properly and working.
Change-Id: I8fa7b01b3256ec8f01edc3fe48a519accfff9638
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
During some concurrencies even though we are not
enabling the swrm port, we are trying to disable it.
which causes problem w.r.t clock disablement,
To avoid that we are updating the set bit only
when port is enabled, based on that bit we are taking
decision to disable or enable the port.
Change-Id: I6707c56c40dd3716917edc097c4b7bcad68261fd
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Fix wsa884x deinitialization to avoid double
free and use correct kfree function to prevent
crash.
Change-Id: If7e0e3ceb76f9a29fbafee274147f2992e02085f
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Change snd_soc_component_update_bits to
regmap_update_bits because wsa884x may not be
initalized post IRQ.
Change-Id: I3018c680e8b2db346e5acaefc330a5af98150cf2
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Add register initialization for 2S battery configuration, including adding
relevant register shifts and masks.
Change-Id: Ie3bee4283aa57fb489153a3588db638a8a25719c
Signed-off-by: Sam Rainey <quic_rainey@quicinc.com>
Out of bound check for wsa dev mode.
Change-Id: I7a244b8f7a55e4ced06991ce8e945d737eac6f77
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Use BIAS_LEVEL_OFF trigger from ASoC to mark the wcd/wsa power
supplies to LPM (if supported).
Change-Id: I9afdd255ecb385176de82813ed9a638adfdf0292
Signed-off-by: Uppalapati, Phani Kumar <quic_phaniu@quicinc.com>
Update index to read bat cfg from dtsi.
Change-Id: I48ca32d149e14d8ce917be1ffa0822233f69239c
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
During any restart scenario, it is possible for WSA L and WSA R
to be enumerated differently than bootup, causing them to get assinged
with different swr dev_num than during bootup. Add logic to ensure that
during restarts, the swr port params from device tree are reset in
swrm driver to ensure that they match with the new dev_num.
Change-Id: Ied3eca08a95c8d6a92397c446f7c10f41886f29e
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Due to certain write-once registers needing to be set during
bootup, assume that compander on will be the default usecase, unless
haptics SKU is used.
Change-Id: I7903f3a4bf1eae82b4b9302ddc4f1e4c59d2cad3
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Update from SOC_ENUM to SOC_SINGLE to match rest of driver
implementation. Also remove remaining dev_mode enum references
in wsa884x driver.
Change-Id: I2a477c4fa8c29373ffa1e8e2eb599a0f1c61653d
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Add check to validate bat cfg,
bat cfg register read compared to dts read
Change-Id: Ib62ae3b3535a75dbc7c71b2b2ac3752fb2e61156
Signed-off-by: Shazmaan Ali <quic_shazmaan@quicinc.com>
Add mod % 2 to allow dev_index to work with WSA2 Macro.
Also fix issues associated with incorrect parameter
checking of dev_index leading to potential array index
out-of-bounds issues.
Change WSA MODE mixer control to be SOC_SINGLE_EXT for
extra parameter validation.
Change-Id: I030ee64d87fa60c6b44feebf5ccb1265f4291cc1
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
replace all dev(pr)_err/info logs
that could potentially flood kernel logs with
ratelimit functions dev_err_ratelimited and
dev_info_ratelimited
Change-Id: I32dc6002dead1a07622978c4de63d541c01982fd
Signed-off-by: Shazmaan Ali <quic_shazmaan@quicinc.com>
the offset between LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 and
LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 is 8 so updating
0x104 + 8* interp
update ng block register write for NG2 mode in Kundu
Change-Id: I44da894feebb5d25bd467ffd4d54adde111778e6
Signed-off-by: Shazmaan Ali <quic_shazmaan@quicinc.com>
Update equation that converts from the PBR table to
the correct register value.
Improve accuracy of truncation by moving the division
into one operation at the end of the formula and adding 1.
Update a few table values that were copied incorrectly.
Change-Id: I685c02778468e910820a90e2de216e0daf2491ac
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Whenever there is an interrupt,
mute the PA, then wait 1ms and unmute the pa and
check for another interrupt. Then if there are still interrupts,
retry muting and unmuting the pa with delay.
If interrupts persist, the PA will remain muted until there is a
usecase teardown or reset.
Change-Id: Ic59fc33d4606c1c630a61796d513a9ec99a4979c
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Update to latest sequence from WSA hardware systems team.
Add writes for VADC, BG, Boost
Change-Id: Ic61e1c36154ff673fce05546332e89fe683a3075
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Add to avoid crashing related to device tree parsing
of SWR port params.
Change-Id: Id839cc908fb5f7843e5fd6260b3205c8844349ba
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Found potential issues relating to uninitialized or out-of-bounds variables
present in codec drivers. Place checks to ensure proper ranges are used.
Change-Id: Ib68cba2413788a57237f1f18fc5ce5fb5c6bfb0a
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
For PBR and CPS ports, need the ability to customized slave
SWR frame OFFSET1 settings. Add similar method to WCD TX where
offset1 and lane_ctrl parameters are parsed from WSA device tree
and configured in SWRM.
Change-Id: Ib973ed93d9daa5ba02461a156e5b0a8c816d371e
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Update to 5.15 kernel dapm api.
Pin name no longer needs prefix as it is added in API.
Change-Id: I5c1378839f4c4d2aa70fb11706c5bb65d4eb0952
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Removed PA Mute, COMP Offset, Ext_vdd as they will not be used
in WSA884x.
Change-Id: I58ffd490c9929fa3388678d9ab7114207779191d
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>