Enable the 4th Tx. completion ring to save CPU load
Initialization and interrupt handling for 4th completion ring
is done here.
Change-Id: I2db27218a3c3e14d719d012f03454a6a7aa647fe
Currently, we are assigning 9 MSI Vector to DP.
But in some target available MSI Vector are less
because of which they are unable to assign 9 MSI
Vector to DP.
So, to fix the issue reduces MSI requirement for
DP from 9 to 7 and mux DP interrupts.
Change-Id: I48da2d0e8921db3298903a398f981e5b45a60987
CRs-Fixed: 3111170
Repurpose the IPA tx and tx completions rings for
normal use when IPA is disabled either via config
flag or ini.
Change-Id: Ia4b6a89c73d888a217bdef40e3c05435c3bb1bb2
CRs-Fixed: 3059730
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
Some platforms do not support cached descripts for DP Rings.
Add support to set WLAN_CFG_DST_RING_CACHED_DESC to 0 and make
__qdf_nbuf_dma_inv_range as stub if DP_NO_CACHE_DESC_SUPPORT flag is
enabled during compilation.
Change-Id: Ic6b483be25c32f3f3c79b170fb7d7557a232b4ac
CRs-Fixed: 3027649
