Commit Graph

2758 Commitit

Tekijä SHA1 Viesti Päivämäärä
qctecmdr
f5e8249fa7 Merge "disp: msm: sde: add debugfs for FAL1 and FAL10 config" 2022-01-10 21:12:07 -08:00
qctecmdr
355017e478 Merge "disp: msm: sde/dsi: reduce display cyclomatic complexity" 2022-01-10 20:44:01 -08:00
qctecmdr
27a32126fe Merge "display: driver: default post start if SBLUA DMA exist" 2022-01-10 20:09:09 -08:00
qctecmdr
7f4c58ac65 Merge "disp: msm: sde: add line-based QoS calculation support" 2022-01-10 19:12:59 -08:00
GG Hou
644927312e disp: msm: sde/dsi: reduce display cyclomatic complexity
msm/sde/sde_encoder.c
	_sde_encoder_update_rsc_client()
	sde_encoder_prepare_for_kickoff()

msm/dsi/dsi_drm.c
	dsi_bridge_mode_fixup()

Lower the cyclomatic complexity for this function by splitting
the work into helper functions.

Change-Id: I2285809a33078e29989a6b44800c18342aa24170
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
2022-01-10 19:05:50 -08:00
GG Hou
830adf80d6 disp: msm: sde: add debugfs for FAL1 and FAL10 config
Add below debugfs node under */debug/core_perf for micro-idle FAL1 and
FAL10 configuration, uidle_fal10_target_idle_time_us.
  1.uidle_fal10_target_idle_time_us
  2.uidle_fal1_target_idle_time_us
  3.uidle_fal10_threshold_us
  4.uidle_fal1_max_threshold

Usage:
Cat and echo are both available.
echo [value in micro seconds] >
	/sys/kernel/debug/dri/0/debug/core_perf/uidle_fal10_threshold_us

The new value will take effect after any update on plane.

Change-Id: I48896f59a8c0dc22624394ae197a49e3492953da
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
2022-01-10 19:03:47 -08:00
qctecmdr
69d1699364 Merge "disp: msm: sde: add offline WB QoS support" 2022-01-10 18:41:50 -08:00
qctecmdr
55888849a1 Merge "disp: msm: sde: update DT parsing for VBIF QoS remap levels" 2022-01-10 18:11:21 -08:00
qctecmdr
a33fefe00b Merge "disp: msm: sde: update danger/safe QoS LUTs for landscape panels" 2022-01-10 17:38:19 -08:00
qctecmdr
2d519071e8 Merge "disp: msm: sde: remove rgb/cursor pipe related code" 2022-01-10 16:24:25 -08:00
qctecmdr
bf82d96a61 Merge "disp: msm: dsi: add API for handling PHY programming during 0p9 collapse" 2022-01-10 15:54:37 -08:00
Veera Sundaram Sankaran
d1dcc8da8e disp: msm: sde: remove rgb/cursor pipe related code
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.

Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-07 16:53:44 -08:00
qctecmdr
6349465588 Merge "disp: msm: sde: disable ot limit for cwb" 2022-01-07 11:28:22 -08:00
qctecmdr
e1586e4441 Merge "disp: msm: use pm_runtime_resume_and_get instead of pm_runtime_get_sync" 2022-01-07 11:28:22 -08:00
Shashank Babu Chinta Venkata
1b53cc574b disp: msm: dsi: add API for handling PHY programming during 0p9 collapse
Add HW recommended programming sequence for when PHY is allowed to turn
off during idle.

Change-Id: Iaeafa17d9821913b42ae669dbd21f244783f4cdd
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
2022-01-06 16:33:07 -08:00
Shashank Babu Chinta Venkata
122df95255 disp: msm: dsi: add new PHY and PLL version files
Change adds the new files for DSI PHY version 5 and 4nm
DSI PLL.

Change-Id: I97712d6ce53a60a6fae1c8331b6ba9a5d17b8d34
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
2022-01-06 16:32:56 -08:00
Veera Sundaram Sankaran
56862f8118 disp: msm: use pm_runtime_resume_and_get instead of pm_runtime_get_sync
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.

Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:28:41 -08:00
Veera Sundaram Sankaran
ebe8b1bace disp: msm: sde: add line-based QoS calculation support
From kalama, add support for QoS fill level calculations based on
line-based QoS calculations.

Change-Id: I524ca29c6e9d1912b44a328a2a88d08341cccefc
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:16:24 -08:00
Veera Sundaram Sankaran
b7f241585a disp: msm: sde: add offline WB QoS support
Add support to parse and configure QoS values for offline writeback.
Expose a writeback connector property to allow user-mode to set
the usage type of the writeback block - WFD, CWB, offline-WB.

Change-Id: I864f79c4896ec757ac2d8b0f57a6a5775d164f21
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:16:12 -08:00
Veera Sundaram Sankaran
3c8871f45b disp: msm: sde: update DT parsing for VBIF QoS remap levels
Update the sde HW catalog parsing to get separate values for rp_remap
and lvl_remap for each qos level. Previously, only rp_remap were provided
and the same was applied for lvl_remap. As part of the change, add cnoc
remap level which is added as part of MDSS 9.x.

Change-Id: I112a715f8b33cd4b028886d8074e35fef75b8aab
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:14:35 -08:00
Veera Sundaram Sankaran
689d2cd473 disp: msm: sde: update danger/safe QoS LUTs for landscape panels
Update the DT parsing logic to get danger/safe LUT values for
both portrait & landscape for all the usage types.
As part of the change, fix the correct CDP write setting for
CWB usecase.

Change-Id: I4fb6d17537de5df31c9b7f52983c0c3890265174
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:13:44 -08:00
Nilaan Gunabalachandran
5c8caa4c60 disp: msm: sde: disable ot limit for cwb
Currently ot limits are being set for concurrent writeback,
which is not supported. This change adds a check to correctly
set wfd parameter while applying ot limit settings.

Change-Id: I87c1ca756c1714fec4466cd5a5a820ddf2519975
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:12:01 -08:00
Veera Sundaram Sankaran
cab7b41dde disp: msm: sde: allow CDM access for all WB blocks
Currently, CDM usage is restricted to WB2 and INTF3. Expand the usage
to all writeback blocks. However, CDM is a single HW block and can be
used by only one interface at any point of time, which is controlled by
the sde_rm reservation.

Change-Id: I9fc892046e5df6c1d4d74ca410bf48053136a1ca
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-01-05 17:10:26 -08:00
GG Hou
4d5ae8084e display: driver: default post start if SBLUA DMA exist
Keep posted start as default configuration in driver
if SBLUT is supported on target.
Do not allow HAL to override driver's default frame trigger mode.

Change-Id: I46ad5c87abfb05446592b0e497a23a3a3fc62ca7
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
2021-12-14 22:58:29 -08:00
qctecmdr
e7c09f0092 Merge "disp: msm: sde: increment rounded corner HW version" 2021-12-13 22:47:36 -08:00
qctecmdr
27576cdfd5 Merge "disp: msm: sde: extend RC2/3 and LTM2/3 for Kalama target" 2021-12-13 22:47:36 -08:00
qctecmdr
b6c008113a Merge "disp: msm: sde: add support for DMA 4,5 for Kalama" 2021-12-13 22:47:36 -08:00
qctecmdr
9c9343d54f Merge "Merge branch 'display-kernel.lnx.5.10' into display-kernel.lnx.1.0" 2021-12-13 21:16:18 -08:00
Jeykumar Sankaran
cf39b00660 Merge branch 'display-kernel.lnx.5.10' into display-kernel.lnx.1.0
Change-Id: I5d2b08380b6b0eb09492b950fb38cd9a0b3196c1
2021-12-08 12:37:35 -08:00
Amine Najahi
d59faab858 disp: msm: sde: increment rounded corner HW version
Increment rounded corner HW version to 1.1

Change-Id: I8b1004b84e4b897d68b08deb559ef96ea097d7b6
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
2021-12-07 15:11:43 +08:00
Xu Yang
882cc50498 disp: msm: sde: extend RC2/3 and LTM2/3 for Kalama target
Change supports extending the enum for LTM2/3 and RC2/3.

Change-Id: I45df1808fa3a7e23f20afef084edaf091a59d7dd
Signed-off-by: Xu Yang <quic_yangxu@quicinc.com>
2021-12-07 11:40:54 +08:00
Renchao Liu
1238001c28 disp: msm: sde: add support for DMA 4,5 for Kalama
Expand reg dma data structures to support DMA 4,5.

Change-Id: I3aa7e879eb5ab7f89a7152e202759e885b05c75a
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
2021-12-06 17:32:08 -08:00
qctecmdr
c1bc0c5d3d Merge "disp: msm: sde: update ubwc version 4 check" 2021-12-06 12:12:21 -08:00
Jeykumar Sankaran
fe83c42f56 disp: msm: sde: add support for mdp vsync timestamp
MDSS.9.0 adds support for mdp vsync based HW timestamps
on top the existing support for panel vsync based timestamps.

This allows us to enable vsync timestamp calculations for all the
use cases including a few corner cases (e.g. programmable fetch)
which we couldn't support with the existing HW.

This change adds the new HW register support and modifies the
timestamp read logic to use mdp vsync on supporting targets.

Change-Id: I2cb1b56ca9154174331c4fc1d8f82319b6989247
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
2021-12-06 11:06:41 -08:00
Jeykumar Sankaran
24aa389edc disp: msm: sde: separate out DSC 4HS config programming
Dedicated registers are introduced for DSC 4HS merge block
programming from MDSS.9.0. This change adds support in the
driver to identify the change using a DSC feature flag
and separates out 4HS merge block programming to use appropriate
registers based on the DSC HW feature.

Change-Id: Ia64a1ed4bc5f5f301ab422144916cdce2a1dadac
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
2021-12-06 11:05:29 -08:00
Jeykumar Sankaran
39e7775bff disp: msm: sde: add support for CTL done irq
From Kalama, the HW scheduler abstracts the low level
PP_DONE/WB_DONE interrupts and generates a common
CTL_DONE interrupt per hw ctl. This saves the software
the irq latency delays to process the frame complete
operations when multiple encoders are involved.

If supported, this change enables and waits for the
CTL_DONE interrupt instead of PP_DONE and WB_DONE.

This change adds support to wait for CTL_DONE irq in
only command mode panels as we don't drive two WB blocks
with single CTL.

Change-Id: I084d6bfb6a9fb0b48f912fe5787401c460ec5b56
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
2021-12-06 11:03:22 -08:00
Jeykumar Sankaran
4df7bb68dc disp: msm: sde: clean up INTF2 interrupt masks
Clean up stale mask bits which were deprecated from
the HW for the past few generations.

Change-Id: Id6bc20557d1047f7bffbb9641248dfbe0170daf0
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2021-12-05 10:00:29 -08:00
qctecmdr
2a867bb340 Merge "disp: msm: add display config support for parrot" 2021-12-05 04:44:36 -08:00
qctecmdr
d72a4a4f0c Merge "disp: msm: dp: add support for 4nm DP PLL" 2021-12-05 04:44:36 -08:00
qctecmdr
e329cf3904 Merge "disp: msm: dsi: allocate priv info and bit clk list per fps" 2021-12-05 04:44:35 -08:00
qctecmdr
1f8ce74ba8 Merge "disp: msm: dsi: add ctrl and phy version support for Kalama" 2021-12-04 20:12:42 -08:00
Soutrik Mukhopadhyay
aa0eacb522 disp: msm: dp: fixed version check 4nm target
Changes include support to correct the version
check for DP PHY changes for 4nm target.

Change-Id: Ib891d43bd5db10edc4b49a70f7a3b8af073167cd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2021-12-03 17:47:25 +05:30
Ingrid Gallardo
450f6b19b4 disp: msm: sde: update ubwc version 4 check
Update ubwc version 4 check to only check for
the major version.

Change-Id: I4050f7d1a0858741e20f621d186e0ec2b9f7b10c
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
2021-12-01 22:21:45 -08:00
Veera Sundaram Sankaran
3cebf0853a disp: msm: sde: add idle power collapse support for writeback
Extend idle power-collapse support for writeback.

Change-Id: I9b85f367dc7489c1e3c927cbd6040be8b879057e
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-12-01 15:11:16 -08:00
Veera Sundaram Sankaran
ec7bb6c31f disp: msm: sde: enhance writeback encoder logging
Add encoder-id and wb-id in all the eventlogs, errors and debug
messages throughout writeback phys encoder to help in debugging.
Add traces to all the IRQs in writeback to track them efficiently.

Change-Id: I919e4d5054407ea5b01889dfd17c8cab6b40ee52
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-12-01 15:11:16 -08:00
Veera Sundaram Sankaran
8a86ccc9fc disp: msm: sde: add dnsc_blur validations in wb encoder
Add downscale blur block validations in atomic_check phase of writeback
encoder. Downscale blur along with partial update is not supported.
NV12 output in WB is not supported with downscale blur as CDM block
usage is mutually exclusive with dsnc_blur. If destination scaler is
enabled, the ds src or dst should match with dnsc_blur src based on
the ds tap point chosen.

Change-Id: I1d643dc26738c0e77d8e9181b4c834693153209c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-12-01 15:11:16 -08:00
Veera Sundaram Sankaran
88c9a184f9 disp: msm: sde: use dnsc_blur src w/h for calculating crtc/lm w/h
When downscale blur feature is enabled, calculate the mixex and crtc
width and height using the dnsc_blur's src width & height. Update the
sde_crtc_get_mixer width/height functions to return the correct size
based on the features enabled.

Change-Id: I52dd88cc52e1ca5cb37e381e92e0e3032e7b090f
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-12-01 15:11:16 -08:00
Veera Sundaram Sankaran
cc23729c87 disp: msm: sde: configure the dnsc_blur hw block
Add changes to configure the downscale blur hardware block based on
the conifgs set by user-mode. Program the ctl's writeback flush and
active bits when dnsc_blur is enabled. Bind the pingpong block that
feeds pixels to dnsc_blur hw block. Disable the active bits and unbind
the pp block binding during wb disable.

Change-Id: I1961ab437e344b13d0c186c1675a5bf79b84ea74
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-12-01 15:11:16 -08:00
Veera Sundaram Sankaran
93ec98a33e disp: msm: sde: expose dnsc_blur connector properties
Add downscale blur connector properties to expose the hw block count,
downscaling filters used and the ratios supported. Add a custom dnsc_blur
property to allow usermode to send the required configuration to program
the hardware. Expose only for the virtual connector as the dnsc_blur is
only supported with writeback block.

Change-Id: I35dd263d9d5aafdb59bacbb3a0528ffd2bcaf6a3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-12-01 15:11:16 -08:00
Veera Sundaram Sankaran
c24dd3d172 disp: msm: sde: add supported filter and ratios for dnsc_blur
Add sde catalog entries for the downscale blur supported filters
and the corresponding downscale ratios. The PCMN supports ratio
from 1 to 128 and gaussian filter supports specific ratios in the
range between 8 to 64.

Change-Id: Ifdf1a8fc7cfc5f5bd1297f10c7946c2bf9b63dcd
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-12-01 15:11:16 -08:00