Commit Graph

349 Commits

Author SHA1 Message Date
Narendra Muppalla
f402d8e542 disp: msm: sde: program dither based on input data
This change programs dither based on user mode input data and
reprograms the dither when device comes out of power collapse.

Change-Id: I83be20c8eb2dc2221cc57cd2395f6512338ff6ef
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-02-10 15:33:42 -08:00
qctecmdr
52161a09b6 Merge "disp: msm: sde: move resource state change to display thread" 2020-02-07 15:10:32 -08:00
qctecmdr
394cb141e4 Merge "disp: msm: sde: fix dsc hw resource reservation" 2020-02-07 14:00:32 -08:00
Abhijit Kulkarni
2c6c071e45 disp: msm: sde: move resource state change to display thread
In the current kernel version calling kthread_mod_delayed_work
in irq context is not allowed. Due to this resource control state
change to idle on frame done is handled in display thread context.

Change-Id: I709f7e04ac23d7dde72cea1c19d3767b6abc147e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-02-07 10:33:08 -08:00
Christopher Braga
e5383fac2e drm: msm: sde: Centralize last command logic for SB DMA
The original SB DMA last command logic results in multi
feature sets being applied across different frames. Update
the SB DMA logic to do a single last command per CTL path
to ensure all features using SB DMA can get applied in the
same frame.

Change-Id: Ida837765c0f018b0e03afb0a33ece625a0df81eb
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-02-06 14:34:00 -05:00
Christopher Braga
fe087fde3c drm: msm: sde: Attempt DB DMA fallback if SB DMA not supported
The current implementation of DSPP GAMUT + IGC programming rely on
SBDMA for programming. This will cause GAMUT + IGC to be
unprogrammable on derivative Lahaina chipsets that do not have SBDMA
support.

Update the SBDMA handling to more intelligently check if SBDMA is
present, and fallback to DBDMA module where possible.

Change-Id: I89d07e38459ab59b96c69558178b8e97062ed93d
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-02-06 14:33:32 -05:00
Christopher Braga
c5378278f3 disp: msm: sde: Add SSPP Gamut support using new opcode
A new LUTDMA opcode is added to LUTDMA V2 to speed up certain LUT
programming. This change updates the SSPP Gamut LUT programming using
the new opcode and new LUT BUS.

Change-Id: I8b88483dc3acbfcdbd6f441bc2105f4368fa42bb
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-02-06 14:22:09 -05:00
Christopher Braga
8d5499f14d disp: msm: sde: Add DSPP Gamut and IGC support using SB LUTDMA
Add new implementation for DSPP GAMUT and IGC features using
newly added SB LUTDMA.

Change-Id: Iebc099351fde058d7f0e20a9e256bcd71c557506
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-02-06 14:22:01 -05:00
Christopher Braga
5e28b86e3c disp: msm: sde: Add support for SB LUTDMA
A new LUTDMA HW instance has been added to support programming of
SB features via LUTDMA. This change adds corresponding support for
the new SB LUTDMA, including catalog parsing, reg_dma init/deinit/ops
updates and new opcode support.

Change-Id: I0fed7a6e93cd96fe9fe562d2470a8789b161d1bc
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-02-06 14:21:53 -05:00
Christopher Braga
aa818a2f5b disp: msm: sde: Add flush support for DSPP SB
Extend unified flush bit support to control new DSPP
SB LUTDMA bit.

Change-Id: Iba941a4bcd140ceb88e49ab83700c4baef804e0f
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-02-06 14:21:44 -05:00
Abhijit Kulkarni
06ca9dd1e5 disp: msm: sde: fix dsc hw resource reservation
In atomic test phase DSC Hw block should be allowed to be reserved
without checking the mode information. Mode information is not
available before bridge enable is called and this results into dsc
not programmed very first mode set.

Change-Id: Ia9ec9a3c9387e34a8bb1d98ee6932aef8725bc8c
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-02-06 10:56:56 -08:00
qctecmdr
3da2742a90 Merge "disp: msm: sde: fix max downscale check for legacy HW" 2020-02-06 10:02:45 -08:00
qctecmdr
ebb7a67bd3 Merge "disp: msm: sde: reduce complexity for sde_crtc_install_properties" 2020-02-05 17:25:56 -08:00
qctecmdr
6eab0179f2 Merge "disp: msm: sde: fix spacing of #defines" 2020-02-05 16:21:37 -08:00
qctecmdr
5e8abb667b Merge "disp: msm: sde: use helper to determine plane pre-downscale cap" 2020-02-05 15:38:02 -08:00
qctecmdr
23c62b5d23 Merge "msm: drm: uapi: add rounded corner uapi" 2020-02-05 12:51:43 -08:00
qctecmdr
13c967c3cf Merge "disp: msm: sde: intf accept 64-bit compressed pixels" 2020-02-05 11:54:03 -08:00
Steve Cohen
6a2bd3aabb disp: msm: sde: reduce complexity for sde_crtc_install_properties
Reduce the cyclomatic complexity for installing CRTC properties.

Change-Id: I42572413713b3a079fb5edcaa25d9050b76adc6c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-02-04 16:04:35 -05:00
qctecmdr
c89633ed36 Merge "disp: msm: add support for variable compression ratios" 2020-02-03 00:11:10 -08:00
Steve Cohen
c4d617f2c2 disp: msm: sde: fix max downscale check for legacy HW
Legacy HW that does not support pre-downscale capability will
incorrectly fail certain scaling checks. Fix those checks to
fully support HW without pre-downscaler.

Change-Id: I8f645bbff959e176c1d4d05a30a580113e320d4b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-01-31 14:33:01 -05:00
Steve Cohen
516780f4b3 disp: msm: sde: use helper to determine plane pre-downscale cap
The pre-downscale capability is checked in multiple places
within sde_plane.c file. Add a helper function to check this
capability flag instead of manually checking this bit.

Change-Id: I21f818a9d81dd63e5eb3da248532904cfa55c838
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-01-31 14:32:45 -05:00
Amine Najahi
d26c9811ca disp: msm: sde: add partial update handling in cp framework
Add partial update handling for color processing features.
This will validate and set cp features for each frame if
applicable.

Change-Id: Id78c1f4ecbd74781c0c03c04efb528d6a8b91264
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-01-31 07:51:54 -08:00
qctecmdr
da7839e18e Merge "disp: msm: use iterator APIs to walk the connector list" 2020-01-30 17:35:51 -08:00
qctecmdr
5645148693 Merge "disp: msm: sde: refactor use of master_plane_id" 2020-01-30 16:51:08 -08:00
qctecmdr
290f00dbd5 Merge "disp: msm: sde: fix min pre-downscale check" 2020-01-30 16:06:29 -08:00
Amine Najahi
119b84ea5c disp: msm: sde: add atomic check handling in cp framework
Add atomic check handling in color processing framework.
This will check cp features during the validate phase.

Change-Id: I6d94316a749ad247aec0554c31fa56af6db61ab6
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-01-30 14:38:57 -05:00
Amine Najahi
c84f906b30 disp: msm: sde: add support for lutdma absolute mdss addressing
Add support for absolute mdss addressing lutdma payload. This will
allow any mdss register to be programmed using lutdma.

Change-Id: I3af3a85182a75a0583c49c797d6adf99b6ba2ee7
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-01-30 14:28:09 -05:00
Abhijit Kulkarni
7317dc417f disp: msm: sde: intf accept 64-bit compressed pixels
This change enables the interface hw block to accept
64-bit compressed pixels. This configuration is enabled based
on hw capability. For current hw, this is required any time
the compressed pixels flow through the interface block,
whereas in the previous version of DPU hw this configuration
is only required for topology using 4 way dsc merge.

Change-Id: I7bf79d035dba5084c5057022a7fa1117479e8d52
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-29 22:39:44 -08:00
Steve Cohen
f303123d53 disp: msm: sde: fix spacing of #defines
Defines should always have a single space between #define and
the keyword to allow for searching where these definitions are
located using grep.

Change-Id: I38778e789b12df8a7a22c22dd27152a5ab047405
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-01-29 14:51:09 -08:00
Abhinav Kumar
e3f23771ba disp: msm: add support for variable compression ratios
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.

Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.

Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:46:57 -08:00
Abhinav Kumar
27844b7b60 disp: msm: dp: remove usage of compression ratio enum from DP driver
As overall display driver is moving away from hard-coded compression
ratios, prepare the DP driver for the same by removing the usage of
the compression ratio enum.

Change-Id: I298db7d20baed8afec9f96dff8c7e950702bfec9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:46:46 -08:00
Abhinav Kumar
c4f5050e13 disp: msm: add VDC topology related changes
Add support to configure the DPU pipeline to support VDC-m
topologies.

Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:45:35 -08:00
Abhinav Kumar
d88b5b5c67 disp: msm: add hardware register ops for VDC-m block
Add hardware register set and programming for VDC-m block.

Change-Id: I60ef27b507284521abdd10bb679a85303475ddc3
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:45:05 -08:00
Abhinav Kumar
88a43f2441 disp: msm: sde: add hardware catalog support for VDC-m block
Add hardware catalog support for VDC-m block to parse
the register offsets and feature capabilities.

Change-Id: I1bfbc4b6e7e9f34738d49fecdef4b427a0ccded7
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:44:48 -08:00
Abhijit Kulkarni
748372a24c disp: msm: sde: add qactive override
This change adds the hooks to enable the active signal override
in power collapse sequence. Active signal override is needed to
disable the clock gating when the power collapse sequence
is running.

Change-Id: I9edaed7960b236b3d0179cb67f9cc2c9b3546c9d
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-23 14:38:26 -08:00
Linux Build Service Account
8e660ebeaf Merge "disp: msm: sde: add support for 4k aligned memory pools" into display-kernel.lnx.5.4 2020-01-23 14:19:31 -08:00
Linux Build Service Account
bb0ca40080 Merge "disp: msm: sde: add support for new dspp flush" into display-kernel.lnx.5.4 2020-01-23 14:19:30 -08:00
Linux Build Service Account
0a36198742 Merge "disp: msm: sde: check correct field for XIN idle status" into display-kernel.lnx.5.4 2020-01-23 14:18:29 -08:00
Abhijit Kulkarni
616c59b000 disp: msm: sde: add support for 3d_mux DSC topology
This change adds support for dsc using the 3d mux hw block.
The 3d_mux hw block merges the input from layer mixer before passing to
dsc block for compression.

Change-Id: I21544c33fff2c1e604c0ae712a036a127d25afcf
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 13:58:06 -08:00
Abhijit Kulkarni
af5306875f disp: msm: sde: add ctl api to enable/disable sub-blocks
Certain sub-blocks need to be enabled disabled dynamically on a
seemless mode switch (for ex. partial update) CWB is another example
where control path interface configuration needs to be dynamically
changed on enable/disable of concurrent writeback. Similarly
3d mux needs to be enabled/disabled for partial update use cases.
This change modfies the current api update_cwb_cfg and makes it
more generic and adds support to enable/disable only the 3d mux.

Change-Id: I5e5a6e78b0599f689cb2f83d0d626a5f392eff6e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 13:58:06 -08:00
Abhijit Kulkarni
1ef5cee6ca disp: msm: add api to get active status of hw blocks
This change introduces new ctl path api read_active_status to check
if a particular hw block is active or not in the current control path.
This is specially required in continuous splash use case when bootloader
has programmed certain blocks and the kernel driver tries to find
out the same configuration. This is used to ascertain which DSC block
is active in continuous splash case since DSC blocks are not tied to
mixer blocks.

Change-Id: I8dd590aa2dc764bd340727c166e1133ef9ce7af5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 13:57:55 -08:00
Abhijit Kulkarni
e2726c7b1a disp: msm: sde: allocate dsc block based on capability
Certain DSC hw blocks only support 444 mode, while others
support both 444 and 422 modes. This change adds support in
resource manager to check the hw resource requirement with
the capability of the block and then reserve the correct
hw resource.

Change-Id: If85beb2f2f25e9eb7f8a8321c94b57878d048369
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
d3d3f808d4 disp: msm: sde: use pp dsc api only if hw supports
This change checks the capabilities of pingpong block to
check if it needs to call the pingpong api to enable or
disable the dsc. Certain hw versions do not have support
in pingpong block to enable/disable the dsc instead the
dsc block itself have the hooks to control the DSC.

Change-Id: I17dd45479cc33ff2e81f6a6e5a5a8704562dfd24
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
a00714beae disp: msm: sde: add DSC 1.2 implementation
This change adds implementation to configure DSC 1.2 block
registers to enable both dsc1.1 and dsc1.2 specifications.

Change-Id: I2307d7dace05bf20384d3221e9aca65e296b12bd
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
6be579d992 disp: msm: sde: parse dsc_1_2 hw sub-blks
This change adds additional dsc hw sub-blks and their
advertized capabilities. These are required for supporting dsi 1.2 hw
and making the code backward compatible with older hw version.

Change-Id: I84d86ad4f6ac2dd76324bbfd5600b010738b3310
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
acb8d98e66 disp: msm: use upstream dsc config data
This change enforces dp, dsi and the sde drivers to use the
drm framework defined dsc_config data structure. As a part of this,
it introduces the sde_dsc_helper API to configure the dsc params
and creating a PPS command. Earlier each driver implemented it's
private versions leading to duplication of code. Additionaly the
helper api supports DSC spec 1.2 422 and 420 mode.

Change-Id: I25933fab08cdabbc6787079926885d1a78945e97
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
673ebb896c disp: msm: sde: update initial lines calculation for dscv1.2
This change updates the initial lines calculation implementation
to support dsc 1.2.

Change-Id: I322057efc5a4be94d42c29680437d1923ee3547e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
62eecded22 disp: msm: sde: support a single dsc setup function
This change adds a single setup function for different dsc topologies.
This simplifies the dsc code and allows for additional topologies
support.

Change-Id: Iaaddd6e51a2fa53d113d618328dee2bf63e30cab
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:23 -08:00
Abhijit Kulkarni
a8f60081ae disp: msm: sde: add api to query topology details.
This change adds new resource manager api to get number of
ctl paths, interfaces and compression encoders used in the
current topology. This API is required to support both dsc
and vdc encoders and make implementation more generic.

Change-Id: I6cc25e51574cf71cd39f479049572ee7b7e0ead0
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:23 -08:00
Abhijit Kulkarni
ac8ae6b85f disp: msm: sde: use dce api to configure dsc
This change introduces dce api to the encoder component to
configure supported compression hw. This allows encoder to
remain independent of the compression type and specification
supported by the hw.

Change-Id: I6bc35289495b05f57a83323cbab1ea14e9e15db0
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:14 -08:00