Change will be removing checking and clearing dsi cmd done
interrupt in commit thread and in workqueue context, which
can race with dsi isr, when it tries to clear the interrupt.
Change-Id: I96e7f8dffed1af3cec0c7668ab1729337d4b260e
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
There is lag or lead in the FPS during dynamic clock change,
along with the increment or decrement in clock. So, HFP or
VFP are adjusted to ensure a constant FPS.
Change-Id: I87ba7a185104a0f5f1d13734a7e487e728d6b2c0
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change installs blob property on each crtc for client to program
SPR block configuration based on display panel SPR pattern. Property
installation is conditional only if MDSS hw has SPR block entries.
Change-Id: Ie85423d83b7badc547e75e6eb07ee6b9945f8834
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change parses SPR enable entry from panel device tree and
populates SPR specific information in panel data structure.
Valid entry of SPR pack type is treated as panel requirement
to enable SPR for specified pack type from source end. This change
also populate connector capabilities blob with SPR pack type.
Change-Id: I9d9ab8a990476fba281e12890bf3f7b17a174d79
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change parses SPR hw block entries from device tree and populate
SPR block as sub block of DSPP block. Change also enables register dump
by registering sub blocks with sde driver register dump routine.
Change-Id: Ic603cd3cc001dddce5dfea61341c166a5fec1682
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Update the table with new testpoints added for lahaina.
Change-Id: Ib1253f696e6e670b6dc475cc68a73c8c41ee264b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Upstream has added an "enhancement" to the DMA allocator to
reject coherent allocations less than a a full page, so allocate
device managed memory instead of artificially inflating the
buffer sizes. This has the added benefit of having this memory
automatically freed when the module is unloaded, avoiding
possible leaks.
Change-Id: I653f2cd1f06f1a352cd61e36ea8baaf7c30efd98
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Use the new altmode framework to receive the connect, disconnect
and attention events.
Change-Id: Ic542525b526e1abd0f153c293bca6e4cdbb6bf0b
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Add support for PLL programming in the DisplayPort driver.
Change-Id: I4f08a621dcae5d1f54d67bb5c34409249012cc7b
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Create a new driver to handle sysfs and topology events that are
related to application/userspace layer interactions for HDCP
functionality. In turn, this will create a clear separation from
the HDCP QSEECOM layer that defines the communication mechanism
between the kernel and the TrustZone layers.
This implementation is based on a snapshot of the msm_hdcp
driver as of this commit 10ffbfa2c7e03c09 ("drm/msm/dp: Snapshot
of DP and supporting files") on kernel 4.19 project.
Change-Id: I834620420b8d6a580f1905a2b3250cf4e5b8f293
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Add a compile time flag for the MST feature that will allow
selectively enabling the feature.
Change-Id: I8bf288277c7af00c3cf254a8c757151559e0a010
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update colorimetry definition usage and how we access DSC information
as per changes in the upstream DRM framework code.
Change-Id: I28482380124734680e46904b8d536ebadba8cc60
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
This change adds logic to align timing engine vsync with panel
tear check if it is supported.
Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
DSI host vsync is expected to align with panel internal vsync
during transition from command mode to video mode operation.
In order to facilitate this, keep panel TE enabled in video mode
operation until it is aligned with vysnc.
Change-Id: I3fc59b01336b30cd436be332af6953c5a01be7fd
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Change fixes parsing of software TE tag added to the display
name from bootloader.
Change-Id: I4747cc6eff43d681477150d6cad7a737963bf11c
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Check against the max clk_type and clk_state enumerations before
to validate the type and state of DSI clocks to avoid Control
Flow Integrity issues.
Change-Id: Id53465c2b12debb1b356c0c91064eb017c2ca30d
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The original change avoids unnecessary reprogramming
of plane vbif registers, but still copies values into
a local struct before exiting based on boolean. This
can be taken care of by 01e1d4136cc1 ("drm/msm:
minimize qos remap updates") instead.
This reverts commit 0c7159de4f.
Change-Id: Idd9b066db9ebad092aa1a6dd2cf47050b0babd0c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Register the MDSS_HW block (at base offset 0) for access via the
sde_reg node in SDE's debugfs directory. This is needed for
validating correct UBWC register programming.
Change-Id: I2494e066a7603747f2ec12546e58a17f2120a521
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Move blendstage initialization to the atomic begin path in the
case where mixers are not setup. Additionally, clear all
blendstages during crtc disable to clean up registers.
This will avoid resetting each of the blend stages in every
commit and then writing only to the layer being used.
Change-Id: Idf7cb3e17de37034c2060f2563bc082fceb5cae9
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This reverts commit 7470449242.
This is required to satisfy cross component dependencies with
kernel-5.4.
Change-Id: Idba2983923a8605ec0a05408da48f7549730035d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
This reverts commit 982574f095.
This is required to satisfy cross component dependencies with
kernel-5.4.
Change-Id: I979e0371973376c46f2a11659348df726be2679d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Add docstrings for sde_get_dt_props and cleanup error checking
in some call sites.
Change-Id: I031b7a928b894c2db9b8c95863807d77f25176d6
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This reverts commit eaed3221fa
which uses a downstream implementation for checksum calculation.
This will be fixed once the upstream changes to address checksum
calculation are merged.
Change-Id: I7a6ed1c4d4baf52533485d59bcdcb6dd1009d626
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the HBR and RBR swing and pre-emphasis levels as per the
latest published hardware programming guide.
Change-Id: If3b6713e0b6680f65539882221aae32b00bf0254
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update colorimetry definition usage and how we access DSC information
as per changes in the upstream DRM framework code.
Change-Id: Ie52aed2df2f6c3f2df1e4129f342a85256f8fae4
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
With the introduction of sync state drivers, msm_drm probe can be
moved back to module level from late init. It is now guaranteed
that the dependencies are probed before the actual driver is.
Change-Id: Ib7c3e0e3c3d32b37b7672b6119bcf5371783659d
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Support different safe, danger and creq qos lut
configuration based on display fps. It also removes
the fill level calculations from sspp and wb block
because mdss hw supports simple configuration.
Change-Id: I203e4300c9eab27d3632c890bedd6383cca0e5a8
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
DSC and VDC-M sub-block registers are not on contiguous
address range. This change allows dumping the registers
for each individual sub-block.
Change-Id: I06dfc64562211370a0e29f6fc1134351c47722f6
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Ramdump node only allocates portion of splash
buffer memory. It should not be within reserve
memory area because splash buffer is already reserving
these pages.
Change-Id: I7caa818b19cb993571e6bf0648a4dfbbc2ad9d71
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Add underrun line count information for each underrun.
Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.
Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This reverts commit 483c9fdff4c611f250574fe6909cd8e5336808f5. It
is no longer needed on kernel-5.4 as all the upstream changes are
now available.
Change-Id: I11b0317c0e05ea2fe03fb1af734a79a1174b1922
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
