نمودار کامیت

1763 کامیت‌ها

مولف SHA1 پیام تاریخ
Shamika Joshi
f28d9e0a6a disp: msm: sde: add support for INTF WD long term jitter restore from ipc
Change adds support for storing the INTF watchdog timer long term jitter
curve state. The state before collapse is stored in wd_jitter and
restore back during power restore.

Change-Id: Id83b5cc754daea89d7844ab67b38e12199525ff8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-10-25 21:06:39 -07:00
qctecmdr
38c0d4cdba Merge "disp: msm: sde: enable uidle on pineapple target" 2022-10-24 12:37:21 -07:00
qctecmdr
f320be5d5e Merge "disp: msm: sde: avoid setting plane qos_dirty during cwb modeset" 2022-10-24 12:37:21 -07:00
qctecmdr
48dc1006fd Merge "disp: msm: sde: improve qsync trigger window accuracy" 2022-10-24 12:37:21 -07:00
Amine Najahi
88a24f8c45 disp: msm: sde: improve qsync trigger window accuracy
Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).

This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.

Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-24 07:29:31 -07:00
Amine Najahi
16f59151af disp: msm: sde: override qsync read pointer during IPC
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the trigger
window to be out of sync when power is restored until the
next vsync is received.

This change overrides the internal read pointer value to
the maximum qsync timeout value on restore and defers frame
trigger to next vsync.

Change-Id: Ibdad3f8eb367136ee0d766bed10742a281e36b4e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-24 07:29:24 -07:00
Veera Sundaram Sankaran
1b1618ed36 disp: msm: sde: avoid setting plane qos_dirty during cwb modeset
The encoder modeset updates all the plane's qos_dirty flag attached
to the crtc to make sure the qos params are updated during seamless
mode-switch cases like fps or resolution switch. But this is not
required for cwb encoder modeset as it does not have any effect on
the planes attached to the main display. Add check to avoid this
reprogramming.

Change-Id: I1ab7a71971b7200a50e6643407327734b1c9cbc5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-10-24 07:29:15 -07:00
Nilaan Gunabalachandran
6ae388a1c1 disp: msm: sde: enable uidle on pineapple target
Pineapple target adds support for writeback contributing to
fal status. This removes the need to signal fal10 veto in those
usecases. In addition, it is no longer needed to program uidle
active per ctl path.

Change-Id: I5e3509fa6399d212563322d51eba04c38a41e9b8
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-21 12:03:39 -04:00
qctecmdr
03f6a06942 Merge "disp: msm: sde: enable WB rotation feature for pineapple target" 2022-10-20 12:29:12 -07:00
qctecmdr
f378c8b20e Merge "disp: msm: sde: add line counter logging" 2022-10-20 12:29:12 -07:00
qctecmdr
2d49ae68e6 Merge "disp: msm: sde: cache cwb enc mask to use during seamless transitions" 2022-10-20 12:29:12 -07:00
Prabhanjan Kandula
973fb33096 disp: msm: sde: enable WB rotation feature for pineapple target
This change enables the WB rotation feature support for pineapple target.

Change-Id: Ib222c2b2996a40c72414c6c3a581916b95ebffd6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:24:18 -07:00
Prabhanjan Kandula
bdfc560f6e disp: msm: sde: extend DNSC validation for wb rotate
Atomic validation checks added for DNSC feature need to
be extended considering WB rotate feature enable.

Change-Id: Iff908da062280418536d00a5fcdeb99939267659
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:24:11 -07:00
Prabhanjan Kandula
c3991049c1 disp: msm: sde: add support for new QoS mode of WB rotation
This change adds support for new dynamic QoS mode for WB rotation
which is required to achieve rotation output available at required
rate to meet real time use case. Though traffic shaper can be
disabled in dynamic QoS mode, part of traffic shaper algo to track
WB operating speed is enabled and WB generates creq priority
based on current ouput rate compared to targetted ouput to help
meeting real time use case requirement.

Change-Id: I98c2dcae53f1b175dc49b40238b9da33e95717a6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:24:04 -07:00
Prabhanjan Kandula
3128214eac disp: msm: sde: add rotation support with writeback block
MDSS 10.0.0 HW is capable to rotate input image in WB hardware
block. WB hardware can only perform rotation of clockwise 90 degrees
and this can be used to achieve the required 2D rotation by adding
appropriate FLIP transformation to the SSPP. This change adds required
software support in display driver to excericse input image
rotation through WB block.

Change-Id: Ia5c2fc84eabb68f29d130333316527b60d02cbc7
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:23:58 -07:00
Prabhanjan Kandula
f3c2c5e37d disp: msm: sde: add WB rotation output color formats
MDSS 10.0.0 HW supports rotation of input image with
writeback HW but output color formats are restricted to
32 bit uncompressed A5X tile formats. This change exposes
the supported WB output color formats to client for WB
rotation usecase.

Change-Id: Ic52e6ee4ab882b7dad6edd0daa91b593afbcae01
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:23:50 -07:00
Prabhanjan Kandula
4cca89d615 disp: msm: sde: add drm properties required for wb rotation
This change installs required drm properties for writeback
connector to implement rotation with writeback hw in mdss.

Change-Id: I85ed359d06ff4bafee85a4bfa5b8a99774311e60
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:22:49 -07:00
Raviteja Tamatam
22a3c5a842 disp: msm: fix display compilation for 6.0 kernel upgrade
Fix display compilation issues for 6.0 kernel upgrade.

Change-Id: Ied1940e653ceaa1de18a8aedeab01197c235603c
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-10-19 11:04:22 -07:00
Linux Build Service Account
c14780557f Merge changes Ibacf0ec3,I7630766d into display-kernel.lnx.1.0
* changes:
  disp: msm: sde: enable second dedicated CWB feature
  disp: msm: sde: add support for IRQs in new CWB Pingpong blocks
2022-10-18 22:36:23 -07:00
Linux Build Service Account
aa5dc72c1d Merge "disp: msm: sde: add changes to support additional dedicated-CWB" into display-kernel.lnx.1.0 2022-10-18 22:36:22 -07:00
qctecmdr
bd2011bab1 Merge "disp: msm: sde: fix typo in trace message" 2022-10-17 19:53:39 -07:00
Narendra Muppalla
666bc432e7 disp: msm: sde: fix typo in trace message
This change fix trace message in sde trace.

Change-Id: I73a873984564f995f84e0c08f9e49164cb67063a
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-10-17 12:02:42 -07:00
Christina Oliveira
cbc6d4a0a0 disp: msm: sde: add support for wait on multiple hw fences
This change adds support to wait on multiple hardware fences by
creating a fence array so each dpu-client only gets signaled until all
the hw fences going to the same ctl-path are signaled. It also
accounts for if a fence is a fence array.

Change-Id: Iba4b1d2b7322aea64dc197ca7655920b79dbb919
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-10-17 12:02:35 -07:00
Amine Najahi
2af644d192 disp: msm: sde: add line counter logging
Add logs to track the read/write line counters
and tear check configuration during key events.

Change-Id: Ife8afecc63a9008a8d9fc746d0ec8579a311b335
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-17 12:01:57 -07:00
Veera Sundaram Sankaran
09b2c937c2 disp: msm: sde: cache cwb enc mask to use during seamless transitions
The cwb_enc_mask is set by the wb phys encoder during the validate
phase and this is in-turn used during the commit phase. During
seamless transition cases like poms with cwb, the encoders are
disabled and then enabled back after the validate phase. The cwb
flags are reset during this time leading to issues. Cache the flag
and reapply it during the modeset to avoid this case.

Change-Id: I5df1be18a5e30bb1107dc0f2e87d771a735f1ab6
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-10-14 02:57:55 -07:00
Shamika Joshi
f3525a4051 disp: msm: sde: enable second dedicated CWB feature
Set the boolean property to enable second dedicated
CWB feature on pineapple hardware.

Change-Id: Ibacf0ec327c5d6d803f1fc5211dedb3a591b441a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-10-13 20:03:59 -07:00
Shamika Joshi
493362f656 disp: msm: sde: add support for IRQs in new CWB Pingpong blocks
For second dedicated CWB pingpong blocks, the overflow irq needs
to be mapped properly to existing IRQ handlers.

Change-Id: I7630766d1865f7ad7079947185ef4ae629d71f3e
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-10-13 20:03:26 -07:00
Shamika Joshi
b9553cf5f3 disp: msm: sde: add changes to support additional dedicated-CWB
Update the hardware blocks and corresponding APIs
to configure new D-CWB data path. Add new hardware
pingpong blocks that are dedicated for second DCWB.

Change-Id: I529c24ac5aa483f30b6c9e7653eb1713c6b8fb8a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-10-13 20:02:57 -07:00
qctecmdr
eb15d0d825 Merge "disp: msm: sde: enable dsc full ICH error precision" 2022-10-10 13:49:32 -07:00
qctecmdr
d92a44d525 Merge "disp: msm: sde: enable 32bit intf te registers" 2022-10-10 13:49:32 -07:00
Nilaan Gunabalachandran
719e3a8e1d disp: msm: sde: upstream memblock_free API returns void
The memblock_free API has been updated to return void. This
change removes the check on return and passes the pointer
address in correctly.

Change-Id: I8b60c8d3c5e3e8c2f94e33015c2c03686a556807
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-10 11:50:33 -07:00
Nilaan Gunabalachandran
a0f3537872 disp: msm: sde: include file.h
This change adds includes for <linux/file.h> required for the
display driver in kernel 5.19.

Change-Id: Ibe5401997b43844b692869ebb6d28faa7bcb7740
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-10 11:21:55 -07:00
GG Hou
61359169c5 disp: msm: sde: implement format_mod_supported API
This change implements the drm_plane_funcs API format_mod_supported
necessary to correctly check if format modifiers are supported.

Change-Id: I39a26f7b053c44ef7577401d88e7cf6934c198f8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-10 11:21:30 -07:00
GG Hou
45b0891612 disp: msm: sde: replace the allow_fb_modifiers variable
The allow_fb_modifiers variable has been replaced by
fb_modifiers_not_supported. This value is disabled by default
so no additional initialization is necessary.

Link: https://patchwork.freedesktop.org/patch/msgid/20220128060836.11216-2-etom@igel.co.jp

Change-Id: Id738be53ce1133232f525b75ec0b678ce777eff7
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-10 11:20:12 -07:00
Nilaan Gunabalachandran
c348513806 disp: msm: sde: enable dsc full ICH error precision
This feature enables using all available bits when ICH
error calculations are made. This improves precision and
image quality when there are more than 8 bits per component.

Change-Id: I851f05418283d0e731332d4069e3b6e57487b9a3
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-06 13:51:52 -07:00
Nilaan Gunabalachandran
f73f15ae39 disp: msm: sde: enable 32bit intf te registers
This change adds support for INTF TE using 32 bit values and
single update per TE. These features help ensure that during
QSync mode the TE does not overrun in certain late trigger uses.

Change-Id: I893d0cde81320c3f17604694a4d8ee52b29a9425
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-06 13:51:35 -07:00
Nilaan Gunabalachandran
00369e3266 disp: msm: sde: enable mdp vsync frame count
Currently, the driver uses the panel frame count along with
mdp vsync timestamp which can be unreliable if there are any
latencies. This change adds support to use mdp vsync frame
count, if the hardware supports it.

Change-Id: I784d4f4e525212269371a40071bcb912181cba9f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-06 13:51:29 -07:00
Nilaan Gunabalachandran
875db134b3 disp: msm: sde: add pineapple mdss version support
This change adds pineapple mdss revision and enables features
based on the hardware capabilities.

Change-Id: I930e1ffd8e070f5bd258e5d3e441a966ade5f760
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-06 13:50:35 -07:00
qctecmdr
e567bba0d5 Merge "disp: msm: sde: detach dsc/vdc encoder blocks properly during modeswitch" 2022-10-04 14:30:33 -07:00
Gopikrishnaiah Anandan
5edd5553a9 drm: msm: disable LTM hardware during encoder disable
LTM block should be disabled when encoder is being disabled to avoid
display hang when all driver clients have been closed.
Change disables LTM hardware block when encoder is disabled.

Change-Id: I279296b566ab93c302e6166b6fa4b7197c2cc0ab
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
2022-10-04 01:49:57 -07:00
Yashwanth
a14aea9aac disp: msm: sde: detach dsc/vdc encoder blocks properly during modeswitch
In the current code if there is a switch from DSC to non-DSC
mode, all the DSC blocks attached to the sde_encoder are not
cleaned up properly. Due to this, during virt disable these
DSC blocks are disabled and flushed resulting in underruns
on other ctl paths which might be using them. This change
properly cleans up all the dsc/vdc attached to the sde
encoder to avoid such issues.

Change-Id: Ie644701cbda6b4d056bc7ef30300be96096c5214
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-09-30 01:39:15 -07:00
Linux Build Service Account
9fbbeb65ba Merge "disp: msm: sde: move some frame_events from crtc commit to event thread" into display-kernel.lnx.1.0 2022-09-23 12:20:26 -07:00
Veera Sundaram Sankaran
58bff0115e disp: msm: sde: move some frame_events from crtc commit to event thread
Move frame data stats collection/notification during frame-done and
retire fence sysfs notification to event thread. This will free up
some interrupt time.

Change-Id: I2648ac4287ce8712e9a059edd408a59753aa6d32
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-09-23 11:48:34 -07:00
Veera Sundaram Sankaran
2139b617bf disp: msm: sde: fix crtc count based on layer mixer
Fix the max crtc count based on the number of real layer mixers
available. Usermode can use the crtc count to derive the number
of layer mixers. This will be used in usermode to check if a new
DP/IWE/WB session can be supported by the HW, based on the existing
displays at that point. This will avoid atomic_check validation
failures in driver.

Change-Id: I63b033604ac549fc01bccef2a9320e0befab5926
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-09-23 11:48:21 -07:00
Linux Build Service Account
5d2c1a0801 Merge "disp: msm: sde: expose cdm block count through connector" into display-kernel.lnx.1.0 2022-09-23 11:36:44 -07:00
Linux Build Service Account
c5ffc48adf Merge "disp: msm: sde: avoid connector remove in dual display recovery" into display-kernel.lnx.1.0 2022-09-23 11:36:42 -07:00
Linux Build Service Account
25d6c5aab9 Merge "drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs" into display-kernel.lnx.1.0 2022-09-23 11:35:41 -07:00
Raviteja Tamatam
45a1db8361 disp: msm: sde: avoid connector remove in dual display recovery
Add changes to get drm object reference for connector and
remove out fb in dual display recovery case.

Change-Id: I1fd0c4818575b3f532d51ad41285031e8320c5fe
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-09-21 11:17:52 -07:00
Gopikrishnaiah Anandan
4ee3a1a5e2 drm: msm: re-enable driver disabled color features
When encoder is disabled, demura is disabled since pipes
are disabled internally.
Change marks the features which were active and disabled
by driver as dirty so that it can be applied in the next commit.

Change-Id: I805d17d673a8ff41f9bdb18ba7f2fd185b5ccb5a
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
2022-09-21 11:02:43 -07:00
Veera Sundaram Sankaran
8602fee9f8 disp: msm: sde: expose cdm block count through connector
Expose the number of cdm blocks available through the connector
capabilities. Add CDM to the topology_control table, so usermode
can use the property to reserve the CDM block during modeset.
Additionally, fix a error code return during CDM block reservation
failure in sde resource manager.

Change-Id: Ib42ca4e8614076a8e5df77d8abc77a9e73674390
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-09-21 11:01:17 -07:00