Commit Graph

1612 Commits

Author SHA1 Message Date
Narendra Muppalla
f014267f93 disp: msm: sde: update vsync soure as part of post modeset
This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.

Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-05-03 15:02:54 -07:00
Nisarg Bhavsar
75aedb1c53 disp: msm: Address static analysis issues
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.

Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-04-28 11:53:38 -04:00
qctecmdr
b0aa8dbb0f Merge "disp: msm: sde: add support for LLCC_DISP_1 SCID" 2022-04-26 13:11:31 -07:00
Amine Najahi
bffdc0271d disp: msm: sde: add support for LLCC_DISP_1 SCID
Currently only LLCC_DISP SCID is used to read and write to
system cache during static display use case.

This changes adds SCID LLCC_DISP_1 to allow each SCID to
have a dedicated function (read/write).

Change-Id: I5604ec1183d99a8492b005ec06ac94e5db60b5f7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-26 10:29:29 -04:00
qctecmdr
2ed5675910 Merge "disp: msm: sde: convert system cache boolean to feature bit" 2022-04-26 06:38:24 -07:00
Amine Najahi
50092909c0 disp: msm: sde: convert system cache boolean to feature bit
Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.

This change converts it to use a feature bit instead.

Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-25 16:33:00 -04:00
Amine Najahi
edd8be4319 disp: msm: sde: log SCID during LLCC activation
Add SCID to event log and debug print during LLCC activation.

Change-Id: Ib4c0a68506e9620ca42aba03db35c9ee21eda6dd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-25 16:32:53 -04:00
Bruce Hoo
02e97873a2 disp: msm: merge flag of register and dbgbus
Merge reg_dump and dbgbus dump flag into dump_mode, and bring
back debugfs node "evtlog_dump" to keep flexible controlling
of evtlog.
Set in_mem option as default dump mode, since in_coredump
option will be enabled once HW recovery feature is enabled.

Change-Id: I75de1a69b01594b652479bf79201591ac0bf62e5
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
2022-04-25 08:07:46 -07:00
qctecmdr
13d8ca3148 Merge "disp: msm: sde: change ubwc revision" 2022-04-22 23:08:47 -07:00
Amine Najahi
3cfd52c905 disp: msm: sde: enable vsync irq during sys cache read work
Currently, when doze mode is enabled the encoder off work
worker is started 1 ms after idle power collapse because of
aggressive idle-pc feature. This causes the system cache
worker to start after the clocks and vsync interrupt are disabled.

This change independently enables clocks and interrupts during
system cache work thread to decouple it from the encoder
off work sequence.

Change-Id: I8ed172b0e7c5c8e4e270e768434301d972e90eb9
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-20 13:23:06 -04:00
Shamika Joshi
b2f0c90aca disp: msm: sde: change ubwc revision
UBWC revision is in the expanded form, no need to process it again.

Change-Id: Ie4aafeea5459a76f325a07e58af1de5665fe45ba
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-04-19 09:32:11 -07:00
qctecmdr
99e41b7489 Merge "disp: msm: sde: reset plane cache state on plane disable" 2022-04-11 16:47:35 -07:00
qctecmdr
97c6db4693 Merge "disp: msm: sde: use LLCC_DISP for static display usecase with cwb" 2022-04-10 07:19:01 -07:00
qctecmdr
efb465749b Merge "disp: msm: sde: handle SSPP system cache for multi-plane scenario" 2022-04-10 03:21:03 -07:00
qctecmdr
cb6ce492b5 Merge "disp: msm: sde: update HFC layer checks" 2022-04-09 16:51:07 -07:00
qctecmdr
95eb4d982c Merge "disp: msm: sde: add the DE lpf flag setting" 2022-04-09 13:24:42 -07:00
qctecmdr
6e5db7e5eb Merge "drm: msm: add spr by pass support" 2022-04-09 13:24:42 -07:00
Veera Sundaram Sankaran
c5121825bf disp: msm: sde: reset plane cache state on plane disable
Plane cache state is updated based on the crtc's cache state.
The plane is left with state cache state, if the particular plane
is not used in the subsequent frame by the same crtc. Reset the
plane cache state on plane disable and reset_custom_properties to
avoid this case.

Change-Id: Ic6d31567af23906e94c5404d1d366e030b9be199
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-06 10:51:24 -07:00
Veera Sundaram Sankaran
65b81f914e disp: msm: sde: use LLCC_DISP for static display usecase with cwb
Static display usecase uses concurrent writeback path to compose the
layers and updates the primary display in the next cycle with cwb
output. Use LLCC_DISP scid for system cache in cwb path, to keep it
in sync with the legacy static display path. Use LLCC_DISP_WB for
the offline-wb path. Expose the writeback connector cache property
only when either or both the cache types are enabled.

Change-Id: I8ca4b14828a14ce0bde829136fb4baef272166aa
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-06 10:51:24 -07:00
Veera Sundaram Sankaran
beeab715ac disp: msm: sde: enable LLCC_DISP_WB for kalama target
Add sde hw catalog change to enable LLCC_DISP_WB system cache, which
is used for 2-pass composition usecases with offline writeback path.

Change-Id: Ic320b95a6699e59c62fed41f7fb88c484d98ffd0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-06 10:51:24 -07:00
Amine Najahi
05014b30d1 disp: msm: sde: handle SSPP system cache for multi-plane scenario
Currently, when CWB system cache use case is enabled and multiple planes
are used to fetch the LLCC data only one SSPP is programmed correctly.

This change ensures that whenever the fb_cache_flag is non 0, the SSPP
system cache gets reprogrammed.

Change-Id: Ic90eaae207f6221efb1fc8749093d8b44e092e44
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-04 07:07:49 -07:00
Rajesh kv
03aad2fdf9 disp: msm: sde: add line insertion support for sspp
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.

Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
2022-04-01 09:35:03 +05:30
qctecmdr
fdcfe00b0b Merge "disp: msm: sde: drop suspend state if commit is skipped" 2022-03-31 17:23:16 -07:00
qctecmdr
0d5e286187 Merge "disp: msm: sde: shorter idle-pc duration in doze mode" 2022-03-31 17:23:15 -07:00
qctecmdr
e84f1b6640 Merge "disp: msm: sde: disable autorefresh on encoder disable" 2022-03-31 07:49:19 -07:00
Veera Sundaram Sankaran
3112cb87dd disp: msm: sde: fix sde_vbif_get_xin_status return value
sde_vbif_get_xin_status is expected to return true if client is idle
and false otherwise. Update the final return status based on this
expectation.

Change-Id: I3a9ff7c83cb5966ff5573b27e5c2e88423448199
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-03-29 12:16:17 -07:00
Veera Sundaram Sankaran
e50d08286f disp: msm: sde: disable autorefresh on encoder disable
Disable the autorefresh during encoder disable to avoid any
pending frame transfers while disabling. Additionally, handle
frame_done for new autorefresh frames to signal the fences and
proper accounting of pending_kickoff counter.

Change-Id: I8af114972b19ccdf0edab6b4c454ee90b4e8d8cf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-03-29 10:41:46 -07:00
Yu Wu
6e050f641a disp: msm: dsi: Remove backlight operation during poms process
During POMS process, from vid to cmd or from cmd to vid, we both
see black screen, this is caused by backlight operation. Logically
display driver should not operate on backlight during POMS process.

Change-Id: I3bc76d6ed9ccee50f740c36cb276b6b103e7d43e
Signed-off-by: Yu Wu <quic_zwy@quicinc.com>
2022-03-28 00:36:32 -07:00
qctecmdr
cba5134cac Merge "disp: msm: sde: address static analysis issues" 2022-03-25 23:49:17 -07:00
Nisarg Bhavsar
4d8bf011d5 disp: msm: sde: address static analysis issues
Avoid various possible nullptr dereferences
and check validity of index before accessing
arrays. Addresses issues highlighted by
static analysis.

Change-Id: I5abfbc8c4cacb56e9decc3a6339ab0fa3a63b606
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-03-25 13:26:33 -07:00
qctecmdr
89422fbde1 Merge "disp: msm: sde: enable llcc in AOD mode" 2022-03-25 12:06:36 -07:00
Govinda Rao K S
1928128776 disp: msm: sde: enable llcc in AOD mode
LLCC usage is currently limited to static display
configuration. With these changes, LLCC will be
enabled for always-on screen with Video mode.

Change-Id: I54cbb6f0aa6380819ca00e02ac8ffd1c01d07ede
Signed-off-by: Govinda Rao K S <quic_gkarikur@quicinc.com>
2022-03-25 09:09:42 +05:30
qctecmdr
51f0c1bd0b Merge "disp: msm: sde: install default value for panel_mode property" 2022-03-24 20:13:01 -07:00
qctecmdr
67c4ea24a4 Merge "disp: msm: add capability to dynamically update the transfer time" 2022-03-24 07:56:56 -07:00
qctecmdr
07a272bcb8 Merge "disp: msm: sde: remove hardcoding of LLCC use case id" 2022-03-24 04:19:48 -07:00
qctecmdr
41505c6109 Merge "disp: msm: sde: refactor _sde_encoder_phys_wb_update_cwb_flush function" 2022-03-23 00:39:24 -07:00
Amine Najahi
213997b2c9 disp: msm: sde: remove hardcoding of LLCC use case id
Remove hardcoding LLCC use case id and use catalog information
to decide which system cache section to use.

Change-Id: I9748ca1f3569db0cf77689af296def0759fe94cc
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-03-22 11:15:14 -04:00
Nilaan Gunabalachandran
e5fcf7f263 disp: msm: add capability to dynamically update the transfer time
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.

It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.

Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-03-21 14:13:32 -04:00
Govinda Rao K S
c35cbdda4f disp: msm: sde: shorter idle-pc duration in doze mode
Currently aggresive idle-pc entry is only enabled in
case of doze-suspend mode. Extend the support to doze
mode as well.

Change-Id: I8e9e0e116bb65a1aec0180bf9bc10bed99d4a137
Signed-off-by: Govinda Rao K S <quic_gkarikur@quicinc.com>
2022-03-21 02:14:55 -07:00
Renchao Liu
34fa5b131a disp: msm: sde: add the DE lpf flag setting
Change adds the DE lpf flag setting and updates its register write.

Change-Id: Ifdfd26ef51dd66293fe99f25fef79c5e76e9ca31
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
2022-03-21 16:50:36 +08:00
Shamika Joshi
d66d6a1a71 disp: msm: sde: refactor _sde_encoder_phys_wb_update_cwb_flush function
Refactor the function '_sde_encoder_phys_wb_update_cwb_flush' to
reduce its complexity.

Change-Id: I91b5fd5409617d06c3c17799d6af128578c3ba16
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-03-18 18:30:37 -07:00
Lei Chen
ffcdd853a5 disp: msm: sde: install default value for panel_mode property
Install default panel mode for connector panel_mode property
so that the panel mode can be changed to default mode accordingly
when SDM is restarted.

Change-Id: I3229a1b8e60da9030d6e20112f6b1f3071b5f988
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
2022-03-18 00:44:18 -07:00
qctecmdr
33ed6045ac Merge "disp: msm: sde: remove WB output buffer pitch alignment check" 2022-03-17 15:54:13 -07:00
qctecmdr
2884396664 Merge "disp: msm: sde: avoid null pointer dereference" 2022-03-17 15:54:12 -07:00
Amine Najahi
cc19682733 disp: msm: sde: remove WB output buffer pitch alignment check
Currently, driver enforces the allocated WB output buffer to be 256 bits
aligned in memory in order to optimize DDR access and meet maximum system
bandwidth requirements.

Since there are no functional failures with using a 256 bits unaligned
buffer, this change removes this unnecessary check.

Change-Id: I23476e8a28e970f2e1853bbcc0c1d1042d9fdfe2
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-03-17 16:09:09 -04:00
qctecmdr
96782a0d63 Merge "disp: msm: sde: program master intf register for single intf" 2022-03-17 07:48:44 -07:00
Nisarg Bhavsar
a9c8b41adf disp: msm: sde: avoid null pointer dereference
Avoids null function pointer dereference in WriteBack object.

Change-Id: I9f23a7f9f5e72e09cfd7a955d0c0ca64b401f89e
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-03-16 11:41:18 -07:00
qctecmdr
aea34b4fd7 Merge "disp: msm: sde: enable tui flag in catalog for kalama" 2022-03-15 19:54:04 -07:00
Raviteja Tamatam
3555dc45ca disp: msm: sde: enable tui flag in catalog for kalama
Enable trusted vm flag for kalama target

Change-Id: I2f2c0a838914d5fccf6642690c082c592e04e38d
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-03-14 15:23:07 -07:00
Raviteja Tamatam
2d4e001512 disp: msm: sde: SID programming for new MDSS
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.

Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-03-14 15:21:56 -07:00