DSI controller and clock will be disabled/enabled during panel mode
switch, so disallow backlight update during panel mode switch to
avoiding DSI exception.
Change-Id: I37e2f3c9aa929555593ffb53950521150ee7698f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Make sure that cmd dma done mask is set before sending
dma commands. This will make sure that we don't timeout
if the refcnt's are not properly handled. Many oem's
have their own customizations around this which maynot
handle the refcnt's correctly.
Change-Id: If7f5ed1fae20b57f6e9147cae2caa3c5097466c9
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For command mode panels, if a dynamic mode switch occurs on
the first frame, the current code skips DSI controller initialization
and registering for error handlers. This causes the software state
to be uninitialized for DSI CTRL, resulting in command transfer
failures and eventual crash. The change ensures that initialization
is complete even if the DMS occurs on first frame.
Change-Id: I83e3336f7c09424b6c7b95826c30b37974ec29ab
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add this change to ensure that DFPS and RFI happen in the
same panel mode for avoiding unexpected panel mode switch.
Change-Id: I6783b320e73a88e8f75cb83bcce85e50f798b6ab
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Reject composition if panel mode switch is requested
during power on/off commits.
Change-Id: I3a5b28fd9f5bd927537824033a1c8dc838366d5b
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Avoid esd check during pm_suspend state because core
clock enable will fail. This change adds additional
check and also adds the clock enable failure check.
Change-Id: Ie8bfa4f74d323ff15a07fb037675f07ab942f016
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
It should not be an error that panel mode isn't specified
in timing node, so add this change to lower the log level
from error to info.
Change-Id: I49bd1fec1c09697d9829a8e0767dfa3cf2cff512
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For constant fps feature, porch is calculated based on supported
clk rates. Currently, data type of local variables used for porch
calculation is u32 which leads to incorrect porch calculation for
higher clk rates. So, update the data type to u64.
Change-Id: I8eb04487d1dcce05989448c0b063e56752af412b
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add changes to support dynamic switching of dsi clock feature for
phy ver 2.0. This helps to avoid RF interference with DSI clock.
Change-Id: I69958d9224665296cc0f272e39dcdfcefbe293d4
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For video mode panels, async wait feature for DCS command
transmission may not always be reliable as additional programming
would be needed to ensure that the DCS commands are correctly scheduled.
Until this feature is properly implemented and validated, disable this
for video mode panels to avoid potential DSI command transfer
failures.
Change-Id: I18c853bc5607cc1cc523b36f6f346b213911c1a9
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change will be removing checking and clearing dsi cmd done
interrupt in commit thread and in workqueue context, which
can race with dsi isr, when it tries to clear the interrupt.
Change-Id: I96e7f8dffed1af3cec0c7668ab1729337d4b260e
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
There is lag or lead in the FPS during dynamic clock change,
along with the increment or decrement in clock. So, HFP or
VFP are adjusted to ensure a constant FPS.
Change-Id: I87ba7a185104a0f5f1d13734a7e487e728d6b2c0
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change parses SPR enable entry from panel device tree and
populates SPR specific information in panel data structure.
Valid entry of SPR pack type is treated as panel requirement
to enable SPR for specified pack type from source end. This change
also populate connector capabilities blob with SPR pack type.
Change-Id: I9d9ab8a990476fba281e12890bf3f7b17a174d79
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
DSI host vsync is expected to align with panel internal vsync
during transition from command mode to video mode operation.
In order to facilitate this, keep panel TE enabled in video mode
operation until it is aligned with vysnc.
Change-Id: I3fc59b01336b30cd436be332af6953c5a01be7fd
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Change fixes parsing of software TE tag added to the display
name from bootloader.
Change-Id: I4747cc6eff43d681477150d6cad7a737963bf11c
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Check against the max clk_type and clk_state enumerations before
to validate the type and state of DSI clocks to avoid Control
Flow Integrity issues.
Change-Id: Id53465c2b12debb1b356c0c91064eb017c2ca30d
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change fixes issues which causes corruption for dual dsi
dsc panel. It fixes the number of slices configured on
dsc hw block and handles deriving correct picture width from
mode timings. Additionally it fixes the core max buffer sizes
used by the hw block.
Change-Id: Iec0ef80528425ffcb5f29d469bd181eb7040de16
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
The clock framework nulls the clock hardware init data, after a variant
of clk_register is called on the clk_hw pointer. This results in a null
pointer dereference when we try to call set rate in the PLL prepare
function. The call can be a direct call to the function rather than
trying to access through the init_data pointer of the clk_hw.
Change-Id: I3613eea915d4f5620d7f0258ae391ad2ac624148
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.
Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.
Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add a generic API which calculates the horizontal timings based
on the compression type in case compression is enabled and even
for non-compression cases.
Replace the usage of the DSC macros with this generic API.
Change-Id: Ie9174c20adc51a0be7c9127529d41faa4b473b55
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support to configure the DPU pipeline to support VDC-m
topologies.
Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add the support to program DSI compression registers
for VDC-m. These are calculated based on the VDC parameters
and mode information.
Change-Id: I09b163a496842331d5f2a78371f380180b3a15b8
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support for PPS command for VDC-m. This shall be sent from the
encoder to the decoder such that both can produce the same model
state.
Change-Id: Iae48615eab7c91ef7ecc68b84334057de5090364
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support to calculate the parameters needed to configure
the VDC-m encoder. These are also needed to configure the PPS
command which shall be sent to the decoder.
Change-Id: I36db93f7555aee34b5b893e389a7eb88d0e05f68
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support for parsing VDC-m DTSI parameters and also
perform basic validation checks on those.
Change-Id: I4b13cf04b1500c3c801c227658cb787bdad6174f
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This change enforces dp, dsi and the sde drivers to use the
drm framework defined dsc_config data structure. As a part of this,
it introduces the sde_dsc_helper API to configure the dsc params
and creating a PPS command. Earlier each driver implemented it's
private versions leading to duplication of code. Additionaly the
helper api supports DSC spec 1.2 422 and 420 mode.
Change-Id: I25933fab08cdabbc6787079926885d1a78945e97
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change takes care of swapping the byte order in
the packet header to work with MSM hardware.
Change-Id: I38b92a277aa4677d53e263ce343721b8f2b48497
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Use the DRM APIs for walking the list of connectors. This ensures
the proper locks are taken to prevent possible corruption by other
threads.
Change-Id: Iacdd1c6ad8eab224ceac550e0229489851a09706
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
DSI PLL is tightly coupled with DSI PHY. This change removes
separate DSI pll driver and makes DSI pll as a subnode to DSI
PHY which is an accurate way of representation. In addition, this
change adds support for 5nm DSI ctrl and PHY revisions and adds
DSI pll support for 5nm. Remove support for older DSI pll revisions
such as 7nm, 10nm, 14nm, 20nm, 28nm.
Change-Id: Ic8b886a9fe24b906e4ec5130720600efa1e59b68
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
DSI driver did not use msm bus scaling setting,
remove the code.
Change-Id: I71675c8f4e3e97f1ded72ecac3fa87bdc7fb3774
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
This snapshot change adds downstream support
for drm 5.x+(msm_lahaina branch) linux kernel.
Change-Id: Ia691c95da155a00e449c91a2f1a5b20a8e71aed4
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change ensures that if the dsi clock rate is not specified
in the timing modes, setting clkrate_change_pending is not bypassed.
Change-Id: I2475da1e548f29c68a6a4466c5ef540f7f11d553
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The current solution triggers the DMA command and waits till
the command dma done and ISR signals completion. This change
introduces asynchronous wait after a DCS command has been
triggered. Enable this mode only during pre kickoff, so as to not
block commit thread.
Change-Id: Iead7b6328883e844147d47ff68dc878943879553
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
