Commit Graph

97 Commitit

Tekijä SHA1 Viesti Päivämäärä
qctecmdr
ebc9eee2ac Merge "msm: eva: Increasing wait time to acquire xo reset" 2023-11-09 01:59:04 -08:00
qctecmdr
00b9a53e95 Merge "msm: eva: Revert to 80us before XO de-assert" 2023-11-08 09:41:23 -08:00
George Shen
dc5c927020 msm: eva: Add QDENY and QACTIVE checks
During CPU NoC LPI sequence. Print more debugging registers
in case LPI QACCEPT is not set after 20ms. It indicates a pending
transaction lingering around. Adding dump for NOC registers.

Change-Id: Ied58e52e30572074be77b4d51a03fb4194d78caa
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-11-07 00:31:21 +05:30
George Shen
3454357c09 msm: eva: Revert to 80us before XO de-assert
Revert back 200us sleep to 80us before XO de-assert.

Change-Id: I8446aa2eb5cfac32fdc5fc971ddd37b999623bf8
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-11-07 00:15:49 +05:30
Palak Joshi
7761c7c52d msm: eva: Increasing wait time to acquire xo reset
Waiting for 1sec to acquire xo reset else BUG_ON.

Change-Id: I26bcc27d02b4104f36b1bcdac97cb784c1daca44
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
2023-11-07 00:09:31 +05:30
Palak Joshi
65910f2681 msm: eva: Added QOS registers settings
Changes made to accommodate difference in QOS & NOC
base registers offsets between pineapple and cliffs.

Change-Id: If8c631480d1f09bac21de52d0f27f0c29cdf594e
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
2023-11-02 21:01:30 -07:00
George Shen
d2c57a156b msm: eva: Add delay after resetting xo clk
Wait 200us to 300us.

Change-Id: Ia3d83b18a8b1c8fe351ab9fcd7a0ec3ed1b9822a
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-10-06 09:43:17 -07:00
George Shen
4db4b2a5fa msm: eva: Add missing QOS setting
Fix wrong QoS setting for RGE and GCE.

Change-Id: Ibd156b4133c9027ec7ab7c383c86f81ef9d744e3
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-09-14 08:39:23 -07:00
George Shen
8adf2c6b69 msm: eva: Map dsp hfi queue using dma alloc api
Use dma_alloc_coherent to allocate 4MB dsp hfi queues and map
them in non-io-coherent way.

Change-Id: I6d8adb58ebcddae569259862a83e3aeffa3d2304
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-08-21 23:18:59 -07:00
George Shen
f79b5db5ae msm: eva: Reduce session creation delay
by one milisecond at least.

Change-Id: Ia32840d2a47533aa81ff3b31af5404b1636b546b
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-08-16 11:36:49 -07:00
George Shen
b293b5b713 msm: eva: Rename hfi related devices
To avoid confusion in code reading and prepare for
future compatibility changes.

Change-Id: I43d61e18d2e2d75d1fd46ceb2e763511329ee32d
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-07-29 16:34:22 -07:00
George Shen
936925471d msm: eva: Enhanced check to avoid kernel panic
Avoid delete non-existing session and power on check before
register write.

Change-Id: I0b7d5045d68fd18e5a9a041d3ad3e37f4dac16ad
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-07-29 12:09:46 -07:00
George Shen
1741a5b55c msm: cvp: Avoid racing in bw voting
when SSR is releasing core and some clients voting for bus.

Change-Id: I8575d747c17f234bbce216c346843ab07ea6b340
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-07-18 18:41:32 -07:00
George Shen
deb4fd788e msm: eva: Remove unused test bus dump
Avoid NoC error during smmu fault handling.

Change-Id: I4b6e4314c6d95bed1c89754955f1ffc975c74d48
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-07-18 08:31:15 -07:00
George Shen
ea94318515 msm: eva: mmap firmware debug memory
For user mode to save into a dump file. It helps FW debugging.

Change-Id: I1c9c52d27d0dfd20e3eeb54b203416f6df095c8d
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-06-20 14:14:02 -07:00
George Shen
aafc38db81 msm: eva: Condition ready check for IRQ_MASK
Core shall be powered on and WRAPPER_SPARE bit 1 shall be clear.

Change-Id: Id225c44f4a245482a8b9387109211461d03042e9
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-06-16 13:37:20 -07:00
Palak Joshi
0eedd436e1 msm: eva: Identify the actual number of silver cores available with target
As PM QOS request needs to done for silver cores only for EVA and
number of silver cores would be different for different target so,
better to identify the actual number of available silver cores.
Added cpu_possible check to confirm if cpu is available or not.

Change-Id: Ibccc7688200732c3c666041a8fe414b4f2818993
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
2023-06-05 03:29:31 -07:00
George Shen
304e2cf9c0 msm: eva: Allocate 1MB debug buffer for FW
For FW to hold debug info. Simplify driver structure for easy
dump in T32.

Change-Id: Ib310a3d9fe3437d5ce49783eb813fbb2d8bd3216
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-06-02 14:40:35 -07:00
George Shen
df291cad83 msm: eva: Give EVA IRQ thread realtime priority
To ensure consistent EVA feature performance.

Change-Id: I8068984bb677b7eef388b114efc36520be9f8d76
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-06-02 10:01:55 -07:00
George Shen
43c37a29e1 msm: eva: Send EVA session error to UMD
Through POLL SSR event, only notify the error session. Other
sessions will not be impacted. This is different than SSR
handling.

Change-Id: I5acb4e21c19909b16350816621ae085d54fe05ac
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-06-01 08:36:30 -07:00
George Shen
37a21d759b msm: eva: Recover EVA SMMU fault
Needs extra change to enable EVA SMMU fault. This change clears
all the obstacles to achieve the goal.

Change-Id: Ia93ff2132ff53741f3c20d4271083f6f93824cac
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-05-23 10:06:11 -07:00
George Shen
115a7bf5c7 msm: eva: Enhance power and perf logging
Use CVP_PWR instead of CVP_PROF.
Add AON timer reading.
Avoid SSR if core init failed.

Change-Id: I1dd40edc893009a2f2794e3431bb08398ec6352b
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-05-16 11:09:28 -07:00
George Shen
73f3cecfbd msm: eva: Support Synx V2 only
Simplify code base for future generations of driver.

Change-Id: I9ed940184da3b2224c74092ac31163de29c84f64
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-05-02 10:06:41 -07:00
George Shen
4e3d3a91bd msm: eva: Change FW boot sequence
Match MPTest sequence to facilitate presilicon bringup.

Change-Id: Iafd4443eb0f9d6045e61eb2dd33b6663dc3f1334
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-04-28 15:22:11 -07:00
Jingyu Su
564ed96df0 msm: eva: fix KASAN stack-out-of-bounds issue in __iface_cmdq_write_relaxed
Change-Id: Id5b07cf778804ac7865f150e72331be6e94cb80d
Signed-off-by: Jingyu Su <quic_jingyus@quicinc.com>
2023-04-25 09:58:09 -07:00
Palak Joshi
00f7039e3c msm: eva: Added EVA FW/HW hung detection mechanism using WD ISR
Recovery mechanism is added to invoke SSR when WD ISR is triggered.

Change-Id: I6f7a289f822c6f1a50494cd6a4855a2c3ba2cc72
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
2023-04-14 01:33:58 +05:30
George Shen
2532f316af msm: eva: Use correct error code in __dsp_suspend
Incorrect error code misleads driver to trigger SSR.

Change-Id: I6e64c6b79be973c4e5b0b9968dc3b952855a2004
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-04-11 10:31:22 -07:00
George Shen
815ffdf422 msm: eva: Fix NoC Hang When accessing NoC
Acquire xo_reset before accessing CVP NoC. There is a chance the NoC clock,
XO clock is disabled during XO reset. Acquiring xo_reset will block the
XO clock reset.

Change-Id: I51ab201beafbd1a4b998ee33a9d23c1efa3e2a14
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-04-10 21:58:52 -07:00
Jingyu Su
cde58caa65 msm: eva: Remove two calls to qcom_clk_set_flags() in cvp_hfi.c
Change-Id: I6ffd3e045999ce701825aaec66f38255fd98cff2
Signed-off-by: Jingyu Su <quic_jingyus@quicinc.com>
2023-04-06 17:06:35 -07:00
George Shen
dcaf2dcdfb msm: eva: Remove unused dsp power flags
Avoid mis-use of old flag that could lead to failure in
powering collapse EVA when a session becomes idle for 3s.

Change-Id: I954bc0972b1f627b274b78659c34626127619af5
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-03-21 14:13:07 -07:00
Palak Joshi
a33d13c191 msm: eva: Updated error handling in case of core init fails.
Removed release and disable subcache in case of core init fails,
as subcache deinit is done as part of load FW failure error handling
and also as part of unload FW.

Change-Id: Ic1a6bf75eacaa8a4ccb95a7155e720932a372a58
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
2023-03-20 23:27:56 -07:00
Sabharsh Sidhu
db7c8ad719 msm: eva: Add CVP_CMD debug logging
Add cmd logging functionality as an
alternative to pkt logging. This has
advantages related to log dropping
and log mangling.

Change-Id: I0ff6801445821e1224f83fa7e2eb8bf8a849962b
2023-03-17 15:17:23 -07:00
George Shen
f466a36b98 msm: eva: Print SID programming registers
During SMMU fault.

Change-Id: Ic66736ed5d5c97ec6344c295c0ec0f1ca01cf19a
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-03-16 11:34:49 -07:00
Nagesh Gunna
79c9987bbe eva-kernel: hfi q info at session timeout
Printing hfi q info at the of
           session queue time out to get debug
           info on missed cmd/frame pkt.

Change-Id: I9b324a6496699272f9f1b9cb794f3e322d5421ae
Signed-off-by: Nagesh Gunna <quic_ngunna@quicinc.com>
2023-03-15 19:10:24 +05:30
George Shen
264f4c7c0d msm: eva: Add session start/stop through FW
New HFI allows FW stop session and notify driver of
its completion. Driver is safe to reclaim resources
allocated for the session.

Change-Id: Ic6a08334a0bafd57f366a635c53f4f5f8f31f77e
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-02-25 14:58:02 -08:00
George Shen
fe87e8f0fa msm: eva: Add AON Timer mapping for fW
Reorganize the way to store FW required register mappings.
It will make future error check and debugging easier.

Update MID value to name translation table.

Change-Id: I6e3dbd837f2f2c297af16152754f27242aeb2637
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-02-13 14:17:51 -08:00
George Shen
608f7035b6 msm: eva: moves synx_recovery ahead of f/w loading
Before booting f/w, synx_recovery() shall be called as part of
SSR.

Change-Id: I1d03f073c964eaf5b26dd4fec5aac88b7d9de1a8
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-02-09 16:41:01 -08:00
George Shen
5d1307dda2 msm: eva: Checks clocks before accesing NoC
Checks AHB, MVS1, MVS1C, SLEEP, XO clocks, ensure they are
turned on before initial accessing NoC registers.

Change-Id: I429e2e410ac29aab893b490dbbd985914843ed9b
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-02-06 15:10:36 -08:00
George Shen
26bf3dba95 msm: eva: Update QoS, SMMU debug register offsets
SMMU debug register block was relocated. New QoS registers was
introduced. Without the change, S1 fault will end up as S2 fault.
The EVA driver cannot dump appropriate debugging info.

Change-Id: I5e833cee51a56164f7853baa91e8c6011ec41189
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-01-24 15:49:38 -08:00
George Shen
5c1c699cc1 msm: eva: Release resources after core init fail
Change-Id: Ic19fc13405c570a8747ce17df62d59d5c6d9d652
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-01-13 20:52:03 -08:00
Yu SI
a605440282 msm: eva: updated AON mapping attribute for FW
updated AON mapping attribute for FW

Change-Id: I207e7aaf0413e9d71db1d7f98f99db8d28a831a8
2023-01-06 16:27:36 -08:00
Yu SI
803a412ea9 msm: eva: add AON mapping for FW
added support to map AON reg range for FW
updated clk_get return check

Change-Id: I93732f840a6354558853d6c6644b569c53fa93db
Signed-off-by: Yu SI <quic_ysi@quicinc.com>
2023-01-05 16:31:13 -08:00
George Shen
b873ee6df9 msm: eva: Support XO clock reset mutual exclusion
Using existing clock reset APIs.
Remove DSP debug level bitmask check.

Change-Id: Iab6ff6309b2d56e678b468b2137834f8931071e9
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-01-04 10:37:53 -08:00
Yu SI
d9410c7653 msm: eva: power on off sequence update
update according to HPG
--added utility to asser & de-assert clk individually by name
--added xo clk reset and vote for sleep_clk
--defined more CVP_AON_WRAPPER_XXX regs in IO header
--updated power off controller sequence
--updated power on controller sequence
Debug, to move later
--clk_set_flags for mvs1c cbcr for retain_periph retain_mem

Change-Id: Ia0872270412119e4dc6c3e2b12b59862adeea0c5
Signed-off-by: Yu SI <quic_ysi@quicinc.com>
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2023-01-02 17:03:49 -08:00
George Shen
1fb08bdc09 msm: eva: add RGE, VADL ITOF CB setting print
Dumps registers to debug FW issue in setting CBs
for CDM buffers.

Change-Id: I287f18455f2a6b2f7cebd520c73a0de84030a8e6
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2022-11-17 12:39:07 -08:00
George Shen
d052ed9da6 msm: eva: print kdata in MSG
For presilicon debugging

Change-Id: I4fc82e1a14d8f623f237c30e3ab63877ddfb97f5
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2022-11-10 10:01:20 -08:00
George Shen
c7a2d986df msm: eva: Fix dprintk compilation errors
Shown in recent Lanai releases

Change-Id: Ia85a57756a35f14d4426ea5ea10cd5374188a9d4
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2022-11-07 09:57:57 -08:00
George Shen
1aed484f01 msm: eva: enabling support for data path bringup.
Add checksum support per packet type, configurable.
Add debug hook to print SID setting registers at SMMU fault.
Enable Auto-PIL.
Enable DSP interface.

Change-Id: Ie1fd2c584681b751836854667981a3c10beb56d4
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2022-10-26 15:29:57 -07:00
George Shen
163d88795c msm: eva: Add core power on/off seq change
For Lanai

Change-Id: I06572cd9923d4b8c1565638006f01cb09af90bb5
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2022-10-19 15:41:40 -07:00
Yu SI
7597271dde msm: eva: synx v2 support
propagated sync v2 support from 2.0
reference 4162025

Change-Id: I3427657e21e7eda92088d828203a330ba3c86335
Signed-off-by: Yu SI <quic_ysi@quicinc.com>
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
2022-10-10 18:20:57 -07:00