During CPU NoC LPI sequence. Print more debugging registers
in case LPI QACCEPT is not set after 20ms. It indicates a pending
transaction lingering around. Adding dump for NOC registers.
Change-Id: Ied58e52e30572074be77b4d51a03fb4194d78caa
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Revert back 200us sleep to 80us before XO de-assert.
Change-Id: I8446aa2eb5cfac32fdc5fc971ddd37b999623bf8
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Waiting for 1sec to acquire xo reset else BUG_ON.
Change-Id: I26bcc27d02b4104f36b1bcdac97cb784c1daca44
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
Changes made to accommodate difference in QOS & NOC
base registers offsets between pineapple and cliffs.
Change-Id: If8c631480d1f09bac21de52d0f27f0c29cdf594e
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
Use dma_alloc_coherent to allocate 4MB dsp hfi queues and map
them in non-io-coherent way.
Change-Id: I6d8adb58ebcddae569259862a83e3aeffa3d2304
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
To avoid confusion in code reading and prepare for
future compatibility changes.
Change-Id: I43d61e18d2e2d75d1fd46ceb2e763511329ee32d
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Avoid delete non-existing session and power on check before
register write.
Change-Id: I0b7d5045d68fd18e5a9a041d3ad3e37f4dac16ad
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
when SSR is releasing core and some clients voting for bus.
Change-Id: I8575d747c17f234bbce216c346843ab07ea6b340
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
For user mode to save into a dump file. It helps FW debugging.
Change-Id: I1c9c52d27d0dfd20e3eeb54b203416f6df095c8d
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Core shall be powered on and WRAPPER_SPARE bit 1 shall be clear.
Change-Id: Id225c44f4a245482a8b9387109211461d03042e9
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
As PM QOS request needs to done for silver cores only for EVA and
number of silver cores would be different for different target so,
better to identify the actual number of available silver cores.
Added cpu_possible check to confirm if cpu is available or not.
Change-Id: Ibccc7688200732c3c666041a8fe414b4f2818993
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
For FW to hold debug info. Simplify driver structure for easy
dump in T32.
Change-Id: Ib310a3d9fe3437d5ce49783eb813fbb2d8bd3216
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Through POLL SSR event, only notify the error session. Other
sessions will not be impacted. This is different than SSR
handling.
Change-Id: I5acb4e21c19909b16350816621ae085d54fe05ac
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Needs extra change to enable EVA SMMU fault. This change clears
all the obstacles to achieve the goal.
Change-Id: Ia93ff2132ff53741f3c20d4271083f6f93824cac
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Use CVP_PWR instead of CVP_PROF.
Add AON timer reading.
Avoid SSR if core init failed.
Change-Id: I1dd40edc893009a2f2794e3431bb08398ec6352b
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Simplify code base for future generations of driver.
Change-Id: I9ed940184da3b2224c74092ac31163de29c84f64
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Match MPTest sequence to facilitate presilicon bringup.
Change-Id: Iafd4443eb0f9d6045e61eb2dd33b6663dc3f1334
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Recovery mechanism is added to invoke SSR when WD ISR is triggered.
Change-Id: I6f7a289f822c6f1a50494cd6a4855a2c3ba2cc72
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
Acquire xo_reset before accessing CVP NoC. There is a chance the NoC clock,
XO clock is disabled during XO reset. Acquiring xo_reset will block the
XO clock reset.
Change-Id: I51ab201beafbd1a4b998ee33a9d23c1efa3e2a14
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Avoid mis-use of old flag that could lead to failure in
powering collapse EVA when a session becomes idle for 3s.
Change-Id: I954bc0972b1f627b274b78659c34626127619af5
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Removed release and disable subcache in case of core init fails,
as subcache deinit is done as part of load FW failure error handling
and also as part of unload FW.
Change-Id: Ic1a6bf75eacaa8a4ccb95a7155e720932a372a58
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
Add cmd logging functionality as an
alternative to pkt logging. This has
advantages related to log dropping
and log mangling.
Change-Id: I0ff6801445821e1224f83fa7e2eb8bf8a849962b
Printing hfi q info at the of
session queue time out to get debug
info on missed cmd/frame pkt.
Change-Id: I9b324a6496699272f9f1b9cb794f3e322d5421ae
Signed-off-by: Nagesh Gunna <quic_ngunna@quicinc.com>
New HFI allows FW stop session and notify driver of
its completion. Driver is safe to reclaim resources
allocated for the session.
Change-Id: Ic6a08334a0bafd57f366a635c53f4f5f8f31f77e
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Reorganize the way to store FW required register mappings.
It will make future error check and debugging easier.
Update MID value to name translation table.
Change-Id: I6e3dbd837f2f2c297af16152754f27242aeb2637
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Before booting f/w, synx_recovery() shall be called as part of
SSR.
Change-Id: I1d03f073c964eaf5b26dd4fec5aac88b7d9de1a8
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Checks AHB, MVS1, MVS1C, SLEEP, XO clocks, ensure they are
turned on before initial accessing NoC registers.
Change-Id: I429e2e410ac29aab893b490dbbd985914843ed9b
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
SMMU debug register block was relocated. New QoS registers was
introduced. Without the change, S1 fault will end up as S2 fault.
The EVA driver cannot dump appropriate debugging info.
Change-Id: I5e833cee51a56164f7853baa91e8c6011ec41189
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
added support to map AON reg range for FW
updated clk_get return check
Change-Id: I93732f840a6354558853d6c6644b569c53fa93db
Signed-off-by: Yu SI <quic_ysi@quicinc.com>
update according to HPG
--added utility to asser & de-assert clk individually by name
--added xo clk reset and vote for sleep_clk
--defined more CVP_AON_WRAPPER_XXX regs in IO header
--updated power off controller sequence
--updated power on controller sequence
Debug, to move later
--clk_set_flags for mvs1c cbcr for retain_periph retain_mem
Change-Id: Ia0872270412119e4dc6c3e2b12b59862adeea0c5
Signed-off-by: Yu SI <quic_ysi@quicinc.com>
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Dumps registers to debug FW issue in setting CBs
for CDM buffers.
Change-Id: I287f18455f2a6b2f7cebd520c73a0de84030a8e6
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
propagated sync v2 support from 2.0
reference 4162025
Change-Id: I3427657e21e7eda92088d828203a330ba3c86335
Signed-off-by: Yu SI <quic_ysi@quicinc.com>
Signed-off-by: George Shen <quic_sqiao@quicinc.com>