Add support for sw2rxdma_link_ring size cfg ini.
Also add wrapper function to get the sw2rxdma_link_ring size.
Change-Id: Ic5b17f029fe6c735785701801b75284dd489ac1e
CRs-Fixed: 3525040
Include Umac reset irq line in the mask table only
when it is enabled for 8 msi group to make sure
the legacy devices are not impacted.
Change-Id: If8f6b7f948a7c9f45247e8ff934642f0a532ff0d
CRs-Fixed: 3499500
add multiple history array to keep track of mem allocation and
deallocation for qref table.
Change-Id: I9fa97fbe5a5c36509cbb5a458851a152200318a5
CRs-Fixed: 3475981
Add new set and get APIs for cfg items so that
those cfg items can be managed from the external
components.
Change-Id: I52eb747fc6c544cfe43273c3b8b0fcc27b5a4a5f
CRs-Fixed: 3502582
As part of CPE V2 or split phy board, IPA will start using
two TX ring and for the same disable the DP interrupt mask
assignment.
Change-Id: Ia676bfa6a8b89274f5dfd313f73761132bb7909c
CRs-Fixed: 3445325
1. Add ini configuration for enabling round robin flows to
core distribution in FSE
2. Register FSE APIs to CDP FSE ops
Change-Id: Ic61c44eb9bc68a8c1a0116d4e6aa1d54cf489b62
CRs-Fixed: 3505287
Allow the ppe ds tx descriptor pool to have a maximum
size of 64k tx descriptors.
Change-Id: I4c09b6337efaabedea93f36a3477f5bdcc32f288
CRs-Fixed: 3468613
Add DP API to evaluate if TX ILP needs to be enabled,
it is only enabled if following two conditions are met,
(1) INI for TX ILP is enabled
(2) htt msdu index to qtype mapping table index 3 value is
HTT_MSDU_QTYPE_LATENCY_TOLERANT
Change-Id: I4d0c1103941b8b12b8441762dc6b45d28ee1df21
CRs-Fixed: 3447096
ppe2tcl and Umac reset interrupts need dedicated irq lines.
Hence, group some of the existing dp groups togeather
to share MSI lines to make space for ppe2tcl and Umac reset
dedicated irqs.
Change-Id: I5181caeaeb4d0107b62e7ac812c2f829fd8215a2
CRs-Fixed: 3423553
This code helps to initialize and deinitialize new SOFTUMAC
based Rhine architecture.
Change-Id: I374140ccb3b31e9351c6e683c77d81a5a876472a
CRs-Fixed: 3382913
Support REO2SW ring pointer update threshold configuration,
it is helpful for PCIe utilization improvement.
timer based threshold - M: issue pointer updates when M micro
seconds has elapsed.
number based threshold - N: issue pointer updates when N entries
updates occur.
Change-Id: I49ed388520fd52e97e303d6ea9c04ced6cb5cf5f
CRs-Fixed: 3420101
Add support to enable/disable MLO Link Peer stats through
ini and cfg80211tool enable_ol stats command
Change-Id: Id1229a149befa416d060e1b07eee150e6b295abf
CRs-Fixed: 3397721
Tx completion is processed in napi context, which should follow
napi's max quota, otherwise once process count is over napi quota,
it will trigger napi repoll in kernel, meanwhile by current design,
tx completion hard irq will be enabled when the 1st napi process
finished, in such case 2nd napi process will conflict with repoll process,
finally trigger kernel side napi list crash.
Since napi quota is used in serval cases, while for tx completion
process, we want to process tx completion count as many as possbile
in one cycle, set 64k transmit frames account for 1 napi work unit
to gain max tx kpi.
Change-Id: Ic24f131c90b90b0e118edffcab559ddf31779dcf
CRs-Fixed: 3421368
Enable or Disable PPEDS for specific
WLAN Soc.
usage:
add "ppeds_wifi_soc_cfg=0x02"
in /ini/global_i.ini to enable
PPEDS only for second WLAN SoC.
Change-Id: I65f138cf37298feac70e76b95c22507e58394618
CRs-Fixed: 3408439
Reuse the tx descriptors released in tx completions
without releasing the associated skbs to reduce
the cpu utilization in direct switch mode.
Change-Id: I4ab3ac58977a626344877b8a818a4dbc4864aaf3
CRs-Fixed: 3393968
Make DP changes for handling umac reset in QCA5332.
Changes are done to program msi_data value of the IPC interrupt to FW.
Change-Id: Ib6453755e191da655b87b528a7cef38a464f316b
CRs-Fixed: 3401146
Change the number of tx descs per soc for direct switch
used for ppe2tcl ring to 2048 from existing 8192 to reduce
buffer usage.
Change-Id: I1e749833002926e9b6b9a84d38651525548dc79c
CRs-Fixed: 3391066
If TX data is TCP ACK, configure TX flow index 3 in
SW2TCL data cmd ring descriptor.
Change-Id: Ibd08b13ba8f0481aa11cd9c3dc54a49cd73674fb
CRs-Fixed: 3368303
Added changes in wifi module to update PPE2TCL & REO2PPE ring
size as 8k to improve the perf for MLO case
Change-Id: I6ca241c21c44b4cda8869e5e2ae9a4a906d98fc8
CRs-Fixed: 3365361
An INI dp_tx_spl_device_limit is defined and can be used to configure the
limit of TX descriptors that can reserved on the SOC to handle
special frames like EAPOL.
CRs-Fixed: 3343207
Change-Id: Ic84a11249880a3541749a72ac6d60df548f2bc5c
An INI dp_tx_spl_desc is defined and can be used to configure the
limit of TX descriptors that can reserved on the pdev to handle
special frames like EAPOL.
CRs-Fixed: 3343209
Change-Id: I6578bddd1f4ea07528c9f66f778b113ec6fb9e61
1. Change the names of parameters and functions related
to direct switch feature from ppe to ppeds
2. Remove the unused ppe_release_ring
Change-Id: I5a95b1273e338f354903af98158578ac65758a8a
CRs-Fixed: 3345097
The kernel-doc script identified a multitude of documentation issues
in the wlan_cfg folder, so fix them.
Change-Id: Id6bfb397608de6b858e448a867a3c21dffc9a178
CRs-Fixed: 3352408
Enable and register PPE2TCL and REO2PPE ring interrupts
for direct switch
Set interrupt timer threshold for ppe2tcl ring as 30 us.
Change-Id: Ida1ff6c3c2000f16f07960f7eae0d10edc337dc0
CRs-Fixed: 3341790
Change minimum limit of dp_rxdma_buf_ring and
dp_ipa_tx_alt_ring_size value for ini may change little.
Change-Id: Ibbf8843b8f21bbfff1db83a0934f95222930b9ab
CRs-Fixed: 3338076
On low memory targets, even with current min values, OOM is seen
on driver load time. This requires us to further reduce
the min value.
With 11be enabled, current max value may not meet KPI requirements.
Hence align min and max INI values for IPA TX ring and TX completion
ring size with HOST used ones.
Change-Id: Iedf1c2d4be04d798314e9ba61a844038c5696f45
CRs-Fixed: 3338114
To support MLO on 4 chips, update the maximum number of chips that
can participate in MLO to 4.
CRs-Fixed: 3314581
Change-Id: I93a253b4e54f7e4e19ea8407facfb69e6347d192
