This change sets lm_mask for dp connector based on
number of LMs allocated by RM. This mask will be
used during rm allocation and validation of dcwb
mixers for dp display.
Change-Id: I271af03da560587faf17446471bd6b81bb9e809b
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
DSC enable status is updated in DP panel struct as per the DPCD reg
read which is done at the start of the HPD ISR. However, there is a
chance that DSC is actually disabled later during mode query due to
shortage of DSC blocks. This status is stored as part of compression
info structure. This change checks for the latter struct to determine
the actual DSC status.
Change-Id: Id7cd4e65060f2ec939f945e9ac4f4e66260605d3
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Add existing debug logs to ipc logging to be
accessed through debugfs.
Change-Id: Id9bfe61cb7921674eadc5635847c81a0fbdaef5c
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Some of the display status changes such as re-enable
or re-disable are not critical errors and can be ignored.
This change downgrades such errors as warnings.
Change-Id: I6800e534fc7fb825a472f37bb78a928e2e78d63a
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Currently in an MST scenario, DSC resources are updated in
bookkeeping only when the corresponding stream is enabled.
This would lead to assigning already reserved DSC blocks to the
2nd stream, if 2nd stream is validated before the 1st stream is
enabled. This change would update the bookkeeping as soon as the
mode is validated.
Change-Id: I7f89a16639efcde3e5dfdf423715ed354e1de66a
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.
Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
The software mvid/nvid values represent the ratio of mode clock
to link clock. Currently we are converting the link clock to vco
clock, get the ratio of vco clock to mode clock and then adjust
the resulting values to get the ratio of link clock to mode clock.
This change simplifies this logic by directly using the link
clock to get the ratio and uses fixed point arithmetic to scale
the resulting mvid, nvid values to meet requirements.
Change-Id: Ifdfa27edb73d2db6381e592db219e75806d6bdc7
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Currently the tpg_ctrl node takes a boolean flag to enable or disable
test pattern output on DP controller. It always sets the pattern type
to a default pattern. This change updates this interface to accept an
integer value so the user can select different patterns supported by
the controller.
Change-Id: I399091a57f353b2fb8d29a48a8390898ca9afb55
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
drm device pointer is not set in dp aux object which
is leading to a warning message during device bootup.
This change will set that pointer before registering
aux object.
Change-Id: Ib79ece56d7d5efd098e06104eb020648d1d075f7
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Modified the pre-emph values for S3P0 & S1P1 in HBR/RBR
table. Also, modified BG timer value as per the latest
HPG changes.
Change-Id: Id9088d3cfe73cb14518dcf490676d92c54925793
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Because of changes to ref clock frequency, few of the pll
reg values are different for kalama compared to palima.
This change differentiates between these two 4nm versions,
based on pll revision and also introduces a pll reg table
to differentiate the values.
Change-Id: I016330ded10ab334012daa8cc288a8cd5c039f58
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
DP PLL driver is the clock provider for link_clk and pixel_clk source
clocks. Once the PLL is configured, the clock rates for these output
clocks must be explicitly set using the clk_set_rate() API so that
the clock framework can correctly compute any MND values required
to satisfy the requested rate at the branch clocks that source from
the PLL output clocks.
Change-Id: I14f8f58333ac5ba3f547d12a123cb5e5f05c6005
Signed-off-by: Aravind Venkateswaran <quic_aravindh@quicinc.com>
Change removes the dependency of reading MVID and NVID settings
from dispcc registers and calculates the values locally in displayport
driver.
Change-Id: I9ad66aea44a3cbc0f739060c49e23d389022a48a
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Swing/Pre-emph, SSC, and CLKBUFLR values updated to match
latest changes as per kalama HPG.
Change-Id: Iae96b38f0f8c39280081ae43b41f73ea10f6ddb7
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
On kailua onwards USB3 DP SSPHY power is control using GDSC.
This change adds support to vote for GDSC when displayport
driver is active.
Change-Id: I2e741f2091018f5dae9a1e7e886179bc6b982d40
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Changes include support to update necessary copyright
information to dp file for 4nm target.
Change-Id: Iebb2cc542f7b9262073936f12d55eb1be788e757
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Changes include updated register writes for DP PLL
as per 4nm target.
Change-Id: I2d8ddbf4af5c2c6d885c73b7c888f31ce45f4cbf
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
In an effort to reset the DP controller states on a disconnect, the
driver is issuing a SW reset to the controller. But SW reset on
the controller doesn't necessarily restore the controller to its
full reset state. It only resets part of the logic. So if for some
reason the MST streams were not disabled properly, ie. the slot
allocations were not reset properly in the controller, then a SW
reset would result in the DP controller raising state interrupts.
Since this SW reset is issued in the tail end of the disconnect
processing, the driver turns off all the clocks and also
removes the irq handler. This results in an interrupt storm at
the MDSS top level.
This change removes the SW reset on the disconnect path and
relies on the SW reset that already exists in the connect path
to restore controller state.
Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
MST driver is incorrectly using maximum bw_code while initializing
MST topology manager instead of maximum link clock in KHz. This
prevents the topology manager to set MST state on a subsequent MST
plug in causing all MST cases to fail.
Change-Id: I9fc4e0326fe0c7a6c9b81af8810b7098fa8ba967
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Decouple the configuration and parsing of aux switches with the
parsing and configuration of HPD sources. HPD notification can come from
either GPIO based approach or a PD module through a SW interface. The
presence of AUX switch on the board should have no bearing in deciding
which configuration for HPD detection is used. Update the implementation
to allow for flexibility in selecting any combination of the HPD source
and aux switches.
Change-Id: I96d558f1d88a359d523fae6dc746045393884d5a
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
DP PHY version is changed for kalama. This change
initializes the catalog structure for this new
version.
Change-Id: Ib89293cb874c61c6276f49573266822570e715bb
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Certain pll variables and function signatures are
obsolete and hence removing the header file
declaration containing these.
Change-Id: I93d4ff096ff253f21d67660287d6d3baa857cca1
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
In an effort to reset the DP controller states on a disconnect, the
driver is issuing a SW reset to the controller. But SW reset on
the controller doesn't necessarily restore the controller to its
full reset state. It only resets part of the logic. So if for some
reason the MST streams were not disabled properly, ie. the slot
allocations were not reset properly in the controller, then a SW
reset would result in the DP controller raising state interrupts.
Since this SW reset is issued in the tail end of the disconnect
processing, the driver turns off all the clocks and also
removes the irq handler. This results in an interrupt storm at
the MDSS top level.
This change removes the SW reset on the disconnect path and
relies on the SW reset that already exists in the connect path
to restore controller state.
Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Changes include support to correct the version
check for DP PHY changes for 4nm target.
Change-Id: Ib891d43bd5db10edc4b49a70f7a3b8af073167cd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Commit 283560c ("disp: msm: dp: use Extended Base Receiver Capability DPCD space")
pass additional parameters to supply maximum lane count and rate to MST topology
manager. In cases where sources have lower maximum lane count or rate than default
MAX_LINK_RATE, these values will be used instead.
This change puts macros in the callers of function drm_dp_mst_topology_mgr_init to
handle interface change between kernel version 5.10 and version 5.15.
Change-Id: I394c70640606de477d67b08cafb495bebb6c549f
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Commit 1ef7ff2 ("disp: msm: dp: pass drm_dp_aux to drm_dp_link_train* APIs")
passes additional parameter drm_dp_aux to drm_dp_link_train APIs in order
to use drm_dbg_* within those functions.
This change put a macro in the drm_dp_link_train* APIs caller to handle API
changes for both kernel version 5.10 and version 5.15.
Change-Id: I9fd22e0effbe87b6cfecf72b38a10d74a2c0c5ea
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Changes include support for 4nm DP PHY and DP PLL.
Added dp_pll_4nm.c file with register programming
sequences for DP PHY and PLL.
Change-Id: I104cf69964904c9a47a17e75a84df011d7994c9f
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Changes include support for specific DP PHY
registers and related code changes for 4nm
target.
Change-Id: I9b349e47ff057421fa465a59e1206fd09f7e367a
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
If there are any uncleared DP interrupts before deinitialing
and turning off the clocks, the interrupt might get stuck at
the MDP level and can't be cleared without turning the DP
clocks back on. To avoid this situation, this change clears
all the interrupts before turning off the clocks.
Change-Id: Id13b102fa81c85f92ae8c1d11ffaf7d5bad5fd12
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
