Commit grafiek

3791 Commits

Auteur SHA1 Bericht Datum
Soutrik Mukhopadhyay
26666bdf16 disp: msm: dp: update PHY settings
Update PHY settings for targets using pll-revision as
"4nm-v1".

Change-Id: I1242154cdb3aef5c9a84954d69e40f0520157620
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2023-09-29 11:19:56 +05:30
Jayaprakash Madisetty
29852fa715 disp: msm: sde: program read pointer after configuring vsync_counter_en
Program the read pointer after configuring the tearcheck registers.
The read pointer register should be configured after VSYNC_COUNTER_EN
is set as per hw programming sequence.

Change-Id: Idc410867aa92760b43117552b00914481c0ba6d3
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2023-09-28 15:50:30 +05:30
Srihitha Tangudu
6192a10871 disp: msm: dsi: Only enable lanes required during phy enable
Currently we are enabling all the lanes irrespective of the
lanes we are actually going to use. Add support to enable
only those lanes that are required and thus save power.

Change-Id: I9aae76eeaa05a79337d4e4b1f2e36ea9842bd580
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2023-09-28 11:47:25 +05:30
Nisarg Bhavsar
b97e86c661 disp: msm: dp:Add ready state check in deinit flow
Add check for READY state in dp_display_host_deinit.

Clear READY state in deinit flow to prevent state machine
errors with multiple concurrent plug/unplug events.

Change-Id: I0b17cffc7a3261ae4259225bb51452162763ae2a
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-09-26 15:44:13 -07:00
qctecmdr
75727e2f3a Merge "disp: msm: dsi: avoid restoring bit clk & front porches during set mode" 2023-09-26 10:16:58 -07:00
Anand Tarakh
958b7d3644 disp: msm: dsi: clear pll unlock error bit before unmasking
Since PLL UNLOCK status bit is a sticky bit, ensure this bit
is cleared before unmasking PLL UNLOCK error.
Otherwise unnecessarily DSI controller will trigger error
interrupts for the stale status, the moment error is
unmasked.

Change-Id: I7b7aa63b5e508dde446a4469d9a6625a071dae00
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
2023-09-25 23:15:17 -07:00
Alisha Thapaliya
63723f6441 disp: msm: sde: Add a separate modify block for sixzonev2
Sixzonev2 uses a combination of broadcast enabled and disabled
cases to program luts and modify PA config registers respectively.
It also uses SB LUTDMA which requires all DSPP sub blocks to be
flushed. The modify operation can't be used with broadcast enabled and
was resetting the sub blocks to only indicate DSPP1 and causing the
DSPP_SB flush to be missed for DSPP 0. This change maintains the original
dspp indices to be used for broadcast enabled case and SB LUTDMA kickoff.

Change-Id: I1079878bbf44238419d4f88a40814e488c0800e3
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
2023-09-25 13:29:28 -07:00
qctecmdr
dd7b2f5e5a Merge "disp: msm: dsi: use ctrl cell index to set frequencies for link clks" 2023-09-25 10:05:01 -07:00
qctecmdr
abc73d74d3 Merge "disp: msm: dsi: add mutex lock before link clock frequency update" 2023-09-25 04:47:22 -07:00
Anand Tarakh
0f011042ec disp: msm: dsi: avoid restoring bit clk & front porches during set mode
Suppose there's a mode change in  Nth commit and N+1th commit mode
change request for dynamic clock came even before the Nth commit
mode is set in DSI. Now, restoring the bit clock and porches during
mode set of Nth commit will update the clock and porches according
to the new dynamic clock request which should have actually been
handled in N+1th commit mode set and this can lead to DSI underflow
/overflow.

Avoid restoring bit clock during bridge enable as it is already
taken care during bridge mode fixup.

Change-Id: Ieecb0020a77f5e082a8b9da0ecf461acdbe89e0c
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
2023-09-25 00:06:50 -07:00
qctecmdr
27f29fb439 Merge "disp: msm: sde: swap right mixer flag" 2023-09-20 11:19:16 -07:00
qctecmdr
d0c7fa0965 Merge "disp: msm: sde: disable solver for autorefresh disable transition" 2023-09-20 11:19:16 -07:00
Anand Tarakh
cf56be0bb8 disp: msm: dsi: use ctrl cell index to set frequencies for link clks
To set frequencies for link clks, the clk manager index of
ctrl is require. Use ctrl cell index to get clk manager index.

Change-Id: I175d0721e672fb4d368349584c8b448ba63f4224
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
2023-09-20 11:47:30 +05:30
Raviteja Tamatam
a57c71fa4e disp: msm: sde: wait for pending vsync event in encoder disable
In some corner cases there is pending vsync timestamp event to
sf when encoder is getting disabled. This is keeping vblank irq
to be enabled after sde_encoder_virt_reset leading to NULL ptr
access. In these cases, wait for vsync event to be completed which
disables the irq.

Change-Id: If0a6be1fc282906fb1b9c0fd18ede1d31d2549b3
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
2023-09-15 12:07:07 +05:30
Anand Tarakh
307aea3dc1 disp: msm: dsi: add mutex lock before link clock frequency update
Acquire mngr clk_mutex before updating link clock frequencies.
Failing this may lead to race around condition while setting the
link clock frequency rates.
Make sure byteclk and pclk rates of PLL are configured according
to clock manager and not the controller.

Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
2023-09-14 12:25:44 +05:30
Renchao Liu
681524cca9 disp: msm: sde: swap right mixer flag
Change swaps right mixer flag when swapping mixer.
Histogram IRQ is registered to unexpected mixer
index if both mixers' right mixer flag set as false.

Change-Id: I0243d70129dc0c3bff24cabc8877c626101acd83
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
2023-09-11 17:50:03 -07:00
Prabhanjan Kandula
1bd779a0da disp: msm: sde: disable solver for autorefresh disable transition
RSC Solver enable during autorefresh enable need to be avoided.
Currently in SDE driver, solver is disabled if autorefresh is
enabled from HLOS client but autorefresh disable transition is not
considered. This change avoids RSC solver mode in autorefresh
disable transition commit including splash hand-off.

Change-Id: Ib1c4791b203892629abdd84999671830a61f6ed0
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
2023-09-10 19:34:00 -07:00
qctecmdr
04e6f35c65 Merge "disp: msm: dsi: Send report_panel_dead in underflow or overflow cases" 2023-09-04 00:49:00 -07:00
qctecmdr
381401fb32 Merge "disp: msm: dp: change err to warn on link failure" 2023-09-04 00:49:00 -07:00
Rohith Iyer
5413180441 disp: msm: dsi: Send report_panel_dead in underflow or overflow cases
In the case of DSI underflow or overflow, skip enabling back the DSI error
interrupts and instead send panel_dead. The error interrupt will be enabled
later by HAL as part of handling panel_dead event. Not enabling back the
DSI error interrupts immediately can prevent IRQ storm from occurring.

Change-Id: I769872bb5ac9ef8826c3e4caaab7723901dfc7d8
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
2023-08-31 11:54:14 -07:00
qctecmdr
53d849adcb Merge "disp: msm: dp: Reduce IPC logging" 2023-08-18 07:20:32 -07:00
qctecmdr
5ef87fe44b Merge "disp: msm: dp: Re-intialize panel after link training failure" 2023-08-18 07:20:32 -07:00
Nisarg Bhavsar
6156c55770 disp: msm: dp: Reduce IPC logging
Reduce logs going into IPC buffer to avoid overflow.

Change-Id: I51ae06cf244d1447c3c183b45133960737c4eafd
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-08-10 11:20:13 -07:00
qctecmdr
bb9a0f1f00 Merge "disp: msm: sde: fix dsc reservation logic" 2023-08-09 13:04:53 -07:00
qctecmdr
e4686b1561 Merge "disp: msm: dp: Add vc_start_slot check before payload allocation call" 2023-08-09 13:04:53 -07:00
qctecmdr
ed433b586e Merge "disp: msm: sde: fix plane detach from ctl path" 2023-08-09 13:04:53 -07:00
qctecmdr
b9d7d0d286 Merge "disp: msm: sde: Add roi region for spr" 2023-08-09 13:04:53 -07:00
Qing Huang
afeb7da4d7 disp: msm: sde: Add roi region for spr
Provide spr_roi region for spr over fetch in partial update.
Support different the roi size of connector and crtc.

Change-Id: Ic78a20badcafefd353a97532281dae26e5a772de
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
2023-08-09 01:28:39 +08:00
Prabhanjan Kandula
af53de8544 disp: msm: sde: fix dsc reservation logic
In current SDE driver, DSC resource allocation is done in
reverse order for DP displays. If this DSC resource allocation
invoked with array previously chosen DSC blocks, dereferencing
the array should be in same order of resource allocation to
avoid index mismatch and resource allocation failure.

Change-Id: I83fb74e6677effcf6ddaeea45a0bd6140fd1e6d5
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2023-08-03 12:33:43 -07:00
Nisarg Bhavsar
baf508ce8b disp: msm: dp: Add vc_start_slot check before payload allocation call
Adds a check for payload's vc_start_slot before attempting to finish
payload allocation. vc_start_slot is set to -1 on payload allocation
part 1 failure.

Prevents calling mst helper function on failed payload allocation.

Change-Id: I435f370616afbc875bffd9207b2eb1cf98086178
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-08-03 12:27:13 -07:00
Andrew Bartfeld
0ebfa8bf82 disp: msm: dp: change err to warn on link failure
When HDCP enabled sink reports a link failure, it should
be a warning instead of an error because it can be part
of expected behavior during encryption level changes as
per spec. Also now prints debug statement on min enc
level changes.

Change-Id: I747f6997c32cfcdff9a4b6ca7e4750a651491833
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
2023-08-01 16:04:07 -07:00
Nisarg Bhavsar
338088c9e8 disp: msm: dp: Re-intialize panel after link training failure
Sporadic link training failures occur when panel doesn't
respond to updating of link parameters.

Re-initialize panel after a link training failure when
the link rate is downshifted. Fixes sporadic lt failures.

Change-Id: I638996b9e7f478170aa4314c601772efd66edd16
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-08-01 08:24:40 -07:00
Prabhanjan Kandula
3817317773 disp: msm: sde: fix plane detach from ctl path
During display disable, ensure source pipes are detached
from control path in the disable commit itself. Otherwise,
if other display acquire these pipes immediately it can hang
as these pipes are still staged on current display ctl path.

Change-Id: Idc376051908676c74bc26394372a92316a674e3b
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2023-07-27 18:45:39 -07:00
Linux Build Service Account
6c3035c600 Merge "disp: msm: replace vma->vm_flags direct modifications with modifier calls" into display-kernel.lnx.1.0 2023-07-27 10:19:58 -07:00
qctecmdr
8e69d92449 Merge "disp: msm: dp: clear link info capabilities during DP disconnect" 2023-07-26 20:14:18 -07:00
qctecmdr
0f8456bfda Merge "disp: msm: sde: pass fence error value in hw fence error handling" 2023-07-26 20:14:17 -07:00
qctecmdr
19cb917ff1 Merge "disp: msm: sde: reset cwb encoder after commit done complete" 2023-07-26 20:14:17 -07:00
Nisarg Bhavsar
60c9dce746 disp: msm: dp: Add null check after payload allocation
Adds null check for MST port and connector after payload
allocation. Prevents calling mst helper functions with
a null port or connector on a failed payload allocation.

Change-Id: I8e228bd1498b11b302371c1ad6d805d5f941667e
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-07-26 09:07:41 -07:00
Prabhanjan Kandula
74796543cf disp: msm: sde: reset cwb encoder after commit done complete
Postpone virtual encoder reset until commit done complete
on all the encoders of the crtc to ensure cwb encoder
resources are held until it's primary encoder commit with
cwb resources disable is picked by HW.

Change-Id: I820317d13c00b44f6edd69acff83dc3b494b6282
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2023-07-24 13:30:02 -07:00
jianzhou
6923767e4a disp: msm: replace vma->vm_flags direct modifications with modifier
calls

Replace direct modifications to vma->vm_flags with calls to modifier
functions to be able to track flag changes and to keep vma locking
correctness.

Change-Id: I4ad265028dc138912210eb907a7b0656c72b1464
Signed-off-by: jianzhou <quic_jianzhou@quicinc.com>
2023-07-21 02:41:59 -07:00
GG Hou
34e9a682d7 disp: msm: sde: pass fence error value in hw fence error handling
Passing the same error code received from the input fence error.

Change-Id: I59865e89eb974d1ee9f7c2fe3e13acd66cb82617
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
2023-07-21 01:44:04 +08:00
Yu Wu
f78456a7fa disp: msm: sde: add parameter NULL pointer dereference checks
Add parameter NULL pointer dereference checks to improve code quality.

Change-Id: I79edf073c9b6d0c225a032017cf3a67ce4cd1d57
Signed-off-by: Yu Wu <quic_zwy@quicinc.com>
2023-07-17 11:09:42 +08:00
qctecmdr
8fc8477586 Merge "disp: msm: sde: add buffer size checks" 2023-07-13 03:27:41 -07:00
qctecmdr
403ae7becd Merge "disp: msm: limit reglog to user debug builds" 2023-07-08 12:16:43 -07:00
qctecmdr
1e5f63da67 Merge "disp: msm: dp: send hotplug event on mst sim port status update" 2023-07-06 08:35:36 -07:00
qctecmdr
d8ba3f5ceb Merge "disp: Enable MSM_EXT_DISPLAY config for dp_audio." 2023-07-06 08:35:36 -07:00
qctecmdr
815b01d61d Merge "disp: msm: dp: Release connector reference after reading crc frame value" 2023-07-06 08:35:35 -07:00
Varsha Suresh
6830449deb disp: Enable MSM_EXT_DISPLAY config for dp_audio.
Add support for all the configs symbols under config_options under DDK framework.

Change-Id: Iba2949175afe5f55a2e3107d2afd71e55b862d61
Signed-off-by: Varsha Suresh <quic_varssure@quicinc.com>
2023-07-04 14:57:07 -07:00
Yu Wu
bb70fda262 disp: msm: sde: add buffer size checks
Add buffer size checks to improve code quality.

Change-Id: I99c64d6157d7b0475b0b28e093ea70820981fddd
Signed-off-by: Yu Wu <quic_zwy@quicinc.com>
2023-07-04 14:23:43 +08:00
Soutrik Mukhopadhyay
198f8c702f disp: msm: dp: Release connector reference after reading crc frame value
This change decrements the specific drm connector's reference count
after it has been used for reading crc frame value. Without this
change, there might be a chance of a connector's reference count
still remaining positive, even if it is not accessed anywhere
further in code.

Change-Id: I9058ca046fa114bc10159045f98c40ac68ade751
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2023-07-03 17:31:33 -04:00