Add logic to derive clock residency values for each
frequency levels.
Change-Id: Iadad29d2733cb083fce627999a31dd96475b73c1
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Fix the issue in pineapple CAP Database for
SLICE_DECODE.
Change-Id: I1b4dc51bbb23634aa372eba35b18ca9b6caada2d
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
Set mvs0c clock flags (force mem and pheripheral on).
Change-Id: I52380a30a4c74d9658f989377b5c77209cd8a33e
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
- Implement upstream specific memory_alloc/map and
memory_unmap/free API based on standard dma_alloc_attr()
and dma_free_attr() APIs which allocates and map dma buffer.
- Combine alloc and map, unmap and free.
Change-Id: Ie85914beb72c3976febdc9e6a11c9199f2ea4192
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
introduced core error state and added changes
to refine core state machine.
Change-Id: Ib3b94fd3798e902b7a6cfc5de45820558c89806e
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Introduced MSM_VIDC_CORE_ERROR state in core. It supports
CPU_WATCHDOG and VIDEO_UNRESPONSIVE core substates.
Change-Id: I6aa700c37782d64d64cd132ea13009dda22cc8d1
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Poll for AON spare register BIT(0) to become zero before
asserting XO reset from video driver to ensure CVP/EVA driver
is not asserting XO reset around the same time. Asserting
XO reset by both driver at the same time may result in
unpredictable behavior.
Change-Id: I71a0bd0175ef7701c9a855abbf3c2e741d937dfb
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
This is change 2 of the Prepare dependency list without
parent change.
In this change we remove all parent information from
the CAP database.
Change-Id: Ie0b878050ae2d24e3c1a41cbd579ef0f19d42250
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
Prepare dependency list only using children.
Change-Id: Id79487825fed1f121821126589594b64820c85d3
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
Remove addtional mvs0c clock reset which is not
required from power off sequence
Change-Id: I2077cb0ceee6451cd2d2af067ac8a7be3335dd16
Signed-off-by: Deepa Guthyappa Madivalara <quic_dmadival@quicinc.com>
update the set function for BASELAYER_PRIORITY control.
with out this change, configuration is not set to firmware.
Change-Id: I57f01a8e02462ee9e8c221581043a8a70adbfcc5
Signed-off-by: Manikanta Kanamarlapudi <quic_kmanikan@quicinc.com>
Disable video power collapse on pineapple chipset until
power collapse sequence is successful.
Change-Id: I2e7d0085e6d810fb79c2b1070c4bd498f443cfc8
Signed-off-by: Deepa Guthyappa Madivalara <quic_dmadival@quicinc.com>
Introduce core->sub_state similar to inst->sub_state.
[1] pm_suspended - moved to this substate in case of PM suspend
[2] handoff - moved to this state after successful
handoff_regulator call.
[3] fw_power_control - moved to this state in case of IFPC.
[4] power_enable - will track core power_on/power_off status.
[5] page_fault - used to rate_limit fault logs.
[6] cpu_wd - indicates hw fired wd interrupt.
[7] video_unresponsive - moved to this state if sync cmd fails.
Change-Id: Iceb65cf404fd93aff7846860b0276307e4eab570
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Move adjust/set control functions to common/platform.c as part of
upstream effort.
This is part 1 of the change.
Change-Id: I8c440740fe785b5b052c4d44963ea34c21419fa4
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
Upstream driver doesn't support context bank address ranges,
so add dma mask attribute to context bank to specify address
range for upstream driver.
Change-Id: I09191b500006d6c7abf364fbfa22377b480a4b4d
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
video driver is maintaining multiple tables based on enum
name pair. So this mapping might go wrong if new entry is
inserted in different position.
So added logic to prepare enums & static const char* arrays
using macros. So compiler will take care of creation and
maintaining order.
Change-Id: Id3669cf3ce150b3ababb84dce18326220f41d88d
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Enable xo reset clock since it is enabled
from clock driver.
Change-Id: Ica38616f514c9f2288a60fbfb3e0a3683c154b15
Signed-off-by: Darshana Patil <quic_darshana@quicinc.com>
Add assert and deassert axi and mvs0c resets to
avoid video hardware unresponsive issues due to
multiple power collapse sequence execution.
Change-Id: I25ec99eab6b50111161ec9486ea1155bee63f7fc
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
- Add assert and deassert reset control functions to
update power off sequence in pineapple chipset
- Rename clock names to match with clock macros
Change-Id: Ic6dc0daac8110597bfcb02cceba94d2b97548723
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
Update function definition to be same as prototype to
avoid compile error
Change-Id: I92be0d96ce1e95e858cca6e5cad8de0564a60e5b
Signed-off-by: Deepa Guthyappa Madivalara <quic_dmadival@quicinc.com>
1. Allow turbo for HEVC 10bit all intra decoding;
2. Add 25 percent extra to VSP cycle for HEVC
10bit all intra decoding;
Change-Id: I794b2a896f7e9444c8979abdb15b8e673a5270ee
Signed-off-by: Zhongbo Shi <quic_zhongbos@quicinc.com>
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
if PC fails for 10 times then video driver is treating that situation
as fatal and doing force core_deinit(), in this case firmware will not
follow vcodec power_collapse sequence and if there any pending
transaction from any session it will cause smmu_fault during next
firmware_boot sequence. Added change to perform vcodec power_collapse
from power_off_iris3_hardware() incase of core_deinit due to PC failure.
Change-Id: I45e32985d87b5cc882c4f96f77d1cabc796e6ba0
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
