Make msm_drm into single module and all child driver
registers and unregisters are handled from parent's
register and unregister respectively.
Change-Id: I017513d1de3b6b25dd5543d7fa7741c0bac1740d
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
sync_state driver disables any resources that
don't have any votes after driver probe is completed.
Move MDSS resource votes to probe so that any resources
that are needed for continuous splash are intact until
the bind of all the components is complete.
Change-Id: I0056bf1ec56bcd6a1b620a81143d4b49d7ea2921
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.
Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
A new position control register field has been added to the
DSPP PCC on Lahaina. This field controls whether PCC is invoked
before or after GAMUT mapping.
Introduce new PCC control logic to set the PCC position based on
the new PCC_BEFORE flag. Older versions of the PCC control function
now clear all flags to ensure backwards compatibility.
Change-Id: I0a33604111b755e0a0ccf1864a57b17cc9071e3f
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
This change addresses out of range and null checks in
sde and dp driver.
Change-Id: I142196d7394f0bf0abab1bfa89abfd784a5521c8
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add scaling linewidth variable and logic changes to get
valid max linewidth values for inline rotation and scaling.
Modify linewidth check to compare with scaler source width.
Change-Id: I7c63175e568ecb524f9cdf8ada1d7c6fdc999236
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
This change updates plane's dirty flag with QoS
value to ensure QoS gets reprogrammed with new FPS
settings. This is required as QoS values will change
with FPS.
Change-Id: I377b99da2a640d375bd48477f149197b332e7f7b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Updating qos remap updates requires reading registers to update values,
this adds additional CPU processing when in reality this update
is only needed once.
Bug: 142504774
Change-Id: Iec8d4dfd858b0602db7d2275b6b716dbcffe0d2f
(cherry picked from commit dbd1cfbc21db4b9bd4f1a4fc234cedc314fa1265)
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Perf tuning mode can be updated through debugfs and this should
be used to reflect the core clock rate.
Change-Id: I313d079f0b8013f43f4b293c6400f34eaf56b6d2
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Dim layer clearing/setup requires reading registers in order to update
value, doing this add additional CPU processing when it's not really
needed. Add logic to only do the updates only when needed.
Bug: 142504774
Change-Id: I23bcbe39575de35c387cfb7d2b9dc993525e4f98
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change calls setup on blend configuration per stage
instead of per plane per crtc mixer. This avoids unnecessary
register programming if two planes are in the same stage.
Change-Id: I7481270edad13a4182352e72d5d2ab8941de0ae5
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change introduces pre-downscaling values to the path where
these values are not provided by userspace. Currently, pre-downscaling
is only allowed by a factor of 2.2 in the x direction. With this
change pre-downscaling will support >2.2 up to 4 in the x direction.
Change-Id: I04d1b07243a5973e9338ea2a212280985b31b6a3
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Add xlogs to capture the secure state information of
each of the planes during mixer setup.
Change-Id: I5d60fb4287b13b3ba5a78c6b858dd244ebeb18aa
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
When there is a race condition between DMS seamless transition and
drm_wait_vblank_ioctl, the latter gets deregistered for vblank
handle as drm_crtc_vblank_on call in crtc enbale increments vblank
count. This change avoids drm_crtc_vblank_on call during seamless
transition when crtc is already enabled as it is not required.
Change-Id: I0b9327a98cef00405b5b94e24a3fd15205339cfc
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
During stability tests there are cases where smmu faults are
seen due to direct transition from secure display to secure
camera without smmu ATTACHED state. Added atomic check to avoid
such transitions.
Change-Id: I307e342f35c6e7dab82902fa77e3a5c0c082f4e4
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
The color-processing partial update check wrongly
assumes that all pipes in a CRTC have a DSPP attached.
This inhibits the use of any LMs without a valid DSPP.
Fix the issue by removing this invalid check since whenever
a DSPP feature is required, the HW resource availability is
already confirmed during the color-processing property validation.
Change-Id: I5b4565865644e4a0fa3d0542a299067f21756863
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Restart the timeline for the idle power collapse delayed work
timer for every resource control kickoff instead of only during
a power state change. This will prevent entering mode2 at
unexpected times during active scanouts.
Change-Id: I001157ff7e6b6246e26d537e30d8617cab9cb463
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add a check to escape the DSC allocation once the requested
number of DSCs has been reached and a pair is not required
for the last DSC allocated. This issue was introduced when
trying to allow for quad DSC, which broke single DSC use.
Change-Id: I4bc368004f92570d588e76ceb832d63fd3bb15d7
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
This change adds support for regdma accelerated programming of
partial update offsets for SPR hw block and validation of ROI
during atomic check based on SPR hw block limitations.
Change-Id: I9e20af4ba7752e8a4af5e9738612c57603163744
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Current computation of line time does not include compression ratio
from either DSC or VDC. This change stores source bpp and target bpp in
sde_crtc during sde encoder mode set to be used while calculating line
time.
Change-Id: Ib1e045dce17fcf006447d4562b402cc3f214ed8c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.
Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Current wakeup time is surpassing next vsync and not being used.
This change will use mdp transfer time calculated by dsi to compute
line time in command mode. In video mode, fps will be used to compute
the line time. This line time will be used with current interface
line count to calculate time until the next vsync.
Change-Id: I0b6fc396711ade95ecf95755a907280309af223e
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
Add a QoS vote on CPU receiving display interrupt. QoS vote
will prevent that CPU from going into low power mode avoiding
possible interrupt latency. Using irq notifier, display will
receive notification when display IRQ has switched CPUs and
will adjust the vote accordingly. The vote is also removed and
requested whenever display IRQ is enabled or disabled.
Change-Id: I94b4501896b4b20b37deaca90d6b5ff883d56621
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
