Commit Graph

478 Commitit

Tekijä SHA1 Viesti Päivämäärä
Lei Chen
4e679c086d disp: msm: dsi: Enable ESD check after POMS done
ESD check is disabled while switching panel operating mode.
This change enables ESD check after panel operating
mode switch is done.

Change-Id: I421d70d9be4c14107a7b51470801157d28874ffb
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2019-09-04 15:18:27 +08:00
Tatenda Chipeperekwa
1d1ce83ab1 disp: msm: dp: remove session lock for power state update
Remove session lock for power state update to improve functionality
for fast hotplug use cases. This allows the controller and aux modules
to be updated asynchronously based on hotplug state. For example,
in disconnected state all aux transactions will be aborted.
Updates to the power state can be done without the session lock
since this path is only exercised during compliance testing.

Change-Id: Ibe175624ef56d9f7b953b9b54928682f1cac906a
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2019-09-03 18:01:58 -07:00
Tatenda Chipeperekwa
93893b319b disp: msm: dp: clear scrambler bypass for test pattern 4
Clear the scrambler bypass bit while programming test pattern 4
for electrical compliance. This bit is only used for debugging
purposes and must be unset in order to get the correct test pattern
output from the controller.

Change-Id: If54ba17dc5bdd096899cf57cc4f276aab1837308
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2019-09-03 17:01:02 -07:00
Bruce Hoo
52eed6a827 disp: pll: update dynamic dsi clock sequence
Update dynamic dsi clock sequence for 7nm pll, change the register
which is used to store pre-cal code.

Change-Id: I0cd700f65a1dca965372adbda83416dfbbddd60f
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
2019-09-03 16:31:46 +08:00
qctecmdr
dc7e1224cc Merge "disp: msm: add length check for debugfs_ctrl" 2019-08-30 20:06:42 -07:00
RAJAT GUPTA
078b0f0793 drm: msm: dp: turn off audio before dp lane status toggling
There is an audio turn off timeout error whenever DP handles
the link state toggling requests from sink during audio
playback session. The audio hw is waiting for DMA write done
interrupts before issuing a audio session tear down. As the
DP controller is put into reset before link training, the
DMA write done is not sent by the DP controller hence causing
audio timeout errors. These changes turn off audio before the
DP controller is put into reset so that the audio session
tear down takes place within the stipulated time.

Change-Id: I7b88d0385a84f308d8537c2766e6fbc25a2ddc3b
Signed-off-by: RAJAT GUPTA <rajatgu@codeaurora.org>
2019-08-30 15:17:40 +05:30
qctecmdr
643c2e2fce Merge "disp: msm: vote for reg bus during rsc pm_runtime events" 2019-08-29 11:06:13 -07:00
Prashant Singh
4145770b07 disp: msm: add length check for debugfs_ctrl
Add check for length of debugfs_ctrl value before
copying to user buffer invoked during read operation.

Change-Id: I199110992921d0ae3791129fa0bf1e51dcca9107
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
2019-08-27 20:34:45 +05:30
Veera Sundaram Sankaran
386dd329c5 disp: msm: vote for reg bus during rsc pm_runtime events
Add reg bus vote separate for RSC on top of the SDE
driver vote during the pm_runtime suspend/resume
events to avoid register access issues.

Change-Id: Ifbaead747b7b10db107696c8cce8e1ecfae5e0f8
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-08-26 16:06:50 -07:00
qctecmdr
685240ed01 Merge "disp: msm: get and release lock on msm_obj before put iova" 2019-08-26 14:02:54 -07:00
qctecmdr
220f4941da Merge "disp: msm: dp: fix test pattern selection" 2019-08-26 08:54:42 -07:00
qctecmdr
103fc67d5c Merge "disp: msm: sde: add SSPP CP features to dirty list during IPC" 2019-08-22 01:20:22 -07:00
Dhaval Patel
6f06e5cd6f disp: msm: sde: wait for specific pp_done instead of zero
2 Frames transfer pending is possible with posted start.
One ongoing frame and another triggered frame. Current SW
waits for pp_done interrupt if pending frame count is greater
than 1. It is possible that interrupt may be missed for ongoing
frame. In that case, SW should run pp_done wait for one by one
frame instead of two frames together. It allows encoder to
check the ctl scheduler status and trigger the frame done
event on time.

Change-Id: I4817842292d96747890ee70da8a5bdf9b56816ed
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-08-20 21:12:52 -07:00
Ajay Singh Parmar
8fb6f89363 disp: msm: dp: fix test pattern selection
Use one level lower test pattern in case the current
test pattern fails to train link. This helps with few
monitors which sometimes fail with a selected test
pattern. Instead of failing the link, try with a lower
test pattern.

CRs-Fixed: 2507729
Change-Id: I394253398f49b03084dc547dacaededa49a9c527
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-08-19 14:36:17 -07:00
Samantha Tran
27b60379d1 disp: msm: get and release lock on msm_obj before put iova
This change will acquire the proper lock before calling
put_iova and release the lock on return.

Change-Id: I04334597018a6041eab0107660b2d441f8e3cc92
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-08-19 11:55:59 -07:00
Vishnuvardhan Prodduturi
ea1176e4f8 drm:msm:dsi: Add check for max controller count
Add check for max controller count while iterating through
display ctrl structure to avoid out of bounds access.

Change-Id: If4d32c648e7d34591726286226600a92a357479a
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
2019-08-16 18:35:07 +05:30
Christopher Braga
47ecefa419 drm: sde: Remove feature support for IGC/3D LUT for virtual planes
Attempts by virtual planes to set IGC and 3D LUT values are unsupported
and will result in LUTDMA hangs. Update virtual DRM planes capabilities
to disallow these features and make any attempts to set them a NOP.

Change-Id: I50eee7e981208ba53dfae833ab53b8fd0e5cda4e
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2019-08-14 10:39:54 -04:00
Prashant Singh
dc6f198f99 disp: msm: add null pointer sanity checks
Add missing null pointer checks for variables
before referencing them.

Change-Id: I5592ea136d2759e0a4adb288492c6ef00ae79c4d
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
2019-08-14 18:04:45 +05:30
qctecmdr
2f41e9ab66 Merge "disp: msm: sde: ensure LUTDMA is complete when auto-refresh enable" 2019-08-13 21:01:42 -07:00
qctecmdr
778635ae10 Merge "disp: msm: sde: cache vbif QoS parameters" 2019-08-12 22:36:26 -07:00
qctecmdr
c0a6abefe7 Merge "disp: msm: fix re-entry problem for msm_atomic_commit" 2019-08-12 19:15:32 -07:00
qctecmdr
b1ad60a7fd Merge "disp: msm: dp: use the correct checksum for EDID" 2019-08-12 09:49:12 -07:00
qctecmdr
fa73055e20 Merge "disp: msm: sde: fix release fence signaling in error cases" 2019-08-12 02:41:05 -07:00
qctecmdr
50e8ef62d3 Merge "disp: msm: add proper null checks and propagate error" 2019-08-11 20:21:19 -07:00
qctecmdr
61d32e7925 Merge "disp: msm: sde: update splash resource allocation for dual display" 2019-08-10 07:51:01 -07:00
qctecmdr
70bb28eaba Merge "disp: msm: dsi: set default value of PPS CMD delay to zero" 2019-08-09 19:20:51 -07:00
qctecmdr
105e91a931 Merge "disp: msm: dsi: update the threshold time based on panel jitter" 2019-08-09 16:06:03 -07:00
qctecmdr
0193855c3c Merge "disp: msm: sde: fix dsi bridge init" 2019-08-08 21:14:07 -07:00
qctecmdr
2a9da1c03b Merge "disp: msm: dp: fix register read/write delays" 2019-08-08 16:50:41 -07:00
qctecmdr
28022d54f0 Merge "disp: msm: dp: fix dp_display module's state handling" 2019-08-08 16:50:40 -07:00
qctecmdr
6cdf3b339e Merge "disp: msm: dp: synchronize debug and aux common buffer handling" 2019-08-08 16:50:40 -07:00
qctecmdr
c19743bbc6 Merge "drm/msm/dp: remove qfprom reference from dp driver Remove qfprom regmap reference from DP driver as it is not used anymore." 2019-08-08 07:09:16 -07:00
Jayaprakash
527692f6f4 disp: msm: sde: ensure LUTDMA is complete when auto-refresh enable
Currently LUTDMA kickoff is immediately followed by CTL flush,
immaterial of the LUTDMA DONE status in command mode. If LUTDMA
kickoff happens too close to the read_ptr in auto-refresh case, it might
cause a race condition between LUTDMA & CTL flush, due to a HW issue.
Serialize LUTDMA & CTL flush by making the LUTDMA kickoff as blocking
to avoid the race condition in auto-refresh case similar to video mode.

Change-Id: I4f4ae90a2c4f1bc8a0686d8fd4f8aa439123c531
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-08-08 18:02:23 +05:30
Prashant Singh
dbb1a3eee9 disp: msm: sde: update splash resource allocation for dual display
Correct the splash resource allocation counter for getting ctl
ids as passed from uefi for dual-display usecase for successful
splash-handoff.

Change-Id: Iffb6649073443e3c319077318e009b910ea53416
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
2019-08-08 15:11:52 +05:30
Veera Sundaram Sankaran
5a2dfc1e83 disp: msm: sde: fix release fence signaling in error cases
Handle release fence/frame-done error signalling for
error case like esd failure, pp_done timeout, interrupt
disable on cpu, etc. It fixes the race condition for
pending_frame count update and also triggers correct
wait function for wr_ptr wait failure.

Change-Id: Iad08f20592c97221a1626bb40e607c398a9812b6
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-08-07 18:56:47 -07:00
Vara Reddy
122b647775 disp: msm: dsi: update the threshold time based on panel jitter
Minimum threshold time is sum of panel jitter time, prefill lines time
and buffer time of 100usec. For panels with high jitter, we can cross the
default threshold time. Update the calculation to accommodate high jitter
panels in calculating dsi clocks.

Change-Id: I93163a07c7d0b51eb3704609b4efed6c1e277761
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2019-08-07 16:36:45 -07:00
Satya Rama Aditya Pinapala
7e77b664bb disp: msm: sde: fix dsi bridge init
Initialization of DSI external bridge must be done within
the initialization of DSI displays. The current method
has the drm_ext_bridge_init being called outside the
loop of DSI displays, and it will fail as the display,
encoder and connector handle are not present.
This fixes the regresion caused by
commit edef6ae040 ("disp: msm: dsi: snapshot of dsi from
4.14 to 4.19").

Change-Id: I50d0a303c2c8f4323e46cf14df1b071ebae80ceb
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-08-06 19:32:22 -07:00
Ajay Singh Parmar
4ca56193c5 disp: msm: dp: synchronize debug and aux common buffer handling
DP debug module is run by external script for automation testing.
DP aux and debug modules operate on shared buffers. In some race
conditions, aux and debug module can go out of sync resulting in
automation failures. Lock the buffers to make sure there are no
race conditions.

Change-Id: If0ae370c22cf035f3177666bd714221d6b3cd56e
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-08-06 15:32:21 -07:00
Samantha Tran
c00bf10768 disp: msm: add proper null checks and propagate error
Fix possible null pointer dereferencing and propagate error
code during early return.

Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-08-06 14:47:18 -07:00
Ajay Singh Parmar
9eb1b41671 disp: msm: dp: fix register read/write delays
Currently, for every DP hardware register read/write, there
is a string comparison to determine the execution mode. This
adds up an extra delay while powering up/down which does a
large number of register reads and writes. During stress
testing and automation, this can cause an issue resulting
in failures. Remove the unnecessary delays by using common
APIs for register reads and writes. Switch these APIs only
in case of execution mode change.

Change-Id: I9403873a29b3466c606297b2aa386d0885bb2dc7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-08-06 12:55:48 -07:00
RAJAT GUPTA
c22348bfd4 drm: msm: dp: change voltage swing levels for lito/kona
Change HBR and RBR voltage swing level for 600mV-3.6db
settings on lito/kona as per hardware specification in
dp phy hpg.

Change-Id: If86bf158fb8b538d7ea31364a757584201d5f1c3
Signed-off-by: RAJAT GUPTA <rajatgu@codeaurora.org>
2019-08-06 12:10:33 +05:30
Satya Rama Aditya Pinapala
2059ae463b disp: msm: dsi: set default value of PPS CMD delay to zero
Fix the default value of post PPS command delay to zero, if
it is not specified as a panel device tree property.

Change-Id: I9aa972839d8be0620036595ac2514290cc6cf697
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-08-05 14:14:44 -07:00
Satya Rama Aditya Pinapala
c32df7879d disp: msm: dsi: add check to avoid null pointer access
Add a check for valid pointer in the DSI CTRL logging macros
to fix null pointer access issues.

Change-Id: I92576e1db6c2d8b52c2adddd8c964bc2455536e4
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-08-05 10:22:46 -07:00
qctecmdr
9081908beb Merge "disp: msm: sde: convert event logs to verbose" 2019-08-04 20:59:36 -07:00
Ajay Singh Parmar
488cb89f09 disp: msm: dp: fix dp_display module's state handling
Currently the DP display's states are not able to handle
the use cases like suspend/resume. The required steps of
host initialization and ready are not properly followed
in such cases. Define proper DP display states, set and
unset at the right places to make sure dp is in proper
state in such cases.

Change-Id: Ibf6d35dec3ab373a7225b30ac1c2f9864bb6ff78
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-08-02 17:26:39 -07:00
qctecmdr
c70f647143 Merge "disp: msm: dp: correct the resolution width check in get_mode_info" 2019-08-02 13:42:29 -07:00
Nilaan Gunabalachandran
08116fb279 disp: msm: sde: convert event logs to verbose
Reduce event logs to verbose only because they do not need
to be logged every frame.

Change-Id: I753154dc4b13cfce1382615b02e8fc7e489a5993
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-08-02 11:41:55 -04:00
qctecmdr
3aa07c4957 Merge "drm/msm/dp: add checks to prevent buffer overflows" 2019-08-02 07:47:14 -07:00
qctecmdr
fed3b2bb45 Merge "disp: msm: sde: add dsi debug bus for kona device" 2019-08-02 05:16:34 -07:00
qctecmdr
c407b8b72f Merge "disp: msm: sde: add trace points for modeset" 2019-08-02 03:24:46 -07:00