For SW2HW ring, if time threshold is non-zero and low threshold
is 0, then if ring is empty, HW will keep generating low threshold
interrupt always which then LPL failed.
Configure SW2HW ring timer threshold 0 to disable low threshold
interrupt, also set batch_count threshold 0 as host not need the
interrupt if HW consumed entries.
Change-Id: I6c8ea516e66abd706fecd97649f3a19702453b85
CRs-Fixed: 3149341
Add support to change the tx_desc value to 65536. Some changes
to make the function argument as u32 type us made
Change-Id: I7cbde1b7ed4ab4e278c25c1ecfa94b7f673197f2
CRs-Fixed: 3130833
Make 1:1 dependency on num REOs and rx_thread. Keep num rx_thread
dependent on rx REO rings, 1 rx_thread for each rx REO ring.
Controlled via INI dp_reo_rings_map.
Change-Id: I7c199226cfa3f173ea328d71075816b8eb9ba91f
CRs-Fixed: 3048260
Ageout flush does not happen for WBM2SW4 if there
is only one TX completion pending in FIFO and all the
other WBM release rings are not active. This is due to
an issue in HW and this prevents suspend to happen due
to pending tx completions.
Fix is to avoid using WBM2SW4 release ring and instead
reuse WBM2SW0.
Change-Id: I250d8c9d460895449939212ebdb7abd62edb0234
CRs-Fixed: 3124733
Enable the 4th Tx. completion ring to save CPU load
Initialization and interrupt handling for 4th completion ring
is done here.
Change-Id: I2db27218a3c3e14d719d012f03454a6a7aa647fe
User can specify a limit and frames are dropped when the memory
used by packets in the queues goes beyond the limit. This is a
SoC level param.
Change-Id: Id2bd9caaa11d9ea9f9e04c635ff629190bb62916
Currently, we are assigning 9 MSI Vector to DP.
But in some target available MSI Vector are less
because of which they are unable to assign 9 MSI
Vector to DP.
So, to fix the issue reduces MSI requirement for
DP from 9 to 7 and mux DP interrupts.
Change-Id: I48da2d0e8921db3298903a398f981e5b45a60987
CRs-Fixed: 3111170
- Fixes for compilation issues after enabling
monitor 2.0 support.
- change copyright year for all files in the chain.
Change-Id: I885e257bd8ca83850656d8a1f408c1bc34920d7a
CRs-Fixed: 3086483
Add the PPE Tx HAL data structures. Also add
dummy functions for reo2ppe and ppe2tcl rings
intializations.
Change-Id: I31fa61a728535c32ea3678407da8ae39f0d9f48d
For WCN7850, the first mac (i.e.. MAC0) is capable of
2G/5G and 6G data transfer. Hence initialize and use
only on RXDMA monitor status ring.
Change-Id: Idb6e23a887a9ed32a52dd54765e5ed3c6a12df06
CRs-Fixed: 3094138
Enable the interrupt based processing in monitor mode
for WCN7850, by enabling MSI interrupts for rxdma
monitor destination ring.
Change-Id: Ia3c4456d28ed58c8ef49a7aa8e711076fbdf9415
CRs-Fixed: 3094129
WCN7850 has only one RXDMA DST ring, as opposed to other
lithium family chipsets, which had 2 RXDMA DST ring.
Refactor the code to pick the number of rxdma destination
rings from CFG context.
Change-Id: I20d475c02690043e969bc7a78605809b8c6814ae
CRs-Fixed: 3084440
Use chip ID and destination peer to determine the target soc
and partner vdev for Intra-BSS in MLO case.
Change-Id: I709c52e74426c5e81b50c8063cad7669c0e7002d
Offsets used by host for HTT stats are not aligned as per the
structure declaration given in file htt.h .
Make change to use the correct offsets to get the correct stats.
Also make change for byte count computation.
Also make cleanup changes for FR65817.
Change-Id: I8bc6164cc4994c49536d7277779f25b258be1592
CRs-Fixed: 3082742
Add configuration at SOC level for hw vdev stats in BE architecture.
Following config parameters are added:
vdev_stats_hw_offload: option to enable/disable hw vdev stats
hw_vdev_stats_timer: timer duration for hw vdev stats
Change-Id: I8cbd2b6a7378d8a9e7de920a3a6fdff0cf7785fe
CRs-Fixed: 3067843
In case of WIN hal_soc will be freed in wifi down
path, this pointer is not valid at pdev_detach or
soc_detach.
Change to populate dmac source ring flag to dp_soc
as access is needed at pdev_detach or soc_detach
Change-Id: I628746bdd05ba3791d3d0e6b6dfdf160ed368e9a
Rx patch changes for multichip MLO
1. Create ini for rx ring mask for each chip
2. Configure hash based routing for each chip based
on lmac_peer_id_msb
3. Peer setup changes to configure lmac_peer_id_msb
to enable hash based routing
4. Rx Replenish changes to provide buffers back to owner
SOC of reo ring
Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
This force use BA64 ini config is no longer needed, because another
gRxAggregationSize can do the same settings and more flexible.
Change is used to remove this config.
Change-Id: Ie780489849f8b701481a628a9bca2b4112460bd8
CRs-Fixed: 3076982
Dynamic GRO feature is enabled by default and aimed for specific
customers. Add an ini control to allow other customers to config
this feature enable/disable.
Change-Id: I7f505599327ac131b3cdac9b4d9e038861b1aeb6
CRs-Fixed: 3074689
For IPQ products, there is 1 refill ring which is of hardware type
and host replenishes the buffers onto this ring so that hardware can
use these buffers for Rx.
In IPA offload mode, the buffer replenishment model is different from
the one mentioned above. There are 3 refill rings, out of which,
2 are software refill rings (1 for host and 1 for IPA), and last ring
is hardware ring given to FW.
Ring given to IPA is to refill the buffers after processing the
regular Rx packets and ring given to host is to refill the buffers
after processing of exception packets. Since there are 2 entities to
refill the buffers, the hardware ring given to FW multiplexes these 2
software rings and provides the buffers to hardware.
Make changes to follow above replenishment model for SDX+Pine
integration.
Change-Id: I0d9e4ec811a3023a258e0a6b9ee22ccdffcebafa
CRs-Fixed: 3049633
ipa_enabled cfg parameter is updated in DP post soc_attach
and soc_init and the default value of ipa_enabled in soc
cfg context is 0. ipa_enabled cfg is used in soc_attach
and soc_init for tx and tx completion ring configurations
and could potentially cause issues when ipa is enabled.
Fix is to update ipa_enabled config as part of dp soc
ipa_config_attach.
Change-Id: Ia797d8feed8aff619b0f7f63ba7ec5823c82458c
CRs-Fixed: 3075076
INI config to set the number of tx rings to 1
or 2 does not take effect since the value of
WLAN_CFG_NUM_TCL_DATA_RINGS_MIN is 3.
Fix is to set WLAN_CFG_NUM_TCL_DATA_RINGS_MIN to 1
to allow for a lower number of tx rings cfg.
Change-Id: Idc7881f75d42fabda5d3ed55e74c9eb784f7705f
CRs-Fixed: 3070272
Repurpose the IPA tx and tx completions rings for
normal use when IPA is disabled either via config
flag or ini.
Change-Id: Ia4b6a89c73d888a217bdef40e3c05435c3bb1bb2
CRs-Fixed: 3059730
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
Currently the IRQ mask for tx completion near full
interrupt is not in sync with the tx completion rings
which are enabled for WCN7850.
Fix the mask for tx completion near full interrupt.
Change-Id: I1432191b260094060873406d48e04fde5b7bc35e
CRs-Fixed: 3052650
Some platforms do not support cached descripts for DP Rings.
Add support to set WLAN_CFG_DST_RING_CACHED_DESC to 0 and make
__qdf_nbuf_dma_inv_range as stub if DP_NO_CACHE_DESC_SUPPORT flag is
enabled during compilation.
Change-Id: Ic6b483be25c32f3f3c79b170fb7d7557a232b4ac
CRs-Fixed: 3027649
Currently, rx packet capture events processing happens even
when feature is disabled by ini. This incurs per packet overhead
in rx path.
The fix is to move all the processing from rx path to packet capture mode
component. Send only wdi event from rx path, when feature is enabled by
ini.
Change-Id: I647256b85117cd3373950c78a5a0ae7d6710e4e2
CRs-Fixed: 2969123
Add support configure ipa tx ring and tx completion ring for
2.4G and/or 5G separately.
Change-Id: Iafb8fa589ff0cce15609a3dfa2209364291d7cef
CRs-Fixed: 2996604
Set default value 7 for INI dp_reo_rings_map, this is just
one WAR to not block HMT before reo_ring_remap and dp thread
issue is fixed.
Change-Id: Ib2c8ebab936951798112759e1ac0baba85996036
CRs-Fixed: 3005555
