This change avoids sde error during fal10_veto override enablement
for targets with uidle disabled and early returns in such case.
Change-Id: I491952615d7b3cbd70d35b4a90ee8d27ab56c2ad
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change fails the drm_atomic_commit and avoids S2 translation
fault if drm_gem_object is found attached to a secure context bank
during non secure session. In the current codeflow, we are detaching
the gem object from secure CB and reattaching it to non secure CB,
but only S1 pagetables entries get modified and S2 pagetables entries
are not corrected since hyp_unassign is not called with CP_PIXEL
VMID which can only be done by client when buffer gets allocated.
Change-Id: I62302064f96276ef82044ee88fb89e295fb96b4b
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change updates framedata event and ubwc stats API to
align with userspace handling and expectations.
This change adds the empty irq event handler required to register
the frame data event.
This change also adds handling to the crtc event notify to provide
the payload pointer directly, required for the buffer object,
ensuring pointers are not mismatched while sending drm events.
This change also updates the ubwc roi plane property to process the
uapi defined roi.
Change-Id: I209f2b7418a0ec33aa0488119eb3fdb8ae94e8ba
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
When cwb is enabled enable software override for fal10 veto to
block fal10 entry as MDSS can keep asserting uidle if there
are no fetch clients like dim layer only usecase.
Change-Id: Ief51499d370c20fcbdda79576aee0179578650fd
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change dumps the userfds input_fence info in dma_fence_array
on speculative fence wait timeout. This will be helpful to isolate
the real fence timeouts when spec fence bind gets successful.
Change-Id: I6aa37a06025f5ea43aaed8733f0803bfadd260fd
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
During virt disable call, sde_enc master was used without checking
for null condition. It results in crash. This change adds required
null pointer check for sde encoder current master before dereferencing
to avoid crash.
Change-Id: I69ee17017712ea3549bfefce5975a564a5a8c2e9
Signed-off-by: Yojana <quic_yjuadi@quicinc.com>
This change avoids alignment condition check if the format is
linear because HW can fetch without any restrictions only in linear
usecase.
Change-Id: Ib823a8d309f7ed579d701a4bf56772ce318fb1f5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
During the first commit, crtc state will be duplicated from the
crtc state populated with splash data. In this case, crtc will
already be set to active, but active_changed will remain cleared.
This will skip the power on event being set during complete commit
phase. This change checks for the cont. splash enabled before
sending the power on event.
Change-Id: I9964317d96468213e9abe9b029e64aa2981fb359
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
As per HW recommendation, FAL10_VETO_OVERRIDE register can
be programmed to disable FAL10 in alternate to disabling
uidle at the sspp level as disabling UIDLE controller will
only disable DPU traffic shaping and will not stop the
system from entering FAL10 state. This change programs
FAL10_VETO_OVERRIDE register during uidle disable and also
sets CTL_x_UIDLE_ACTIVE register to always one to avoid
race condition between different CTL paths.
Change-Id: I9c55f5da2037cb8c448cc978eac0a04608a93650
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Large allocations using kzalloc can lead to timeouts. This updates
the allocation calls accordingly to use vzalloc to remove
requirements on contiguous memory.
Change-Id: I86fa0ae13277d97477210a082703514df792d8a9
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
With full DSC size of 20k, RT performance issues are seen due to the
stress created during larger prefill needed to fill up the 20k DSC buffer.
Limiting DSC size to 10k helps to mitigate these RT performace issues.
This change adds support for this based on new flag has_reduced_ob_max
in sde_mdss_cfg data structure. Flag has_reduced_ob_max has be set
true only on targets where its recommended.
Change-Id: I649d213bcd378025bd0548fb982b55c98c99224f
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
This change adds pp_tx during DMS switch for sim panel to
prevent WD timer getting updated in middle of the frame and
creating early vsync which might result in ppdone timeout.
For non-sim panels, this tx wait is not required and is
done similar to posted start.
Change-Id: Ifec68535efa19df27e651ce0a39c03627dff2089
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
In mid and low tier targets there is reduction in pingpong
blocks and static allocation of pingpong blocks with respect
to dedicated cwb ids causes mismatch failures and leads to
wb kickoff timeouts. This change corrects the pingpong block
id allocation for dedicated cwb in dither control register
programming path.
Change-Id: I98c06a2c3b49c7ea0556dcf1a921969c300fed16
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change avoids setting of max vblank count in crtc
enable if accurate vsync timestamp feature is disabled.
Change-Id: I6d8299359f581a162a7412da8c9b673e3aeae041
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Below is the sequence during which issue is observed
while using stale lut values:
1) Scaler block is enabled in the VIG pipe along with the
valid lut configuration.
2) Idle work gets scheduled and GDSC is turned off erasing
the saved lut values.
3) At the same time, userspace sends a commit assuming lut
values are still valid resulting in artifacts on the
screen.
In the plane state scaler config, only lut flag will be
reset for subsequent commits and remaining properties such
as filter cfgs, lut_idx etc. remains same. This change
caches the lut flag in sde plane whenever the lut is being
set and reuses this flag to handle above issue.
Change-Id: I7d83d5e7a22a73a2d94b100dffe60316f92ec309
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
During DMS, when tear check registers are updated near
rd_ptr line count, it was resulting in a spurious
rd_ptr_irq to which frame is getting latched and causing
tearing on the screen. This change updates
TEAR_SYNC_WRCOUNT register before disabling the vsync
counter and adds a spinlock to avoid pre-emption.
Change-Id: I986dc3ce6fb3da5fed758c2f50562df44f2ab557
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
At present, idle_pc_enabled flag will be set for encoders
containing only these capabilities MSM_DISPLAY_CAP_CMD_MODE
and MSM_DISPLAY_CAP_VID_MODE. When cwb is triggered,extra
power vote will be taken during kickoff and vote remains
till cwb is disabled. In between, if primary goes into idle
power collapse, vote taken by cwb will not be removed since
idle_pc_enabled flag is not set. This change updates
idle_pc_enabled flag for all encoders based on catalog
property.
Change-Id: If4f147edbd610d0302e4d6c0a3e6b7de2c729db1
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Flush ESD status work before resetting the encoder state during
virt_disable sequence to avoid stale pointers being used in
the ESD work.
Change-Id: I4bb08a7a7ae33ad6386169667692736e554141c4
Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
This change allows concurrent qsync updates along with
DMS modeset condition. With this change, qsync can be
enabled or disabled in the same atomic commit along with
MSM_MODE_FLAG_SEAMLESS_DMS condition.
Change-Id: I1b51a68f947126b25a578645e92d95c9a8ae26f5
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
When a new connector is added or removed an a crtc because
of clone mode enable and disable update cached encoder mask.
Currently since cached encoder mask is not updated properly
vblank frame counter is returning wb encoder frame counter
right after clone mode disable on wb encoder.
Change-Id: Ieff9dfbf0c7df3688fb1b6f9d3f3614345b494c2
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
DCS commands triggered right after timing engine enable can conflict
with blanking period causing command transfer failures. Right after
timing engine enable poll for frame start and line count reaching
active region of display before any DCS commands.
Change-Id: Ia3967e01c3bb5bc82aa3549c300fa8335e00210c
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Currently ot limits are being set for concurrent writeback,
which is not supported. This change adds a check to correctly
set wfd parameter while applying ot limit settings.
Change-Id: I87c1ca756c1714fec4466cd5a5a820ddf2519975
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change acquires the vm lock before pre-releasing the
dependent drivers. This avoids any race condition on any
parallel async commands transfers scheduled on connector
drivers. Additionally the main irq line is only disabled
after the pre-release to allow any ongoing transfers
to complete.
Change-Id: Ic0bffc93ebb1b69fbd8d1f096b320a86ad84c857
Signed-off-by: Abhijit Kulkarni <quic_kabhijit@quicinc.com>
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.
Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
allocates new resources and CTL_1 is allocated.
sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.
Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
If vm has already transitioned from primary to trusted,
triggering a wb/secondary display commit will result in
crash since hw is not owned by the vm. This change adds
necessary changes to fail atomic check in such usecases.
Change-Id: Ic9886d479726c27d1072d12304a87f3bf5deeb76
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change sets CTL_UIDLE_ACTIVE register whenever uidle
is enabled and resets it only when uidle is disabled.
Change-Id: I0393d1585df4fdb79a844d04df62ac9eda949232
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
