提交图

2443 次代码提交

作者 SHA1 备注 提交日期
qctecmdr
c9fb272a73 Merge "disp: msm: dsi: allow cmd-engine enable/disable HW op at all times" 2021-08-13 20:50:45 -07:00
qctecmdr
7986d0d1b1 Merge "disp: msm: dp: add support for 3.75:1 compression" 2021-08-13 08:58:26 -07:00
qctecmdr
7ec82f88a8 Merge "disp: msm: add qsync refresh rate support per mode" 2021-08-12 14:10:43 -07:00
qctecmdr
e50cd5cb61 Merge "disp: msm: sde: remove clearing cur_master in encoder enable function" 2021-08-12 14:10:42 -07:00
Lei Chen
b151e6660b disp: msm: sde: remove clearing cur_master in encoder enable function
SDE IRQ callback can run in parallel thread to modeset after removing
pp_done wait before pre_modeset.
If cur_master is cleared in encoder enable function and irq callback
is triggered at the same time, the irq callback could not be handled
properly as cur_master is NULL.
So remove clearing cur_master in encoder enable function to avoid the
race condition between modeset and irq callback.

Change-Id: I2059c699a68838b3c9f6a7dd658a35f178b18c42
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-08-09 10:58:38 +08:00
Rajkumar Subbiah
eebce2ae4c disp: msm: dp: add support for 3.75:1 compression
Currently the DP driver always uses a compression ratio of 3, if
DSC is enabled. So if the sink supports 30bpp, the compressed
output is set to 10bpp. But since the hardware supports
compressing this to 8bpp, it would require less link bandwidth
than 10bpp compressed output. For compliance testing, the
test equipment limits the link bandwidth based on the most
efficient compression ratio and for some resolutions there
is not enough link bandwidth for 3:1 compression.

This change always sets the compression output to 8bpp to
minimize the link bandwidth utilization.

Change-Id: Ifa6129444c2bab4e9c357ddfe49f76efa5b04be0
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2021-08-05 20:26:34 -04:00
Rajkumar Subbiah
17997f6098 disp: msm: dp: update TU calculator for DSC and RB2 support
Updating the TU calculator to fix the formulas for the following
two use cases:
* 3.75:1 DSC compression
* Modes with RB2 (reduced blanking) timing.

Change-Id: I295e3fc252691a7fb42b610101da32c9f31d1855
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2021-08-05 20:26:34 -04:00
Yashwanth
64b732f335 disp: msm: add qsync refresh rate support per mode
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.

Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-05 15:37:20 +05:30
qctecmdr
6bf96605eb Merge "disp: msm: sde: cache disable cp properties during last close" 2021-08-03 19:17:54 -07:00
qctecmdr
8a2ddb713f Merge "disp: msm: sde: expose number of rounded corner blocks" 2021-07-30 10:14:21 -07:00
qctecmdr
f7e7964840 Merge "disp:msm:sde: correct the brightness bound check" 2021-07-29 19:41:43 -07:00
qctecmdr
f4f3c29d70 Merge "disp: msm: dsi: fix RFI mode set detection" 2021-07-29 14:48:53 -07:00
Gopikrishnaiah Anandan
610b71feb9 disp: msm: sde: cache disable cp properties during last close
When all instances of driver fd's are closed by user-space client, drm driver
will be closed. When last close of driver is called, custom reset properties
api will be called where driver should cache the properties that it wants to
clear. Current behavior of color processing driver is to clear hardware
configuration instead of caching which can cause crashes if clocks are off.
Change updates the driver to cache the pending disable and update hardware
during display commit.

Change-Id: I9703f860ed0ae3c859d6fc3995b58be13203f259
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2021-07-29 13:56:02 -07:00
Amine Najahi
0c8c956b1f disp: msm: sde: expose number of rounded corner blocks
Expose the number of RC hardware blocks to handle multi-display
use cases where RC feature needs to be enabled only if there
are sufficent RC hardware blocks available.

Change-Id: I37fe3ee4ac72894d9d51e832551d3fc19c0354b8
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 15:10:24 -04:00
qctecmdr
bc1b84e6fc Merge "disp: msm: sde: update rsvp_cur when poll is enabled for rsvp_nxt" 2021-07-29 10:12:51 -07:00
Amine Najahi
e3c76571dc disp: msm: dsi: fix RFI mode set detection
Currently mode fixup function is called multiple times
in the same commit. This causes invalid combination of
DSI mode flags to be set when there is an RFI change
with proch compensation feature enabled.

This change modifies the mode switch condition for DMS
to compare internal dsi mode and flags and fixes the
dynamic clock change detection by using a single variable.

Change-Id: Iaf9c8ca7c6a27f26aefead399bc93fbbb02b404b
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 07:43:27 -07:00
Amine Najahi
1881acdb2b disp: msm: dsi: publish RFI porch values for rate matching calculation
Currently when RFI is used on a video mode panel the horizontal or
vertical front porch values can be adjusted to maintain a constant FPS.
When this feature is enabled, driver is not propagating the new
htotal or vtotal values to usermode for accurate BW and MDP clock
calculation, which may lead to underrun in some usecase.

This change publishes beforehand all the RFI related timing
such as compensation type, hfp or vfp and clock values for
each mode for accurate BW and clock calculation.

Change-Id: Ib89c5e318fe978b0ae2215dedc430e057a9a81b9
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 10:35:27 -04:00
Ping Li
b7506f0222 disp:msm:sde: correct the brightness bound check
The brightness value from backlight device is OS brightness, not panel
backlight value. This change corrects the brightness bound check to
check against the OS brightness max value instead of panel backlight max
value. This change also move the bound check in dsi display to make sure
the max backlight value send to panel is within the expected range.

Change-Id: Ic9e3ba69700ae4c0e950cb665837a1f0a1317b26
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-07-28 12:32:45 -07:00
qctecmdr
b04d8af8da Merge "disp: msm: dsi: update DSI PHY HW programming" 2021-07-28 06:06:16 -07:00
Jayaprakash Madisetty
0a56792383 disp: msm: sde: update rsvp_cur when poll is enabled for rsvp_nxt
This change updates rsvp_cur pointer to latest to avoid use
after free issues. rsvp_cur pointer can be freed in few cases due
to the unlock, wait and lock of rm_lock present in
_sde_rm_poll_get_rsvp_nxt_locked.

Change-Id: I389048188e8a615edc3e75dd1102d4ca8c74af65
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-07-28 05:40:24 -07:00
Jayaprakash Madisetty
dad1b5f51e disp: msm: sde: handle spec fence bind failure case as non fatal
Add changes to handle speculative fence bind failure case with
invalid userfd as non fatal scenario and stage white frame in such
case.

Change-Id: I1386bfc5ecb5107ab100be220c24597f883d9bd6
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-07-27 13:22:51 +05:30
qctecmdr
2a5878a83f Merge "disp: msm: sde: Correct Demura memory parsing for single address per region" 2021-07-24 14:43:41 -07:00
qctecmdr
3d45203d45 Merge "disp: msm: dp: clear mst edid cache for real monitor plugin" 2021-07-24 04:52:53 -07:00
qctecmdr
e72cdd796f Merge "disp: msm: dsi: prepare resources for cmd transfer at the start of the cmd packet" 2021-07-22 19:51:32 -07:00
Satya Rama Aditya Pinapala
095f5dd58a disp: msm: dsi: prepare resources for cmd transfer at the start of the cmd packet
For batched commands, prepare resources at the start of the command packet and not for the
command with LAST_COMMAND flag set.

Change-Id: Ibbb0d1d1acd4ddeebd07bf9dd6ea1a949edd8d02
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-07-22 10:37:58 -07:00
qctecmdr
8ff5362a29 Merge "disp: msm: update register dump and debug bus memory allocation" 2021-07-21 21:20:52 -07:00
qctecmdr
2df9899db4 Merge "disp: msm: sde: add pr_fmt for SDE VM layer" 2021-07-21 21:20:52 -07:00
qctecmdr
48e71a3272 Merge "disp: msm: dp: account for fec overhead during bpp determination" 2021-07-21 07:18:36 -07:00
Christopher Braga
844e618c26 disp: msm: sde: Correct Demura memory parsing for single address per region
Demura memory region parsing incorrectly uses the display number
as an extraction index, causing failures in dual panel cases.
Update Demura memory region parsing to always use index 0 during
extraction as each defined region is designed to only declare
a single memory address.

Change-Id: I270f392b636148acd9b891bffcc3cf3d032eab70
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-07-20 17:02:21 -04:00
Sudarsan Ramesh
1def76170d disp: msm: dp: clear mst edid cache for real monitor plugin
Currently edid cache is cleared only in the mst attention callback
flow i.e. if a monitor is plugged in/out of a mst dongle. If mst
dongle is plugged out directly, the edid cache is not cleared.
This change clears the edid cache also during the
connect/disconnect callback.

Change-Id: Icc4b4ca6a59f1ee32f7fe062831a3a19f4ab9f00
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-07-19 10:40:22 -04:00
Steve Cohen
a42fd877c7 disp: msm: sde: cancel delayed work items during TUI transition
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.

Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.

Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-07-16 20:45:42 -04:00
Steve Cohen
cce49a77c5 disp: msm: sde: add pr_fmt for SDE VM layer
Add pr_fmt definition in SDE VM modules for simplifying
searching for DRM driver logs.

Change-Id: I3f83b52dec6479dd89306aed7d84e73928f4e9ef
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-07-16 20:38:10 -04:00
Satya Rama Aditya Pinapala
2582a00416 disp: msm: dsi: update DSI PHY HW programming
Change updates DSI PHY programming to match HW recommendation.

Change-Id: I09841e7a9eb73afd4c74363b4b20a598313f0ec3
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-07-16 11:36:38 -07:00
qctecmdr
a5da9d0045 Merge "disp: msm: sde: remove fb's attached to a drm_file in preclose" 2021-07-15 13:14:46 -07:00
qctecmdr
a44120edf1 Merge "disp: msm: sde: correct num_datapath during PM resume with CWB" 2021-07-15 13:14:46 -07:00
qctecmdr
e32c87abbe Merge "disp: msm: sde: modify in_clone_mode after wb_reset is done" 2021-07-15 13:14:46 -07:00
qctecmdr
f2208ec5a0 Merge "disp: msm: sde: reset dim layer dirty prop during idle pc" 2021-07-15 13:14:45 -07:00
Karthik Andhavarapu
2db495708f disp: msm: update register dump and debug bus memory allocation
In current implementation, register dump memory is allocated
separately for each range and block. When register dumps are
added to minidump, this will generate multiple minidump bin files
after a crash. Changes are made to allocate all the required
register dump memory once. When register dumps are added to
minidump, this will generate only one minidump bin file.
Use kvzalloc and kvfree to allocate and free this memory as
the memory needed to allocate is around 126 KB. Update the
allocation of debug buses also to kvzalloc and kvfree.

Change-Id: Ia5cca47b085bcca57ce09981a55cc1bfbeeae77e
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-07-15 23:00:09 +05:30
Jayaprakash Madisetty
436efb403c disp: msm: sde: modify in_clone_mode after wb_reset is done
Add changes to modify the phys_enc->in_clone_mode variable
post wb_reset_state since this is a shared variable used
during atomic_check and atomic_commit. In current issue case,
wb_atomic_check has set in_clone_mode to true in commit N,
and in commit N-1 CWB is being disabled and re-sets the
in_clone_mode variable to false causing pp_done timeouts in
primary in commit N.

Change-Id: I8159bbdb5622a351d76bdc4dba75d48df20f4365
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-14 13:43:21 -07:00
qctecmdr
7d0890d337 Merge "Revert "disp: msm: sde: update smmu fault handler to print debug info"" 2021-07-13 22:57:37 -07:00
Nilaan Gunabalachandran
2c320baeaf Revert "disp: msm: sde: update smmu fault handler to print debug info"
This reverts commit 0623a02a84. It leads to
panic during smmu faults because we do not have any recovery. Reverting
this will give the control to the client to dump if necessary.

Change-Id: I85982e129cabc73b041e25c35e965117d60f3bfa
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-07-13 17:43:37 -04:00
Nilaan Gunabalachandran
d452830710 disp: msm: sde: update supported format lists for wb
This change updates the supported format lists for wb connector.

Change-Id: Idf7e004780e963ef5937049dc1ddedae344697a0
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-07-13 09:44:43 -04:00
qctecmdr
0ee14ac910 Merge "disp: msm: fix CPU mapping for memory buffers" 2021-07-12 22:22:59 -07:00
qctecmdr
06c0d084bd Merge "drm/msm/sde: add check to fix null pointer dereference" 2021-07-12 18:26:36 -07:00
qctecmdr
c2819001b0 Merge "disp: msm: dsi: use dynamic memory allocation for dsi_display_mode_priv_info variable" 2021-07-12 16:29:01 -07:00
qctecmdr
00c6d076fa Merge "disp: msm: sde: allow event log logging with IN_LOG_LIMITED flag" 2021-07-09 12:23:24 -07:00
Steve Cohen
65f3cc37a4 disp: msm: dsi: allow cmd-engine enable/disable HW op at all times
In cases of continuous splash, when command engine is
enabled/disabled as part of commands that are sent before
continuous splash config is called the HW op will disable the
command engine by the end of the command transfer. As part of
continuous splash handoff, the command engine enable call skips
the hardware operation to actually set the CMD_ENGINE_EN bit
as it is guarded by the skip op flag.

With the current change, we allow the HW op to take place, despite
continuous splash being enabled. This way, the HW will always maintain
the correct state pre and post continuous splash handoff.

Change-Id: Id32ebf6f0d7eac46c118b701c138fcf6b9b10318
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-07-09 12:22:17 -07:00
Jayaprakash Madisetty
a29369e224 disp: msm: sde: correct num_datapath during PM resume with CWB
In PM resume with CWB concurrency usecase, crtc pointer in
conn->state is NULL since drm_mode_config_reset operation is
performed on pm_resume. This change relies on conn_mask in
new_crtc_state for primary connector retrieval and also adds
get_num_lm_from_mode callback to DSI for LM count retrieval
from dsi panel topology. Existing get_mode_info api cannot
retrieve the topology info because mode->priv_info is NULL.
This occurs as WB encoder is added in the drm encoder_list
before primary encoder, introduced as part of commit d28ebf05f4
("disp: msm: sde: populate WB display encoder list before dsi").

Change-Id: I55358fd88ab778bd81475cf3628be13335de1cb5
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-09 09:12:26 -07:00
qctecmdr
96d560a883 Merge "disp: msm: dsi: remove seamless dms flag during active changed" 2021-07-09 08:37:09 -07:00
qctecmdr
54ff96efb7 Merge "disp: msm: avoid using spinlock while adding evtlog entry" 2021-07-09 06:49:14 -07:00