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1071 Commits

Autor SHA1 Mensaje Fecha
Krishna Manikandan
e99063c7a3 disp: msm: stage layer with zorder 0 as base layer
Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.

Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-03-29 16:50:44 -07:00
Ray Zhang
782d4feb24 disp: msm: sde: Initialize wr_ptr_wait_success after kickoff
wr_ptr_wait_success is true only if wr_ptr interrupt arrives, so
initialize it after display kickoff.

Change-Id: I5790d9dac25352898ece160f6b258b50ca2edefa
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
2020-03-29 16:50:29 -07:00
Nilaan Gunabalachandran
53a5b3670f disp: msm: sde: update last power event handled correctly
Update triggered power event to last event correctly,
regardless of whether a callback is called.
Add event log to see debugfs clock rate change.

Change-Id: Ifa9c1ffb450f50a3928eb44362723b6d495b2354
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-03-29 16:50:17 -07:00
Veera Sundaram Sankaran
a9574eb8c2 disp: msm: perform delayed buf attach during secure transitions
While transitioning from secure usecases, the secure
context bank is attached back only during the commit
phase. This leads to invalid secure context-bank device
issue, when the prime_to_fd call is made for the next
frame. Avoid it, by attaching to default drm device
during the prime_to_fd call and reattach it to the
secure context-bank device at the delayed import time.

Change-Id: I43e6da7f117f20746943a48b5f2657e9ae2947ea
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-03-29 16:50:07 -07:00
Jayaprakash
e7f3931297 disp: msm: sde: Avoid releasing the committed RM reservations
RM allocated reservations for the ongoing commit are cleared when
there is a delay in ongoing commit scheduling and back to back
prepare comes. This clearing occurs in the subsequent checkonly
commit with modechange property set.

Timeline of the issue:
   --> C1 commit check_only + modeset, RM allocated resources
   --> C2 commit check_only scheduled before C1 commit with
       check_only + modeset, overridden C1 reservations with
       its own into rsvp_nxt
   --> C1 commit scheduled and RM committed reservations
       allocated by C2.

Change-Id: I46cc924fd6515590e32c8e97a82847d2bde97270
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-03-29 16:49:52 -07:00
Krishna Manikandan
ec6688849b disp: msm: sde: avoid CWB connector in determining active crtc
CWB connector is tied to primary crtc along with primary connector.
Avoid using CWB connector power state in determining active crtc,
as it is already done via primary connector.

Change-Id: I35ec95349790990c49b9a63afd6e0f55d23b4887
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-03-29 16:49:40 -07:00
Krishna Manikandan
4442431141 disp: msm: sde: cleanup writeback phys_enc structures during wb disable
Hardware structures for writeback ctl and cdm are set
to null during wb disable, to prevent crtc mode change
on primary during subsequent wfd and cwb sessions.

Change-Id: I7536203761c615c37c8633d1621951475895400a
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-03-29 16:49:12 -07:00
qctecmdr
b994f0f191 Merge "disp: rotator: remove setting secure domain attribute at probe" 2020-03-29 14:03:20 -07:00
qctecmdr
845000ba36 Merge "disp: msm: sde: setting async cmd wait flag only for DSI" 2020-03-29 10:01:25 -07:00
Yashwanth
f4dc9fb0dc disp: rotator: remove setting secure domain attribute at probe
This change removes setting attribute call at probe since it gets
pre-initialized from smmu.

Change-Id: I8c434e9d88ecf36e0cf033798c52613e14e2faba
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-03-29 09:55:20 -07:00
Veera Sundaram Sankaran
20a7886cc5 disp: msm: sde: avoid vblank notification for cwb
The vsync callback for concurrent writeback is
not necessary. This would conflict with vblank
notification of primary as both belongs to the
same crtc.

Change-Id: Idb67915de086f94feb231d61b6f7e4e068a1ac35
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-03-29 09:55:00 -07:00
Nilaan Gunabalachandran
2e0702c7e6 disp: msm: sde: check input & output buffer for secure context
During validate, kernel should check if input buffer frame
buffer for wb conn is in secure context. If so, the output
buffer must also be secure context, or fail validate before commit.

Change-Id: I38e50f8b2ac71c8532d9d44df08850bf33180c41
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-03-29 09:54:43 -07:00
Nilaan Gunabalachandran
42b9fb5937 disp: msm: sde: check power event before set clk rate
Clock rate can be set from debugfs, and this can attempt to
set clock rate even when display power is not enabled.
Set clock rate should check the last power event first.

Change-Id: Ibf01753a288e5a3003928664c99aa6dbf26350d6
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-03-29 09:54:23 -07:00
Jayaprakash
8274efd919 disp: msm: sde: add plane check in continuous splash case
In dual display continuous splash case, there are certain
scenarios where pipe being used in secondary display at boot up
is allocated by primary crtc. Add check to return failure
in such cases.

Change-Id: I9047b6e7f91e59a9daff5089abb41017c068b449
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-03-29 09:51:49 -07:00
Jayaprakash
4536e7b2a6 disp: msm: sde: add null pointer checks
Add null check for pingpong block used during
the commit phase.

Change-Id: I3ebbcfe9c42ee6d1201a141f553bbb0a0ae97ad6
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-03-29 09:51:30 -07:00
Jayaprakash
2f050dc9fe disp: msm: sde: modify setting of split_display flag
For CTL_ACTIVE targets, slave ctl need not to be reserved
as both the interfaces can be driven with single ctl.
Add a necessary check before enabling the feature.

Change-Id: Id68d7dd4fc1cf9534466fd5bfa50c3f551d06ce4
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-03-29 09:51:04 -07:00
Raviteja Tamatam
c763a14ba0 disp: msm: sde: signal retire fence in wr_ptr timeout
There can be few cases of ESD where CTL_START is cleared but
wr_ptr interrupt does not come. Signaling retire fence in these
cases to avoid freeze and dangling pending_retire_fence_cnt.

Change-Id: I167f69dce5cbe43b4771e5056d8a73bd7587e76e
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-03-29 09:50:55 -07:00
Kalyan Thota
0380f4bd90 msm:disp:rotator: setup irq during first rotator commit
Move the rotator irq registration from probe to first commit, as the
irq is available only after bind on the mdss master device.
The late bind is causing rotator driver to get defered multiple times
and on some occasions rotator probe is not called as its stuck in
the deferred probe list.

Change-Id: Ieff99b31c42d2c9cbc0a4097de7afc9f1b29df77
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
2020-03-29 09:50:47 -07:00
Veera Sundaram Sankaran
bceea4e1fe disp: msm: sde: reset ctl on autorefresh disable failure
Reset MDP ctl path and DSI ctl on autorefresh
disable failure. This will enable the hardware
to recover from the hang.

Change-Id: Ia9acc8573c22e0713179ef4f6ef604caacabfadb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-03-28 23:07:32 -07:00
Yashwanth
363aadd666 disp: msm: sde: update wb properties to optional
This change updates mandatory wb property to
optional as few low tier targets do not have wb
hardware block.

Change-Id: I39e6bf80a527dff95905e0a204401185e9e7bc03
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-03-28 23:06:59 -07:00
Raviteja Tamatam
69c24f5a32 disp: msm: sde: update BW_INDICATION programing sequence
BW_INDICATION indication must be programed before BWI_THRESHOLD.
Otherwise, it will revert to legacy behaviour and rsc wakeup is
delayed by one vsync causing janks. In current code BW_INDICATION
is done after LM/SSPP programming and plane fence wait. Moved the
perf_crtc_update before this and just after ctl prepare configuration
to avoid chances of BW_INDICATION crossing BWI_THRESHOLD time.

Change-Id: Ie976720910c34aaf140f1ce7daef38ba20bc10f5
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-03-28 23:06:51 -07:00
Jayaprakash
975f864784 disp: rotator: update ot limits for kona family
Update rotator ot limits as per QOS recommendation.

Change-Id: I852155902149dc2518b78144658b96f9ee8b4b4d
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-03-28 23:06:21 -07:00
Ravikanth Tuniki
08a2bea751 disp: msm: use platform independent API for cpu number
Use platform independent API for cpu number which
compiles on both 32 and 64 bit machine.

Change-Id: I539de278776623a84067460569a2b99676a2ba4e
Signed-off-by: Ravikanth Tuniki <rtunik@codeaurora.org>
2020-03-28 23:06:14 -07:00
Kalyan Thota
2eb06ab57f disp: msm: sde: fix clk_array index during prepare fail
In clk enable failure case, pickup only enabled clks
and disable them during unwind process.

Change-Id: I004cf71a8ee567d56a1cd7f8f3d2f39ffb58fd61
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
2020-03-28 23:06:05 -07:00
Ping Li
4a5e84f96b msm: sde: SW workaround for REG_BLK_LUT_WRITE HW limitation
LUTDMA HW has a limitation on REG_BLK_LUT_WRITE opcode that requires
the residual REG_BLK_LUT_WRITE data plus the following opcode to exceed
the 4 DWORDs boundary.

This change provides a software workaround for this HW limitation
by inserting 3 NOP commands beofre any other opcode opertation after
REG_BLK_LUT_WRITE opcode.

Change-Id: I72f83cd761eabdfbc290d35da1f1e7a7a54da3e2
Signed-off-by: Ping Li <pingli@codeaurora.org>
2020-03-27 16:14:29 -07:00
Samantha Tran
e86800f362 disp: msm: sde: update uidle wd timer load value
Update the uidle wd timer load value to 12. This change will allow
for 10us wd timer per power team recommendation.

Change-Id: I8a654fc1f70886c75c077e77c926bebf3bad2305
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-03-27 08:55:42 -07:00
qctecmdr
4195464d87 Merge "disp: msm: sde: fix DSC initial line calculation" 2020-03-26 20:32:06 -07:00
qctecmdr
52d46ebea5 Merge "disp: msm: sde: rename the cont splash region" 2020-03-26 06:42:21 -07:00
qctecmdr
9575e1f87e Merge "disp: msm: sde: modify fal10 thresholds for lahaina" 2020-03-25 07:02:57 -07:00
Abhijit Kulkarni
78f4cffab0 disp: msm: sde: fix DSC initial line calculation
Update the DSC initial line calculations to use logical
or operator instead of bitwise operator. Additionally
this change takes care of removing unnecessary brackets.

Change-Id: Ie7fd099e726f0dbed012d5406860300a48d9b2eb
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-03-24 16:11:32 -07:00
qctecmdr
2e5ae6687f Merge "disp: msm: sde: separate horz/vert max downscale checks" 2020-03-24 14:31:39 -07:00
Abhijit Kulkarni
4051341617 disp: msm: sde: rename the cont splash region
This change renames the splash region memory node name
to align the node with the advanced bootloader naming
convention.

Change-Id: Idfd666b5e32e5f22ccb677f68155621adfe87a14
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-03-24 13:11:59 -07:00
qctecmdr
0ff1ec3260 Merge "disp: msm: update rscc mode-2 seq without NRT FETCH halt" 2020-03-24 00:29:27 -07:00
qctecmdr
610df4684a Merge "disp: msm: enable SDE RSC driver compilation" 2020-03-24 00:29:26 -07:00
Steve Cohen
9992efa7a0 disp: msm: sde: separate horz/vert max downscale checks
Separate the horizontal and vertical max downscale checks
as pre-downscale introduced different limits on different
axes. Also cleanup the variable names for max downscale
limit when pre-downscale is not enabled.

Change-Id: If01aac1844d0bd5133502a50dbc38197e11da5d5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-23 23:44:39 -04:00
Steve Cohen
973788d311 disp: msm: sde: reduce complexity in sde_sspp_parse_dt
Reduce the cyclomatic complexity for this function by splitting
the work in to helpers and using the new sde_dt_props method of
device node parsing.

Change-Id: Id4a41225bd78f06ee353a636d17330ba41daf1ff
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-23 23:44:11 -04:00
qctecmdr
c412266ad7 Merge "disp: msm: sde: re-factor probe time initialization" 2020-03-23 15:58:19 -07:00
qctecmdr
756b42939e Merge "disp: msm: sde: avoid going to solver mode for video mode" 2020-03-23 14:40:06 -07:00
qctecmdr
cce870c083 Merge "disp: msm: sde: fix-up reg-bus device node parsing logic for rsc" 2020-03-23 14:40:06 -07:00
qctecmdr
faf67ca3bd Merge "disp: msm: sde: skip vsync wait during rsc state switch" 2020-03-23 14:40:06 -07:00
Abhijit Kulkarni
a752925112 disp: msm: sde: re-factor probe time initialization
This change moves the msm_driver power resource initialization from
bind time to probe time. This keeps the resource vote on until all the
devices are bound. This is required since the regulator and clock
sync_state driver will remove the proxy votes as soon as msm_driver
has probed.

Change-Id: Icb0e59e4ff0290ef0c1bd3914d6fdbf99bf5d9fa
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-03-23 12:07:40 -07:00
qctecmdr
e12e4e1851 Merge "disp: msm: sde: avoid resetting blend stage in every commit" 2020-03-21 14:23:03 -07:00
Steve Cohen
bb31986be7 disp: msm: sde: avoid going to solver mode for video mode
Avoid updating the rsc state to solver mode for video mode panels
on targets with rsc version 3 and up.

Change-Id: I238f130c914c8c845c172746cc2025acd37840d3
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-21 16:46:53 -04:00
Dhaval Patel
24fab78f4f disp: msm: update rscc mode-2 seq without NRT FETCH halt
Now that inline rotation is enabled and offline rotator is no
longer supported, remove offline rotator's AXI2 NRT port from
the RSCC power-collapse sequence.

Change-Id: Ib7e6637a1bcb44b4c1707208ca84c57aa875aa92
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-21 13:24:13 -07:00
Steve Cohen
90cba74599 disp: msm: enable SDE RSC driver compilation
Enable and export configs to support SDE RSC.

Change-Id: Ia0946a65324e1995bfb448e702a03b4dcc99d678
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-21 16:22:27 -04:00
Steve Cohen
7bd07a29ac disp: msm: sde: fix-up reg-bus device node parsing logic for rsc
Power handle's interconnect interface assumes all interconnects
contain a reg bus entry, but RSC does not require one. Change
the logic to only report interconnect failure if the reg bus
node exists in the device node.

Change-Id: Ia4b1cfd1c482a9674b6a29d07483e801ac20a67c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-21 16:22:11 -04:00
Steve Cohen
7a5d2d5d00 disp: msm: sde: skip vsync wait during rsc state switch
When switching from CMD to VIDEO or vice-versa, HW no longer
requires a vsync wait in between since the vsyncs will be
synchronized. So skip the wait for HW which supports this
feature.

Change-Id: Ia5823495bc7bfc7d590098775b0a5f4b4347b5ed
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-21 16:16:32 -04:00
Steve Cohen
80aa9f9c32 disp: msm: sde: add profiling counters support for RSC
Add support for enabling and reading profiling counters via
debugfs. This change also introduces RSC rev 4 (first rev
supporting profiling counters), enabling all relevant rev 3
features as well.

Change-Id: I0326215b069a37c91072965379b0b4843916ee0a
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-03-21 16:16:32 -04:00
qctecmdr
1fc486ad3e Merge "disp: msm: sde: ctl hw flush ops clean up" 2020-03-21 13:08:07 -07:00
qctecmdr
7e6415ab67 Merge "disp: msm: dsi: fix kw issues in DSI" 2020-03-21 11:05:07 -07:00