Currently mixer calculation does not take the number of LMs into
consideration when it is greater than 2. This changes adjusts mixer
count for 4LM use cases based on maximum clock and pipe width.
Change-Id: I05631dee3beadaa0d50548282a539835bcb548c0
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Reserve LM in the sequence of primary-peer and then
primary-peer again until all required LM are reserved.
Searching sequence will not change for single/dual LM
reservation. For single LM reservation it will return
right after the first primary LM is found. For dual LM
reservation it will return after the first primary-peer
pair is found.
The logic can also work for triple/quad or any number
of LM reservetion and make sure that all the reserved
LMs are in pairs except the last one if total LM number
is odd.
Change-Id: Ia28bb64fedeb43430039775051943d751259a3d2
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Signed-off-by: satbir singh <satbsing@codeaurora.org>
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
When a 4LM topology is used each plane attached to a CRTC
is tagged with a L/R layout value and an offset value
depending on where destination X coordinate lands on the display.
The layout information is used to determine SSPP to LM
pair mapping and local coordinate space.
This change also handles source-split and Z-order
validation checks for planes staged on different mixer
pairs.
Change-Id: I1b20223388e65fc36a8b379ad9df23a277fcd1a5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add 4LM topology variants in resource manager and in drm
connector topology name property.
Change-Id: I13e6eaafe60037b48d2c9d356f668b69720cbf48
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Display is entering into mode2 since no new frames are queued,
but auto-refresh requires HW to remain active. Make sure to
cancel the timer for entering idle power collapse whenever
there's a kickoff with auto-refresh feature enabled.
Change-Id: I0ac74e514c9893c31506edc3f2d7e069ab9a3ef8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change adds secure-ui blendstage support for
lahaina target.
Change-Id: If6e0f9df469e39f53329b264416ef9214ec01be9
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change updates resource topology mapping tables and includes
logic to compare compression types for dsc vs vdc.
Change-Id: I1735edeb07aec8ed0065f84ac0824c58158412f3
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
With posted start enabled SW no longer waits for ppdone events
unless more than one frame is in queue. HW recovery logic relied
on these waits to know when we recover from a timeout. This
change moves the HW recovery SUCCESS event signalling outside of
the wait to ensure this event is sent to user-space regardless
of the status of posted start.
Change-Id: I8896e8126284b415513499723ccf0155ee8bc6a7
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Setup blendstages is done per LM but FETCH_PIPE_ACTIVE is per CTL.
Overloading mixer blendstage setup with fetch pipe logic can lead
to HW programming errors. Refactor the logic for setting
FETCH_PIPE_ACTIVE by adding a new op that allows caller to provide
a bitmask of all pipes required to be active on this CTL. This new
logic includes support for:
- 4LM use-cases, staging pipes for all LMs within a CRTC
- Demura fetch-pipe without need for tracking via active_cfg (removed)
Also, lower the cyclomatic complexity in setup_blendstages by moving
the logic for obtaining the mixer config settings in to a helper
function.
Change-Id: I2907b359ffad5734be5b06f44919b5ddb1ef3f7c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Currently, compression info passed to resource manager is not
valid in atomic check phase. Also in current design allocation
of msm mode info object is from stack which is huge and causing
stack overflow in continuous splash use case. This change fixes
these issues by moving mode info object to heap allocation.
Change-Id: Ifaf39b3ae59c942da5c00b82c73cb97cdaf500d3
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Make msm_drm into single module and all child driver
registers and unregisters are handled from parent's
register and unregister respectively.
Change-Id: I017513d1de3b6b25dd5543d7fa7741c0bac1740d
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
sync_state driver disables any resources that
don't have any votes after driver probe is completed.
Move MDSS resource votes to probe so that any resources
that are needed for continuous splash are intact until
the bind of all the components is complete.
Change-Id: I0056bf1ec56bcd6a1b620a81143d4b49d7ea2921
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Currently, the value for predownscale_x_0 is being set based
on source height and destination height. This value should only
be set if userspace has not set a value for it already or if
default scale is enabled through debugfs.
Change-Id: Icf13ac33ae4a1a40bff90cd639428e9a11f96241
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.
Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
A new position control register field has been added to the
DSPP PCC on Lahaina. This field controls whether PCC is invoked
before or after GAMUT mapping.
Introduce new PCC control logic to set the PCC position based on
the new PCC_BEFORE flag. Older versions of the PCC control function
now clear all flags to ensure backwards compatibility.
Change-Id: I0a33604111b755e0a0ccf1864a57b17cc9071e3f
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
This change addresses out of range and null checks in
sde and dp driver.
Change-Id: I142196d7394f0bf0abab1bfa89abfd784a5521c8
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Lower the cyclomatic complexity for this function by splitting
the work into helpers.
Change-Id: I9e32d4ff13d31360a2baa77e013751ee8f0773fb
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Use the new helper for parsing TOP device node properties and
reduce the code complexity by re-arranging the ordering of some
conditional branching which simplifies the logic.
Change-Id: I222bff6d1311f988c57f5f43e677dac4167fb7b9
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This reverts commit a4c2827a47.
The change is not needed on 5.4 since BW limits have moved to
user-space per-target based XML file, and there are already other
properties for specifying the various linewidth parameters.
Change-Id: I87d81047678869bba6f8ec98104dec17c7a9ace2
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Lower the cyclomatic complexity for this function by splitting the
work into helper functions.
Change-Id: I07d399e455ca2f73a14875b45c30f123c39fa501
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add scaling linewidth variable and logic changes to get
valid max linewidth values for inline rotation and scaling.
Modify linewidth check to compare with scaler source width.
Change-Id: I7c63175e568ecb524f9cdf8ada1d7c6fdc999236
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
Update the VDC-m hardware version in the display driver as per
the latest programming guidelines.
Change-Id: I0073cb7b713599de43f2a675202390df3b4a1d58
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This change updates plane's dirty flag with QoS
value to ensure QoS gets reprogrammed with new FPS
settings. This is required as QoS values will change
with FPS.
Change-Id: I377b99da2a640d375bd48477f149197b332e7f7b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Updating qos remap updates requires reading registers to update values,
this adds additional CPU processing when in reality this update
is only needed once.
Bug: 142504774
Change-Id: Iec8d4dfd858b0602db7d2275b6b716dbcffe0d2f
(cherry picked from commit dbd1cfbc21db4b9bd4f1a4fc234cedc314fa1265)
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Perf tuning mode can be updated through debugfs and this should
be used to reflect the core clock rate.
Change-Id: I313d079f0b8013f43f4b293c6400f34eaf56b6d2
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
