1. Check Tx halt during umac reset and avoid halt if set already.
2. Perform SRNG disable only in case of umac reset
Change-Id: Id364a6460a64e83002b5c96e08031ad2a0bc8fd7
CRs-Fixed: 3459427
Added change,
1. Define new DBR module DBR_MODULE_CBF to handle TxBF
standalone sounding CV data and corresponding ring
initialization.
2. API to extract new meta data TLV added for CV data.
3. API to handle standalone sounding complete.
Change-Id: Id28c5561bb8b3bf08de7ddd9aa2365e2ae99f1c2
CRs-Fixed: 3415627
The kernel-doc script identified multiple documentation issues in the
target_if folder. Some sub-folders which had a multitude of issues
were patched individually. Now fix the remaining issues.
Change-Id: Ia46f54eaec90762e61e590344760f3c3364088de
CRs-Fixed: 3417471
Mark srng_initialized to true when the DBR ring memory
allocation is completed.
Change-Id: Iacb4d5ac884bb575ad4b98201280527521906e63
CRs-Fixed: 3355169
Set default value for 'offset' to fix the compile issue
'variables may be used uninitialized'.
Change-Id: Ib8db38140463fb543b1d98f19743b3a3a7fded4c
CRs-Fixed: 3345183
In the current implementation, the Direct DMA completion event is getting
processed in the tasklet context. When the Direct DMA events land on the
same processor core as the one used by the WLAN data path events, the
Direct DMA events can pre-empt the data path events as the datapath
events usually run in NAPI context. This could impact the data path
throughput when there is a high volume of frequent Direct DMA events. To
fix this, Direct DMA events can be run in work queue context based on
user configuration. Add support for the same.
Change-Id: I1a89b185c6765addc7ee725e9324025f0318d9ed
CRs-Fixed: 3276157
Hif and tgt if layer changes to handle Umac post reset
and post reset complete events from firmware.
Change-Id: I08bbd90741708fe76b2db0371ccfda7bfe7b0b2d
CRs-Fixed: 3267222
When we try to unregister a module that was not registered earlier, we will
try to unmap the buffers that were not allocated. As a result, we end up
with invalid memory access. Fix this issue by checking if the module was
registered before unregistering it.
Change-Id: I97c4ee7a6690c6cba2a7d1a919a39fcb12ebb692
CRs-Fixed: 3179498
Read out of bound due to invalid cookie and cause device broken. This
change checks cookie before using it as index of DBR buffer pool.
Change-Id: I1abc7d771cc62a7dd2dfe98784bf8ef2710f26ca
CRs-Fixed: 3144133
Memory node pointer to unaligned vaddr, and it free the vaddr firstly
and then remove the memory node, which cause invalid memory access.
This change remove memory node firstly, and then free the unaligned
vaddr.
Change-Id: I3b81c1eb4df7c786a3deec456294107ee3b8f226
CRs-Fixed: 3118545
To avoid memory allocation failure during idle restart,
hold the memories with large size for DBR ring during
the entire lifetime of PSOC.
Change-Id: Idfe5f0e895cc088509b5a62ae07191aed32864f2
CRs-Fixed: 3099522
Currently in function wmi_extract_dbr_buf_release_entry,
num_buf_release_entry & num_meta_data_entry are copied
to direct_buf_rx_rsp structure without any validation which
may cause out of bound issue if num_buf_release_entry or
num_meta_data_entries provided in fixed param becomes greater
than actual number of entries.
Fix is to validate num_entries and num_meta_data before populating
param->num_buf_release_entry and param->num_meta_data_entry.
Change-Id: I18050fd4f90f8815d7eceb5f715fdbaa09130d3a
CRs-Fixed: 3000875
It takes long time to init DBR, so add more log to trace the time when
exit target_if_dbr_fill_ring.
Change-Id: I9ec76c92db209a44c277b0f9e1840e6dd0132559
CRs-Fixed: 3002654
When host failed to find out vaddr by paddr from FW, output more
information for debug further.
Change-Id: I65c4965c12c2ffa3fe2a26a82df01d1b91501c73
CRs-Fixed: 2925194
Fix compilation errors when DIRECT_BUF_RX_ENABLE compile-time flag is
disabled.
Change-Id: I2bbce6eb8838ecab02b6462c1c0ee28877accdb4
CRs-Fixed: 2883310
DBR srng details are not sent properly to F.W via WMI_DMA_CFG_REQ
msg, this leads to F.W accessing undefined address.
Fix this by passing DBR srng details properly.
Change-Id: I15b393ad809dc0757e3637558f0bddd05530149d
CRs-Fixed: 2861621
Use the hal_srng APIs that handle byte-order conversion of ring pointers
for big-endian platforms.
Change-Id: I2664636d5d2a1abfd7b643ea4c4d63d328a9880f
CRs-Fixed: 2845047
Direct Buf Rx has a source ring to communicate with the target.
The target updates its tail pointer in little-endian format and this update
doesn't go through any byte-order conversion at the target. On a big-endian
Host platform, this tail pointer will be read in reverse order of bytes.
To fix this, convert the tail pointer to the Host order before using it.
Change-Id: Ibcaf3d7507910ea81eeb895772241ab9861ee45a
CRs-Fixed: 2843259
If module is not registered for dbr in any platform it
results into Null pointer dereference.
Added Sanity check to avoid Null pointer dereference for
cfg80211tool wifi0 g_dbr_ring_status.
Change-Id: I9e68dfc9d58d70693184f53913cd7f2324d788c1
WLAN chip components are little-endian based. When such a chip is attached
to a big-endian Host platform, there will be a mismatch in the order of
bytes for the data that is transferred between the Host and target.
Direct DMA framework writes 64-bit values to its DMA ring entries.
These DMA ring entries are present in the shared memory between the Host
and the FW and the data transfer doesn't go through any copy engine.
So, to avoid invalid reads at the FW side on a big-endian platform, write
ring entries in little-endian format so that the FW reads them correctly.
Change-Id: I9c9189f914fdda335723c25fc05484487985447c
CRs-Fixed: 2828746
wmi_unified_register_event return QDF_STATUS
Handle same return type in caller function
CRs-Fixed: 2764185
Change-Id: If77efc6a5b451bf2cf4acb59d5a2126ce486f02f
In direct buf rx, if physical address is not intact or
is corrupt, the dbr lookup for vaddr will fail and result
in vaddr being NULL. There is no validation for this vaddr
in the caller and hence results in NULL access in the
callstack.
Add debug log and return error status when dbr
vaddr lookup fails, which indicates that there is
corruption in paddr received and avoid NULL access.
Change-Id: I76ee300ce3e686765dd5c4ee73fa71d1735c163a
CRs-Fixed: 2748529
For adrastea targets, enhanced CFR is not supported. When only
CONFIG_WLAN_CFR_ENABLE is set, some compilation errors are
observed as CONFIG_WLAN_ENH_CFR_ENABLE is not set true.
Fix these compilation errors when only CONFIG_WLAN_CFR_ENABLE
is set for targets which do not support enhanced CFR.
Change-Id: I96a769d8f10144033e48e123bb68d48a54cdf8ab
CRs-Fixed: 2706904
Clear console log boot up error prints by removing unnecessary
prints, modifying prints to appropriate info or debug and
by fixing the errors
Change-Id: Ica3f126280399eef59b894236849e2079a62565f
CRs-Fixed: 2597026
In dynamic HW mode switch feature, DBR pdev object of primary device
needs to be re-assigned after HW mode change. Store the DBR objects
in psoc for all devs and then use the mapped pdev to retrieve the
corresponding DBR object.
Change-Id: Ie56bdf9d430a5a3ca7e4e9a872018257d032c908
CRs-Fixed: 2589447
For each DBR ring, add debugfs entry to dump at real-time the ring
parameters like head, tail index, the timestamps at which a buffer is
received and replenished. Issues that are specific to tail index
movement from the target can be identified with this debugfs entry.
CRs-Fixed: 2466514
Change-Id: Iafbc61726264464212cb783a1cce46e16b8a48ff
Improper/incomplete DMA by the target affects the functionality of modules
that are using DBR framework. Add debug infrastructure to poison DBR
buffers with a given poison value before handing buffers over to
the target. Buffer owner modules can explicitly check for the poison
value in order to detect the improper DMA.
All modules that use DBR framework can use this debug infrastructure.
Change-Id: Ib3923c13202990e0f1198645b680c44a20736167
CRs-Fixed: 2466518
Add debug infrastructure to track the movement of head and tail pointers
of the DBR ring along with the time at which each buffer is received and
replenished. All modules that use DBR framework can use this
infrastructure. Issues that are specific to tail index movement from
the target can be identified with this debug infrastructure.
CRs-Fixed: 2439460
Change-Id: I6b486a73cf6a3174dfa297f8fb370fd298b46b67
In function target_if_direct_buf_rx_register_events(), the
API direct_buf_rx_info() is used to record log, but the
format is wrong. Fix the log format.
Change-Id: I81bc128e110570d96ca95dfbe773121272eb2588
CRs-Fixed: 2547235
Exceeded 500 logs per second in target_if_get_dbr_data().
Move the info level logs to debug level in direct buf rx as
heavy logging is triggering an assert.
Change-Id: I725bd50f83dc65f4e5378c4a882829a0ad1b7893
CRs-Fixed: 2534298
There is compilation issue about dbr_get_pdev_and_srng_id on hasting
platform, fix it in this change.
Change-Id: Icd5612c31341e6a5f71c65f1ec10533c164798c3
CRs-Fixed: 2530729
It required to support multiple srng per module in direct buffer rx
component.So extend the array "dbr_mod_param" in dbr pdev object and
let it to support two more srngs per module.
Change-Id: Ia2c649dacc3787cdc13b06f0b22c1c175fb451cc
CRs-Fixed: 2523365
EXT2 event carries the dma_ring_caps info.Necessary
support to process the same is being provided.
Change-Id: Id8ef1840470b272db00fa5e8f98d1fe9dc273a7e
1. Alloc size should be passed as input and output parameter since we need
to pass the exact alloc_size while freeing the memory.
2. use qdf_align() to calculate the aligned physical address.
3. In DBR component, pass correct arguments to qdf_aligned_malloc() to fix
the compilation errors.
Alloc size should be passed as input and output parameter since we need
to pass the exact alloc_size while freeing the DMA memory.
Change-Id: I83051b8aa54bbf3bb663902d8f17f2c3c55e57bf
CRs-Fixed: 2462441
Frequent log in direct buffer rx component will cause platform assert,
so lower the log level. Get wmi handler by psoc since since pdev
creation is in progress and it doesn't have related information yet.
Change-Id: Iaaf5a43642f9b6dfaf07ddd3f158abd346903a87
CRs-Fixed: 2495249
The function target_if_direct_buf_rx_rsp_event_handler() handles
the WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID event from target.
This function calls extract_dbr_buf_release_fixed_tlv() to copy
the module id, pdev id number of buffer release entry and number
of meta data release entries. The value of module id is used to
index the array dbr_mod_param to get the value of mod_param.
So if the module id value greater than dbr_pdev_obj->num_modules
could result in possible OOB.
Validate mod_id received in the fixed param of the event
WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID against
dbr_pdev_obj->num_modules.
Change-Id: I1c2c0a2a9c98d8b787496aba7a7c4f8fd781de16
CRs-Fixed: 2428798
CFR requires to configure the number of DBRs that can be packed
in a single DBR event. Currently, this is fixed value.
Make this configurable at the time of registration.
CRs-Fixed: 2415489
Change-Id: Ifcd606641f986a5345f8ccb361c3f45db07fdc37
Per the Linux Kernel coding style, as enforced by the kernel
checkpatch script, pointers should not be explicitly compared to
NULL. Therefore within target_if replace any such comparisons with
logical operations performed on the pointer itself.
Change-Id: I436bb3ec12d331df2260507b6a9afbab84a8a54f
CRs-Fixed: 2418256
CFR needs to correlate data received from direct dma ring and WMI event
for tx completion. These two events can come in any order. To facilitate
correlation CFR module has to hold on to the buffer until both events
are received and then replenish buffer back to direct dma ring. To
facilitate this requirement direct rx buf module is modified to change
callback return to bool to indicate whether buffer can be replenished
immediatley or not. Also add API to indiciate buffer release/replenish
later.
Change-Id: I848c0e7cf0118156fff7cf37ac9027cdf8e2e416
CRs-Fixed: 2403395
