Due to timing protocol constraints between LCR and PD resources and
sof retiminig disabled, PPP resource should be enabled after RDI0
whenever LCR is enabled.
This commit changes the order during the CSID start to enable PPP
after RDI0.
CRs-Fixed: 3222469
Change-Id: I11371ea4602ff4bd72e690453103bd6a18ba836a
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Other than stat WMs, all other clients can run in secure mode.
CRs-Fixed: 3208187
Change-Id: I17956a4815a56eacbaa14e08db98fde681a6d9d6
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Some unhandled buf dones belong to next req, we need
to add them to deferred buf done list and process it
in future.
CRs-Fixed: 3197114
Change-Id: I5489cb6faacf2b6c9018b3b660a1df2ee6ac9564
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Add error handling and information logging for drv error and
info irqs for drv. Also, add debugfs for vote up and down irqs.
Add ddr and mnoc register value logging in vote up and down
irq bottom half.
CRs-Fixed: 3065551
Change-Id: I5332658924762a528625e628c3fa5d5dec07da62
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Add support for bw update version 3. Add provision to
maintain cpas per path bw info internally in drivers.
CRs-Fixed: 3065551
Change-Id: I65e97c6e41f933818f1211bbc27651842e93c028
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Top debug cfg register is getting reset while starting RDI resources.
This commit adds the register data to RDI resources and reads back
the register before updating the register.
CRs-Fixed: 3207575
Change-Id: I4e149fc81cbfc60adb6d3bb842a1057e8202903f
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Removes IFE HW manager reference from ISP context and moves some
LDAR dump functionality for stream info to IFE HW manager.
CRs-Fixed: 3210247
Change-Id: I311c7cd8d8684a68ba0bfbe279ef9ba55cfbbe82
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
Use spin_lock_bh utility to avoid the preemtpion of recovery thread
in ISP context. This can come in rare conditions when IRQ is received
on same CPU which is handling the thread.
Such cases will result in deadlock conditions.
CRs-Fixed: 3208733
Change-Id: I25fde15b484fd72fa779aed393ef94d4fbb183b6
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
In some cases while using scratch buffer UBWC registers are not
configured even after receiving the update blob from Userland.
This results in constraint errors at bus side.
This commit configures the UBWC registers at stream on if the
blob was received for the ports which are UBWC enabled.
Change-Id: Icf9a66808432052c84f52bbf470880fde082cee3
CRs-Fixed: 3108015
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Only for FE use-cases, allow SFE pix ports to be acquired when the
input resource is RDI0-2.
CRs-Fixed: 3207073
Change-Id: Ic190d6ba1fb8cb63db5fef63bda05a7cac9c0c51
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
If csid doesn't give unpacked msb out, packing needs
to be done at csid side for plain128 in order to
enable RPP subpath.
CRs-Fixed: 3198208
Change-Id: I9b228382804a9eb41d45b6d7bf6433bcfd4b4e40
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Currently, the IRQ reg set is not having an empty RDI4 entry,
causing an out of bounds access during probe. Add empty
entry to reg set in headers to enable correct irq register
info to be retrieved in driver.
CRs-Fixed: 3198089
Change-Id: If963ed4295c902651d3d62158cc6c0546cd8e470
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
While printing the resource name in path irq handler, RDI resource
is pointing to TOP Irq index. This prints the wrong IRQ tag.
This commit fixed the issue by assinging correct IRQ index to RDI
resource.
CRs-Fixed: 3197257
Change-Id: I25db915ff427838ae429a86a698424314c3264f6
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
This commit adds debugfs mask(Bit 30) to print SFE Cache
information. This helps to check the SCID settings on SFE
bus read and write master.
Change-Id: I75355bbc167763a09442114f43b23dd1b82e0960
CRs-Fixed: 3197257
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
This change adds supoort for variable fps feature, this
feature needs to stream off the sensor at EOF. So, this
change sends an EOF event to sensor to do the streamimg
off. Since sensor only outputs one frame every round, so
we need to apply the IFE packet to HW immediately, then
the every frame will be valid frame.
CRs-Fixed: 3178221
Change-Id: Ifc57987aac11c9655edd979734e5568c19262571
Signed-off-by: Wang Kan <quic_wkan@quicinc.com>
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
When a page fault is encountered by IFE/SFE, as a side affect
a bus overflow is also seen, which results in CSID overflow.
In this change, CSID driver registers a callback with CPAS,
and on camnoc slave error irq notification CSID will
skip processing the overflow. This will avoid resetting
the SFE/IFE pipeline and all necessary logs for PF debug
will be available. With this change kernel will post only
one error event to userland for PF as opposed to two
for PF and bus overflow.
CRs-Fixed: 3175797
Change-Id: I9789314452075e2b943cf08b19002a645eafb16b
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Check IRQ status on hang detection; if the inline IRQ
is set then the cdm has triggered IRQ but there is a
workqueue scheduling delay which is causing the cdm
config timeout. To prevent the timeout due to
scheduling check the work record and irq status.
Change-Id: Id3d224d6393b69638b27c82ebf0933a6a3dce231
CRs-Fixed: 3163828
Signed-off-by: Shardul Bankar <quic_sharbank@quicinc.com>
Fix syntactical errors that resulted in failed compilation
for TFE and OPE.
CRs-Fixed: 3179075
Change-Id: Iec4dc104160651fb46b18be17a556356dce3b3c0
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Add support for new bus rd ccif violation on SFE v880. Add bus rd
constraint violation description and infrastructure to print the
description. Update constraint violations desc for bus wr on SFE
v880 header. Move the irq err mask to the headers, this way the
mask will be dependent on the error bits for a given target. Add
cons_chk_en_avail to indicate if constraint checker needs to be
activated. Cons checker needs to be enabled on Lanai to get cons
violation irq. Add support to skip false alert of constraint
violation of bus write on image address unalign and image width
unalign error bits.
Move macros for bus rd RUP and BUF done to bus_rd.h file.
CRs-Fixed: 3186604
Change-Id: Ifa48ca8de7666a044e9c9b3641de0915b6f16587
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
The group1 vcdt and decode format value should be got from multi
vcdt cfg0 register address.
CRs-Fixed: 3183661
Change-Id: I155ab823e3d90513c49614802b3f9fabe8fda73c
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
For Kalama, Low level cache controller can be used
for Long exposures as well. To support this, cache
can be shared among SFEs and a single SFE needs to
toggle between the cache IDs to keep the caches
clean.
This commit adds changes to support above requirements.
Change-Id: I9dadf4655db946254be62116b45e81abdb979b3f
CRs-Fixed: 3153295
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
In some hardware, it is possible that global clear command on an
independent controller can clear relevant status bits of a dependent
controller due to the clear register being dirty. This commit
introduces lazy clear register sanitization.
In case of a dirty clear register in a dependent controller, the IRQ
controller waits till the next interrupt and checks if that clear
register is going to get updated. If not, that clear register is
sanitized (set to zero).
CRs-Fixed: 3152588
Change-Id: Ie94252fb378676481410759c8bc87088d27024dd
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
If an IRQ status register has not caused the interrupt to be triggered,
we can skip writing to the corresponding clear register as long as no
previous writes have been made to it that will cause bits of interest to
be cleared (i.e. clear register is dirty). For this, we maintain a dirty
flag for each clear register.
The dirty flag will never cause false negatives (i.e. valid writes to be
missed) since hardware cannot set any bits in the clear register to 1
and will only clear the entire register upon resetting the hardware.
CRs-Fixed: 3152588
Change-Id: I4f97bae0e3cd983ca66d5b89ffb2c16da7c25200
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Due to delays, frame count may not be increamented. Sending such
notifications increase the number of invalid notifications in User
space. If the frame count is same, skip sending the timestamp
to userspace. This provides more time to recover from the delays.
CRs-Fixed: 3164368
Change-Id: I09a96bbafb80233e962304d9a82fde45233a5f89
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
In Non-SFE use cases, camif interrupts from CSID are sufficient to
run the state machine. In SFE cases, interrupts from VFE can be
used to drive the state machine.
This commit adds changes to subscribe the IRQs based on the
use case.
Change-Id: I75c2bc4f6e0754ef1e80a2d4f291b18f16900475
CRs-Fixed: 3153295
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Add register header file for SFE 880 target. Modify
data structures, Macros in SFE top and SFE bus write/read files
accordingly. Update compatible dt match to include sfe 880.
CRs-Fixed: 3175256
Change-Id: I4205578ce473b69f01b3ce79b4f29547d957bb44
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Add output port - HDR_STATS for SFE880 and update all mappings
associated with the port.
CRs-Fixed: 3175256
Change-Id: I1a856f3c705d651a486e0aba5a77ca73f0deb5a5
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
In case of bubble recovery stalling try internal recovery,
halt, reset and resume IFE pipeline. If internal recovery
succeeds skip notifying userland for pipeline recovery.
If the same slot [same request] is stalled again, it will
flag for userspace recovery.
CRs-Fixed: 3098892
Change-Id: I6fff844fecd653897451ab920ddf6c4d8ca2f49e
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Remove max sfe out resource macro from uapi. Remove all usages
of the macro in ife hw mgr and sfe bus write files. Instead, use
max_out_res from sfe header files and Ife hw mgr calls to queries
max sfe out res from sfe bus wr.
CRs-Fixed: 3176997
Change-Id: Ie3fc36f3003305eeebcc60ec9539ff2c6630e337
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
This commit adds new hardware header files for VFE 880 and VFE Lite 880.
It also adds support for loading the hardware structs defined in these
files during probe time.
CRs-Fixed: 3168484
Change-Id: I617cbc0fa6f1fa45b3ff4ba503a65d6eb2e265c0
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Add output port for STATS_ALSC for VFE880 and update all mappings
associated with the port.
CRs-Fixed: 3168484
Change-Id: I0a674e7d2d6fe5fa5a51ff31e22f066fa222e5b7
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
In CSID v2, the top status register indicates which other status
registers have values of interest. Adding a separate IRQ controller for
each such register, and registering them as dependents of the top irq
controller allows optimization of register reads and writes.
CRs-Fixed: 3152588
Change-Id: I930f9b9c58da0f45fffabb2929062d721bb9bbda
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Tweak SOF timestamp recovery logic to handle sending timestamp for
first frame. This is needed when due priority inversion, ISP context
notifies timestamp before SOF.
CRs-Fixed: 3085335
Change-Id: I9baea8d906bb8f820c7aeb2d7d4ae1c1c6f348b2
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
For SFE use-cases, update the hw_idx and paths acquired
for userspace to consume. Currently even in SFE use-cases,
only IFE info is returned which may not be right always.
CRs-Fixed: 3175210
Change-Id: Ice0816993a208965032a71a924cd53f7ebc02e89
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Currently the assumption is the order of the comp groups
and buf done status bits are the same for SFE write clients.
This may not be true for different targets. Add per group
shift value in header, removes dependency on comp group type
and buf done mask.
CRs-Fixed: 3175210
Change-Id: I802fb2676c20847148c02c9a46766115511a2450
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
The index of sfe out res in bus_priv is based on
the sfe out type, rather than the out index, So
we need to get the sfe out type by the out index
first, then get the sfe out res by sfe out type.
CRs-Fixed: 3165425
Change-Id: Ic35f6b5b23a0997c2f05f8950d0a82f488185d39
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Add CDM Debug register dump when the Bubble is detected due
to cdm callback not received.
CRs-Fixed: 3163463
Change-Id: I028ac9216704d14cc51648b0a5a78b0a2a366f12
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
This change does hw recovery and reapply all alive requests
for bus overflow issues.
When we face bus overflow KMD fatal errors, instead of
sending error to UMD, we will try internal recovery and
send a warn message to UMD once internal recovery happens,
if we fail to do recovery, then sending error to UMD.
CRs-Fixed: 3098892
Change-Id: Idee3679ff06227f985e106470bc1f5a14c9cb404
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Shared memory is initialized by CRM and used by
other drivers; with CRM not active other drivers
would fail to access the shared memory if
memory manager is deinit. Reader Writer locks can
prevent the open/close/ioctl calls from other drivers
if CRM open/close is already being processed.
Issue observed with the below sequence if drivers
are opened from UMD directly without this change.
CRM Open successful,ICP open successful,
CRM close in progress, ICP open successful,
mem mgr deinit and CRM close successful,
ICP tries to access HFI memory and result in crash.
This change helps to serialze the calls and prevents
issue.
CRs-Fixed: 3019488
Change-Id: I84d50918713686a067c0e3deb64c9c6ae9edfcb5
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
When validating input/output formats in CSID, if there
is an error, it is being dropped and returned as success.
Handle this to ensure error is propagated from CSID to
HW manager.
CRs-Fixed: 3163468
Change-Id: Ic822feb4ca7418a68ed10ab9a17f72c2408d4759
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
In case of multi vc-dt fetch engine use-cases, validate
the input format for each VC, they are expected to be the same.
Different input formats for each VC for SFE FE use-cases, is
not supported.
CRs-Fixed: 3163468
Change-Id: I73aab062bc316f01af4fdbf3eb0155c7e1b2719e
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
In case of HFR, align the frame increment to 256 to support
36 bit addresssing scheme on Kailua.
CRs-Fixed: 3150471
Change-Id: Ib71132a73a0d07a012ca960718be69a8456a07b8
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Upon Page Fault, smmu driver invokes faulted client's callback
which looks for faulted buffer and context. The client driver
can be ISP, ICP, JPEG, IFE CDM and CPAS CDM. The driver then
fills PF msg struct, logs related info, and notify PF msg to
userspace. Userspace is expected to abort and calls to shut
down kernel drivers. When Titan powers on next session, CAMSS
undergoes async reset.
This change also ensures the page fault related changes added
to TFE, OPE, CRE do not break the drivers compilation.
CRs-Fixed: 3156671
Change-Id: Icd6c8c9a38cac206fe8260d374d03964fb280879
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
For IFE only use-cases bump up the max number of configs
from 25 to 30, to support dual IFE requirements on Kailua.
CRs-Fixed: 3163468
Change-Id: Iffa5735fba3f8271b47ad368437b9174244ef889
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Due to the scheduling delay, We are seeing back to back
two top half for buff done for 2 different requests
but we were expecting the bottom half after 1st top half.
We update the last consumed address in the bottom half so
we have 2nd req buffer address in last consumed reg as
we received 2nd req top half before 1st req bottom half.
We increment num_ack variable of 2nd request in case
of 1st req buff-done as it had 2nd buffer address in
last consumed address.
Ack is going beyond during the 2nd req buff-done.
This check will prevent duplicate acknowledgment increment.
CRs-Fixed: 3165255
Change-Id: I9ea3bca2a782bae6017565f30162484adf2fc789
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
For RDI only context EOF is not notified; it should be
notified, for the corner case if the flash is
configured to apply at EOF then it will block apply for
ISP on SOF as well until the EOF is notified, this
change adds EOF notification.
CRs-Fixed: 3091241
Change-Id: If6d974d092d640d9def89bbcf7a88fba0d85579b
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
