提交線圖

1893 次程式碼提交

作者 SHA1 備註 日期
Nilaan Gunabalachandran
c6bdb5db3a disp: msm: sde: avoid concurrency while calculating max mode width
With DP plug-ins, it is possible for the connector fill modes API
to be called to update available modes on the connector and at the
same time have the commit thread calculate the max mode width
on the available modes. As a result, it is possible to access
pruned modes from the modelist.

This change moves the calculation into the fill modes call-flow,
so that the max mode width is determined once, and stored to be
used during virt enable.

Change-Id: I6c332c57e6e98ed98444a303add97d163a2031bf
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2023-04-25 12:39:05 -04:00
Nilaan Gunabalachandran
825dd16313 disp: msm: sde: correct llcc_slice_getd/putd usage
The llcc_slice_getd/putd APIs were previously used to get/put the
slice descriptor reference, for every time the driver needed the
descriptor. However, the APIs should be used to get the reference
once, and only put after completing usage of the slice
(ie. if the slice is still active, the descriptor cannot be putd).

This change corrects the usage of the llcc_slice_getd/putd APIs by
storing the descriptor after initialization.

Change-Id: I33e6448290ff7a4d8bfa72e1e6bc8ca133283e12
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2023-04-24 16:46:38 -04:00
Veera Sundaram Sankaran
336212e10a Revert "disp: msm: sde: enable EPT_FPS feature for cmd mode in pineapple target"
This reverts commit ae24e846e1.
Enable the feature only when user-mode support is added. With this
feature enabled in driver, it expects EPT_FPS to be set for qsync
enabled cmd-mode panels and will not honor EPT(expected present time).
With the EPT_FPS feature disabled, all panels cmd/video with/without
qsync can use EPT.

Change-Id: Ib8b1625bb1927ece3ec435e4b9a724da0555e518
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2023-04-19 22:08:50 -07:00
qctecmdr
a5b7dc6eb9 Merge "disp: msm: sde: reset dsc 4hs merge enable" 2023-04-19 14:34:14 -07:00
qctecmdr
a5dd993196 Merge "disp: msm: sde: remove EPT & QSYNC dependency" 2023-04-17 17:42:31 -07:00
qctecmdr
a0c954eea2 Merge "disp: msm: sde: add debugfs node to get current uidle status" 2023-04-14 13:12:08 -07:00
qctecmdr
2ccae39402 Merge "disp: msm: sde: program both rc config and ram through lut dma" 2023-04-14 13:12:08 -07:00
qctecmdr
1d9d243a82 Merge "disp: msm: sde: flush pp event work queue before vm release" 2023-04-14 13:12:08 -07:00
Nilaan Gunabalachandran
6962242207 disp: msm: sde: reset dsc 4hs merge enable
If DSC 4hs merge is enabled and disabled on n+1 commit, possible
due to resolution switch, driver does not currently clear the
previous programming.

This change cleares dsc 4hs merge enable if it is not enabled.

Change-Id: I4024073362257b7efabcff22603bcb28a0bc4c5a
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-04-14 12:02:19 -07:00
Lei Chen
8ed479026a disp: msm: sde: add debugfs node to get current uidle status
Add a read only debugfs node to get current uidle status.
Usage:
      cat /sys/kernel/debug/dri/0/debug/core_perf/uidle_status
       N: indicate uidle is disabled.
       Y: indicate uidle is enabled.

Change-Id: I7f28b406588c19decc4efc9012f5bac63925618a
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
2023-04-14 09:49:37 -07:00
Saurabh Yadav
c27d7c56ce disp: msm: sde: program both rc config and ram through lut dma
Currently, only rc ram is programmed through lut dma and
rc config is programmed through ahb.
This change programs both rc config and rc ram through lut dma.

Change-Id: I50a6e87dfbadb9c4a93cebdaa1e813f5be9ba5f5
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
2023-04-14 09:48:43 -07:00
qctecmdr
90ba54e04b Merge "disp: msm: sde: defer S2-only and tvm dma_buf_map_attachment" 2023-04-14 04:33:12 -07:00
qctecmdr
dc5a69d265 Merge "disp: msm: sde: check for hardware ownership before histogram read" 2023-04-13 23:29:59 -07:00
Veera Sundaram Sankaran
62b643a4d6 disp: msm: sde: remove EPT & QSYNC dependency
Expose Expected Present Time property to usermode immaterial of the
panel qsync support. EPT can be used to delay the frame with/without
qsync support.

Change-Id: If4e628dda64181995ba9ba0b008d15d3d9a9cfd4
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2023-04-12 18:28:51 -07:00
qctecmdr
302a160bae Merge "disp: msm: add feature-enabled check for output hw-fence sw-override" 2023-04-10 15:38:33 -07:00
Veera Sundaram Sankaran
d867d748ab disp: msm: sde: defer S2-only and tvm dma_buf_map_attachment
For usecase with S2-only or TVM buffers, the mapping needs to be done
after the SCM call. This is required to ensure the mapping is done to
the correct SID. Previously with S2-only usecase, the map was returning
the PA which would remain the same, so there were no issues even though
the map sequence was incorrect. But this sequence will cause issues with
CSF-2.5 as it uses 2-stage with TVM, and requires the mapping to be done
after the scm-call. Fix the sequence for legacy secure-camera preview,
legacy secure-display and CSF 2.5 solution.

Change-Id: Id663d30fdbf8725f43f61e67d2d7ce72aa9f9506
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2023-04-10 10:04:26 -07:00
Saurabh Yadav
ac9d215e9e disp: msm: sde: flush pp event work queue before vm release
In some vm transitions, pp work might get executed on event thread
after handoff is completed on commit thread leading to crash.
This change flushes the pp event thread queue during vm pre-release
before lending the io resources to the other vm.

Change-Id: I53b76e48bc15084aa5519409fae0e692f49e7558
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
2023-04-07 10:48:19 -07:00
Lakshmi Narayana Kalavala
02fcd809d2 disp: msm: sde: check for hardware ownership before histogram read
This change adds the check for hardware ownership before
reading the histogram statistics.

Change-Id: I0f811cef327c1dea9fb132d5fffd8da445e9d73f
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
2023-04-06 13:18:24 -07:00
Prabhanjan Kandula
ba7b5c08cc disp: msm: sde: avoid skipping of encoder reset in cwb disable
During cwb disable, encoder reset should be invoked to clean up
and release hw resources. This encoder reset should happen even
if cwb encoder TX_DONE is not successful to avoid rm rsvp leak.

Change-Id: I81353f19b69cb68d71f7d5b6477e37b6dab3ae00
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2023-04-05 19:10:10 -07:00
Christina Oliveira
85b87f5573 disp: msm: add feature-enabled check for output hw-fence sw-override
In the case that the hw-fence feature is enabled in the display driver dt
but disabled during initialization by the display driver when hw-fence
driver dependency is disabled, the existing check to determine
if the function pointer is available is not sufficient to determine
if the feature is enabled. This change adds an additional check to ensure
we do not set the output-fences sw-override unless hw-fencing is enabled.

Change-Id: I7f5000037e7b2a142224ef9c45b383e5c701350a
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2023-04-05 11:06:13 -07:00
qctecmdr
827af70599 Merge "disp: msm: sde: reset crop registers in PU cases" 2023-04-04 22:25:51 -07:00
Linux Build Service Account
65afd67e14 Merge "disp: msm: sde: Rename Gunyah RM APIs" into display-kernel.lnx.1.0 2023-04-04 22:11:39 -07:00
Shamika Joshi
eb2cae7569 disp: msm: sde: reset crop registers in PU cases
In back to back partial update cases with CWB the CROP
registers are not reset causing WB timeout in the
following sequence-
1) Nth commit WB_roi != LM_PU_roi, WB CROP registers
are programmed.
2) N+1th commit WB_roi == LM_PU_roi, WB CROP registers
are not cleared retaining old values.
Clear the WB CROP registers in the second case to fix
the issue.

Change-Id: If09a697f48ecaf5ee08d6313be444748d048b20d
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2023-04-04 13:48:33 -07:00
Lakshmi Narayana Kalavala
2751ec018d drm: msm: skip re-marking color processing features as dirty
Current implementation we apply the color properties when atomic begin
is called and mark features as dirty if crtc is not enabled.
For some of the non double buffered features in video mode we will
see a corruption. Change removes marking color properties as dirty
based on crtc on/off.

Change-Id: I4d93b14627d2bc06fcbca3ea9538a4baedb00e56
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
2023-03-28 18:09:49 -07:00
Prakruthi Deepak Heragu
09421907d8 disp: msm: sde: Rename Gunyah RM APIs
As we are merging upstream patches, resolve conflicts of namespaces in
downstream modules.

Change-Id: Id3af0de7102ddd92e312cb3cca10db9968974bcd
Signed-off-by: Prakruthi Deepak Heragu <quic_pheragu@quicinc.com>
Signed-off-by: Raviteja Tamatam<quic_travitej@quicinc.com>
2023-03-27 15:54:11 -07:00
qctecmdr
8c1b88916f Merge "disp: msm: sde: update hw-fence txq wr_ptr from hardware" 2023-03-16 19:58:44 -07:00
qctecmdr
81e8aa8d56 Merge "disp: msm: sde: remove avr state check early return" 2023-03-16 10:55:17 -07:00
Christina Oliveira
b5cbfa8358 disp: msm: sde: update hw-fence txq wr_ptr from hardware
This change adds hardware programming that will update the
txq wr_ptr upon output fence firing.

Change-Id: I79ff0ea5fb2b7f73a48bd70e3c8e71ea69fead95
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2023-03-15 12:53:37 -07:00
Mahadevan
7c8a28d45f disp: msm: sde: qos vote for all cpus during vm transition
For a proxy-scheduled VCPU like the TUI VM, assignment to a
physical core is a runtime decision made by the HLOS scheduler,
and it may change frequently. pm_qos vote added by PVM for
specific CPUs won't be sufficient for addressing irq latency.
This change updates votes for all possible CPUs during TVM
entry and also removes the vote during exit.

Change-Id: Iab5cb5f57e2389ee57689ba2ab69394376f59788
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
2023-03-13 14:54:15 -07:00
Nilaan Gunabalachandran
d483cbe62a disp: msm: sde: remove avr state check early return
After introducing avr step state, the driver checks for avr
state none before returning early. In the case where avr property
is not being set, this leads to skipping qsync programming.

This change removes this state check.

Change-Id: Ie277dd04b8913358135210131a99c598cf2145ba
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2023-03-13 10:48:57 -07:00
qctecmdr
1ca5ff7768 Merge "disp: msm: sde: use vzalloc for large allocations" 2023-03-12 21:39:22 -07:00
qctecmdr
7e688d492e Merge "disp: msm: sde: avoid VMID_TVM check during buf import in trusted-vm" 2023-03-12 08:29:59 -07:00
qctecmdr
c6dd1a40a9 Merge "disp: msm: sde: silence ppb horizontal width check" 2023-03-10 13:40:48 -08:00
qctecmdr
ef29262a3d Merge "disp: msm: sde: use rate limited print for crtc event thread" 2023-03-10 13:40:48 -08:00
Veera Sundaram Sankaran
428a27027d disp: msm: sde: avoid VMID_TVM check during buf import in trusted-vm
Both trusted-vm and secure-camera preview buffers uses the same
VMID_TVM. In primary-vm, the check is used to determine the camera
preview usecase and attach it to the correct device. This is not
necessary for trusted-vm as it can default to nested trusted-vm
context bank. Avoid the check while its in trusted-vm.

Change-Id: I4391a4a1da9dca5d1f4b1719733b8d4edc1900a8
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2023-03-08 20:39:10 -08:00
Nilaan Gunabalachandran
ecdf523387 disp: msm: sde: silence ppb horizontal width check
PPB size programming checks for the max horizontal width of the
panel by checking all available modes. In some DP usecases,
it is possible that this information is not ready at this point.
However, this is not an error, as by default driver will set the
maximum size.

This change reduces the error log to a debug warning.

Change-Id: Ieb63524457db410a2569682f2c3863e082c60805
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2023-03-06 14:00:19 -08:00
Gopikrishnaiah Anand
e556c1083f disp: msm: sde: Split demura config into two blobs
Some of the demura config parameters are single buffered. When demura
config is reprogrammed by user-space clients, single buffered updates
can cause artifacts on screen. Change splits the double buffered and
single buffered configs into different payloads to allow user-space
to update double buffered config.

Change-Id: I493b86944f7c2d630dcc1b863174e816cf8c82ed
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
2023-03-05 02:31:33 -08:00
qctecmdr
c800377c04 Merge "disp: msm: sde: flush event thread work before vm transition" 2023-03-01 17:29:50 -08:00
Nilaan Gunabalachandran
68d3217032 disp: msm: sde: use rate limited print for crtc event thread
When the vblank event overflow error log occurs due to an inability
to handle incoming vblanks, it is posisble to continuously flood
with error print logs. This could cause the CPU to become further
blocked and creates a cycle of failed callbacks and error logging.

This change changes the overflow log in the crtc event thread to
rate limited.

Change-Id: Ie2d77689c8fa989cf3a294f973851b7dacef098b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2023-03-01 16:22:58 -05:00
Raviteja Tamatam
b470c15742 disp: msm: sde: flush event thread work before vm transition
During VM transition there should be no pending crtc event
thread operations in progress to avoid any resource access
after vm release. Flush the event thread worker in prerelease
to ensure it.

Change-Id: I51d6c78a702235ee926c9ff6415c8d69f74b5929
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2023-03-01 10:27:01 -08:00
Anjaneya Prasad Musunuri
9452039e4a disp: msm: sde: use vzalloc for large allocations
Large allocations using kvzalloc can lead to timeouts.
This updates the allocation calls accordingly to use
vzalloc to remove requirements on physically
contiguous memory.

Change-Id: I437913b3bf2e46bfeeb2c511bdfc153470fcbc24
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
2023-03-01 03:31:31 -08:00
Grace An
3564a2c6f2 disp: msm: sde: update output_fence hw programming for pineapple
Starting pineapple, the output_fence trigger_sel register is updated to be
more controllable. Instead of hardware choosing the output fence timing
based on detecting if panel is in video/cmd mode, this is explicitly set
by software. Add support in display driver for to correctly write to
trigger_sel register for video mode.

Change-Id: I76d8cfb644cebfd2f34f3017fc779b87fc52db1a
Signed-off-by: Grace An <quic_gracan@quicinc.com>
2023-02-28 09:16:27 -08:00
Prabhanjan Kandula
1fdd965d0b disp: msm: sde: fix physical encoder spinlock usage
While same spinlock can be used to protect a critical section
in both irq-handler and in non-irq context, in non-irq context
it is mandatory to use irqsave version of locking api to disable
irqs locally on the particular cpu. Otherwise, this could lead
to a deadlock if a non-irq thread holding the spinlock and irq
handler is scheduled on same cpu.

This change replaces physical encoder spinlock locking with
irqsave version of locking api in the non-irq context.

Change-Id: If73b4c995b75e9499d79fbe969d426427fd3a9d1
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2023-02-24 05:40:08 -08:00
Ping Li
5176514114 drm: msm: skip the color processing programming if crtc is not enabled
Add check to avoid programming the color processing HW if sde_crtc is
not enabled.

Change-Id: I7ffd341147f0caebefb647486a139df5c0aeab31
Signed-off-by: Ping Li <quic_pingli@quicinc.com>
2023-02-21 03:54:33 -08:00
qctecmdr
32f7d3149a Merge "disp: msm: sde: add support for ppb size programming" 2023-02-20 11:19:36 -08:00
Nilaan Gunabalachandran
6860fee2c8 disp: msm: sde: update vblank notify to use spin_lock_irqsave
If the event thread worker processing vblank_notify_work is
scheduled out while holding spinlock to process the ctl-done
interrupt, it will result in a deadlock as the
frame_event_callback requires the same spinlock.

This change updates vblank notify work to use spin lock irqsave &
irqrestore to ensure we don't hit this case.

Change-Id: I96bcb3b21bf9426016f5b3ae43f7d1f8581a8483
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2023-02-16 17:26:43 -05:00
Prabhanjan Kandula
a2f3cba8ca disp: msm: sde: add support for ppb size programming
MDSS 10.0 onwards, hw supports programming of pingpong
latency buffer size based on the resolution of display.
In prior targets full size of the latency buffer is used.
This change adds required support in sde driver to program
the pingpong buffer size based on systems recommended
latency lines requirement and the display resolution.

Change-Id: I172b19e5b397eb86190de57fed36f24cd67d2207
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2023-02-14 11:27:23 -08:00
Veera Sundaram Sankaran
f6284fb3fa disp: msm: sde: add eventlog tags in prepare_for_kickoff
Add case tags in eventlogs in cmd_prepare_for_kickoff to
help in differentiating the logs in this function.

Change-Id: Idce10e715c77340175d124ec3ef7ecc30c95a0af
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2023-02-10 14:04:30 -08:00
Veera Sundaram Sankaran
ae24e846e1 disp: msm: sde: enable EPT_FPS feature for cmd mode in pineapple target
Enable the Expected Present Time feature through the FPS for cmd
mode panels in pineapple target.

Change-Id: Ib1e3c7aaf5329004ffdf89672e919228931468ee
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2023-02-09 11:10:08 -08:00
Shirisha Kollapuram
0d6e7e269a disp: msm: sde: program the start window based on "EPT_FPS"
Introduce a new connector property called “EPT_FPS” for the cmd
mode panels. User space will set the “EPT_FPS” based on the
intended content fps, relative to the last retire fence timestamp
as calculated by Surface flinger. Program start window based
on the Expected Present Time fps.

Change-Id: I24b93e0f941af9fb2422b2484328254d04a1acbe
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2023-02-09 11:10:08 -08:00